arch/powerpc/oprofile/op_model_fsl_booke.c

   1 /*
   2  * arch/powerpc/oprofile/op_model_fsl_booke.c
   3  *
   4  * Freescale Book-E oprofile support, based on ppc64 oprofile support
   5  * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
   6  *
   7  * Copyright (c) 2004 Freescale Semiconductor, Inc
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version
  15  * 2 of the License, or (at your option) any later version.
  16  */
  17
  18 #include <linux/oprofile.h>
  19 #include <linux/init.h>
  20 #include <linux/smp.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/system.h>
  23 #include <asm/processor.h>
  24 #include <asm/cputable.h>
  25 #include <asm/reg_booke.h>
  26 #include <asm/page.h>
  27 #include <asm/pmc.h>
  28 #include <asm/oprofile_impl.h>
  29
  30 static unsigned long reset_value[OP_MAX_COUNTER];
  31
  32 static int num_counters;
  33 static int oprofile_running;
  34
  35 static void init_pmc_stop(int ctr)
  36 {
  37         u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
  38                         PMLCA_FCM1 | PMLCA_FCM0);
  39         u32 pmlcb = 0;
  40
  41         switch (ctr) {
  42                 case 0:
  43                         mtpmr(PMRN_PMLCA0, pmlca);
  44                         mtpmr(PMRN_PMLCB0, pmlcb);
  45                         break;
  46                 case 1:
  47                         mtpmr(PMRN_PMLCA1, pmlca);
  48                         mtpmr(PMRN_PMLCB1, pmlcb);
  49                         break;
  50                 case 2:
  51                         mtpmr(PMRN_PMLCA2, pmlca);
  52                         mtpmr(PMRN_PMLCB2, pmlcb);
  53                         break;
  54                 case 3:
  55                         mtpmr(PMRN_PMLCA3, pmlca);
  56                         mtpmr(PMRN_PMLCB3, pmlcb);
  57                         break;
  58                 default:
  59                         panic("Bad ctr number!\n");
  60         }
  61 }
  62
  63 static void set_pmc_event(int ctr, int event)
  64 {
  65         u32 pmlca;
  66
  67         pmlca = get_pmlca(ctr);
  68
  69         pmlca = (pmlca & ~PMLCA_EVENT_MASK) |
  70                 ((event << PMLCA_EVENT_SHIFT) &
  71                  PMLCA_EVENT_MASK);
  72
  73         set_pmlca(ctr, pmlca);
  74 }
  75
  76 static void set_pmc_user_kernel(int ctr, int user, int kernel)
  77 {
  78         u32 pmlca;
  79
  80         pmlca = get_pmlca(ctr);
  81
  82         if(user)
  83                 pmlca &= ~PMLCA_FCU;
  84         else
  85                 pmlca |= PMLCA_FCU;
  86
  87         if(kernel)
  88                 pmlca &= ~PMLCA_FCS;
  89         else
  90                 pmlca |= PMLCA_FCS;
  91
  92         set_pmlca(ctr, pmlca);
  93 }
  94
  95 static void set_pmc_marked(int ctr, int mark0, int mark1)
  96 {
  97         u32 pmlca = get_pmlca(ctr);
  98
  99         if(mark0)
 100                 pmlca &= ~PMLCA_FCM0;
 101         else
 102                 pmlca |= PMLCA_FCM0;
 103
 104         if(mark1)
 105                 pmlca &= ~PMLCA_FCM1;
 106         else
 107                 pmlca |= PMLCA_FCM1;
 108
 109         set_pmlca(ctr, pmlca);
 110 }
 111
 112 static void pmc_start_ctr(int ctr, int enable)
 113 {
 114         u32 pmlca = get_pmlca(ctr);
 115
 116         pmlca &= ~PMLCA_FC;
 117
 118         if (enable)
 119                 pmlca |= PMLCA_CE;
 120         else
 121                 pmlca &= ~PMLCA_CE;
 122
 123         set_pmlca(ctr, pmlca);
 124 }
 125
 126 static void pmc_start_ctrs(int enable)
 127 {
 128         u32 pmgc0 = mfpmr(PMRN_PMGC0);
 129
 130         pmgc0 &= ~PMGC0_FAC;
 131         pmgc0 |= PMGC0_FCECE;
 132
 133         if (enable)
 134                 pmgc0 |= PMGC0_PMIE;
 135         else
 136                 pmgc0 &= ~PMGC0_PMIE;
 137
 138         mtpmr(PMRN_PMGC0, pmgc0);
 139 }
 140
 141 static void pmc_stop_ctrs(void)
 142 {
 143         u32 pmgc0 = mfpmr(PMRN_PMGC0);
 144
 145         pmgc0 |= PMGC0_FAC;
 146
 147         pmgc0 &= ~(PMGC0_PMIE | PMGC0_FCECE);
 148
 149         mtpmr(PMRN_PMGC0, pmgc0);
 150 }
 151
 152 static void dump_pmcs(void)
 153 {
 154         printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0));
 155         printk("pmc\t\tpmlca\t\tpmlcb\n");
 156         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0),
 157                         mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0));
 158         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1),
 159                         mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1));
 160         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2),
 161                         mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2));
 162         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3),
 163                         mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
 164 }
 165
 166 static void fsl_booke_cpu_setup(struct op_counter_config *ctr)
 167 {
 168         int i;
 169
 170         /* freeze all counters */
 171         pmc_stop_ctrs();
 172
 173         for (i = 0;i < num_counters;i++) {
 174                 init_pmc_stop(i);
 175
 176                 set_pmc_event(i, ctr[i].event);
 177
 178                 set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
 179         }
 180 }
 181
 182 static void fsl_booke_reg_setup(struct op_counter_config *ctr,
 183                              struct op_system_config *sys,
 184                              int num_ctrs)
 185 {
 186         int i;
 187
 188         num_counters = num_ctrs;
 189
 190         /* Our counters count up, and "count" refers to
 191          * how much before the next interrupt, and we interrupt
 192          * on overflow.  So we calculate the starting value
 193          * which will give us "count" until overflow.
 194          * Then we set the events on the enabled counters */
 195         for (i = 0; i < num_counters; ++i)
 196                 reset_value[i] = 0x80000000UL - ctr[i].count;
 197
 198 }
 199
 200 static void fsl_booke_start(struct op_counter_config *ctr)
 201 {
 202         int i;
 203
 204         mtmsr(mfmsr() | MSR_PMM);
 205
 206         for (i = 0; i < num_counters; ++i) {
 207                 if (ctr[i].enabled) {
 208                         ctr_write(i, reset_value[i]);
 209                         /* Set each enabled counter to only
 210                          * count when the Mark bit is *not* set */
 211                         set_pmc_marked(i, 1, 0);
 212                         pmc_start_ctr(i, 1);
 213                 } else {
 214                         ctr_write(i, 0);
 215
 216                         /* Set the ctr to be stopped */
 217                         pmc_start_ctr(i, 0);
 218                 }
 219         }
 220
 221         /* Clear the freeze bit, and enable the interrupt.
 222          * The counters won't actually start until the rfi clears
 223          * the PMM bit */
 224         pmc_start_ctrs(1);
 225
 226         oprofile_running = 1;
 227
 228         pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
 229                         mfpmr(PMRN_PMGC0));
 230 }
 231
 232 static void fsl_booke_stop(void)
 233 {
 234         /* freeze counters */
 235         pmc_stop_ctrs();
 236
 237         oprofile_running = 0;
 238
 239         pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
 240                         mfpmr(PMRN_PMGC0));
 241
 242         mb();
 243 }
 244
 245
 246 static void fsl_booke_handle_interrupt(struct pt_regs *regs,
 247                                     struct op_counter_config *ctr)
 248 {
 249         unsigned long pc;
 250         int is_kernel;
 251         int val;
 252         int i;
 253
 254         /* set the PMM bit (see comment below) */
 255         mtmsr(mfmsr() | MSR_PMM);
 256
 257         pc = regs->nip;
 258         is_kernel = is_kernel_addr(pc);
 259
 260         for (i = 0; i < num_counters; ++i) {
 261                 val = ctr_read(i);
 262                 if (val < 0) {
 263                         if (oprofile_running && ctr[i].enabled) {
 264                                 oprofile_add_ext_sample(pc, regs, i, is_kernel);
 265                                 ctr_write(i, reset_value[i]);
 266                         } else {
 267                                 ctr_write(i, 0);
 268                         }
 269                 }
 270         }
 271
 272         /* The freeze bit was set by the interrupt. */
 273         /* Clear the freeze bit, and reenable the interrupt.
 274          * The counters won't actually start until the rfi clears
 275          * the PMM bit */
 276         pmc_start_ctrs(1);
 277 }
 278
 279 struct op_powerpc_model op_model_fsl_booke = {
 280         .reg_setup              = fsl_booke_reg_setup,
 281         .cpu_setup              = fsl_booke_cpu_setup,
 282         .start                  = fsl_booke_start,
 283         .stop                   = fsl_booke_stop,
 284         .handle_interrupt       = fsl_booke_handle_interrupt,
 285 };