arch/powerpc/boot/dts/mpc8568mds.dts

   1 /*
   2  * MPC8568E MDS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 /*
  14 /memreserve/    00000000 1000000;
  15 */
  16
  17 / {
  18         model = "MPC8568EMDS";
  19         compatible = "MPC8568EMDS", "MPC85xxMDS";
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 PowerPC,8568@0 {
  28                         device_type = "cpu";
  29                         reg = <0>;
  30                         d-cache-line-size = <20>;       // 32 bytes
  31                         i-cache-line-size = <20>;       // 32 bytes
  32                         d-cache-size = <8000>;          // L1, 32K
  33                         i-cache-size = <8000>;          // L1, 32K
  34                         timebase-frequency = <0>;
  35                         bus-frequency = <0>;
  36                         clock-frequency = <0>;
  37                         32-bit;
  38                 };
  39         };
  40
  41         memory {
  42                 device_type = "memory";
  43                 reg = <00000000 10000000>;
  44         };
  45
  46         bcsr@f8000000 {
  47                 device_type = "board-control";
  48                 reg = <f8000000 8000>;
  49         };
  50
  51         soc8568@e0000000 {
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 #interrupt-cells = <2>;
  55                 device_type = "soc";
  56                 ranges = <0 e0000000 00100000>;
  57                 reg = <e0000000 00100000>;
  58                 bus-frequency = <0>;
  59
  60                 i2c@3000 {
  61                         device_type = "i2c";
  62                         compatible = "fsl-i2c";
  63                         reg = <3000 100>;
  64                         interrupts = <1b 2>;
  65                         interrupt-parent = <&mpic>;
  66                         dfsrr;
  67                 };
  68
  69                 i2c@3100 {
  70                         device_type = "i2c";
  71                         compatible = "fsl-i2c";
  72                         reg = <3100 100>;
  73                         interrupts = <1b 2>;
  74                         interrupt-parent = <&mpic>;
  75                         dfsrr;
  76                 };
  77
  78                 mdio@24520 {
  79                         #address-cells = <1>;
  80                         #size-cells = <0>;
  81                         device_type = "mdio";
  82                         compatible = "gianfar";
  83                         reg = <24520 20>;
  84                         phy0: ethernet-phy@0 {
  85                                 interrupt-parent = <&mpic>;
  86                                 interrupts = <31 1>;
  87                                 reg = <0>;
  88                                 device_type = "ethernet-phy";
  89                         };
  90                         phy1: ethernet-phy@1 {
  91                                 interrupt-parent = <&mpic>;
  92                                 interrupts = <32 1>;
  93                                 reg = <1>;
  94                                 device_type = "ethernet-phy";
  95                         };
  96                         phy2: ethernet-phy@2 {
  97                                 interrupt-parent = <&mpic>;
  98                                 interrupts = <31 1>;
  99                                 reg = <2>;
 100                                 device_type = "ethernet-phy";
 101                         };
 102                         phy3: ethernet-phy@3 {
 103                                 interrupt-parent = <&mpic>;
 104                                 interrupts = <32 1>;
 105                                 reg = <3>;
 106                                 device_type = "ethernet-phy";
 107                         };
 108                 };
 109
 110                 ethernet@24000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         device_type = "network";
 114                         model = "eTSEC";
 115                         compatible = "gianfar";
 116                         reg = <24000 1000>;
 117                         mac-address = [ 00 00 00 00 00 00 ];
 118                         interrupts = <d 2 e 2 12 2>;
 119                         interrupt-parent = <&mpic>;
 120                         phy-handle = <&phy2>;
 121                 };
 122
 123                 ethernet@25000 {
 124                         #address-cells = <1>;
 125                         #size-cells = <0>;
 126                         device_type = "network";
 127                         model = "eTSEC";
 128                         compatible = "gianfar";
 129                         reg = <25000 1000>;
 130                         mac-address = [ 00 00 00 00 00 00];
 131                         interrupts = <13 2 14 2 18 2>;
 132                         interrupt-parent = <&mpic>;
 133                         phy-handle = <&phy3>;
 134                 };
 135
 136                 serial@4500 {
 137                         device_type = "serial";
 138                         compatible = "ns16550";
 139                         reg = <4500 100>;
 140                         clock-frequency = <0>;
 141                         interrupts = <1a 2>;
 142                         interrupt-parent = <&mpic>;
 143                 };
 144
 145                 serial@4600 {
 146                         device_type = "serial";
 147                         compatible = "ns16550";
 148                         reg = <4600 100>;
 149                         clock-frequency = <0>;
 150                         interrupts = <1a 2>;
 151                         interrupt-parent = <&mpic>;
 152                 };
 153
 154                 crypto@30000 {
 155                         device_type = "crypto";
 156                         model = "SEC2";
 157                         compatible = "talitos";
 158                         reg = <30000 f000>;
 159                         interrupts = <1d 2>;
 160                         interrupt-parent = <&mpic>;
 161                         num-channels = <4>;
 162                         channel-fifo-len = <18>;
 163                         exec-units-mask = <000000fe>;
 164                         descriptor-types-mask = <012b0ebf>;
 165                 };
 166
 167                 mpic: pic@40000 {
 168                         clock-frequency = <0>;
 169                         interrupt-controller;
 170                         #address-cells = <0>;
 171                         #interrupt-cells = <2>;
 172                         reg = <40000 40000>;
 173                         built-in;
 174                         compatible = "chrp,open-pic";
 175                         device_type = "open-pic";
 176                         big-endian;
 177                 };
 178                 par_io@e0100 {
 179                         reg = <e0100 100>;
 180                         device_type = "par_io";
 181                         num-ports = <7>;
 182
 183                         pio1: ucc_pin@01 {
 184                                 pio-map = <
 185                         /* port  pin  dir  open_drain  assignment  has_irq */
 186                                         4  0a  1  0  2  0       /* TxD0 */
 187                                         4  09  1  0  2  0       /* TxD1 */
 188                                         4  08  1  0  2  0       /* TxD2 */
 189                                         4  07  1  0  2  0       /* TxD3 */
 190                                         4  17  1  0  2  0       /* TxD4 */
 191                                         4  16  1  0  2  0       /* TxD5 */
 192                                         4  15  1  0  2  0       /* TxD6 */
 193                                         4  14  1  0  2  0       /* TxD7 */
 194                                         4  0f  2  0  2  0       /* RxD0 */
 195                                         4  0e  2  0  2  0       /* RxD1 */
 196                                         4  0d  2  0  2  0       /* RxD2 */
 197                                         4  0c  2  0  2  0       /* RxD3 */
 198                                         4  1d  2  0  2  0       /* RxD4 */
 199                                         4  1c  2  0  2  0       /* RxD5 */
 200                                         4  1b  2  0  2  0       /* RxD6 */
 201                                         4  1a  2  0  2  0       /* RxD7 */
 202                                         4  0b  1  0  2  0       /* TX_EN */
 203                                         4  18  1  0  2  0       /* TX_ER */
 204                                         4  0f  2  0  2  0       /* RX_DV */
 205                                         4  1e  2  0  2  0       /* RX_ER */
 206                                         4  11  2  0  2  0       /* RX_CLK */
 207                                         4  13  1  0  2  0       /* GTX_CLK */
 208                                         1  1f  2  0  3  0>;     /* GTX125 */
 209                         };
 210                         pio2: ucc_pin@02 {
 211                                 pio-map = <
 212                         /* port  pin  dir  open_drain  assignment  has_irq */
 213                                         5  0a 1  0  2  0   /* TxD0 */
 214                                         5  09 1  0  2  0   /* TxD1 */
 215                                         5  08 1  0  2  0   /* TxD2 */
 216                                         5  07 1  0  2  0   /* TxD3 */
 217                                         5  17 1  0  2  0   /* TxD4 */
 218                                         5  16 1  0  2  0   /* TxD5 */
 219                                         5  15 1  0  2  0   /* TxD6 */
 220                                         5  14 1  0  2  0   /* TxD7 */
 221                                         5  0f 2  0  2  0   /* RxD0 */
 222                                         5  0e 2  0  2  0   /* RxD1 */
 223                                         5  0d 2  0  2  0   /* RxD2 */
 224                                         5  0c 2  0  2  0   /* RxD3 */
 225                                         5  1d 2  0  2  0   /* RxD4 */
 226                                         5  1c 2  0  2  0   /* RxD5 */
 227                                         5  1b 2  0  2  0   /* RxD6 */
 228                                         5  1a 2  0  2  0   /* RxD7 */
 229                                         5  0b 1  0  2  0   /* TX_EN */
 230                                         5  18 1  0  2  0   /* TX_ER */
 231                                         5  10 2  0  2  0   /* RX_DV */
 232                                         5  1e 2  0  2  0   /* RX_ER */
 233                                         5  11 2  0  2  0   /* RX_CLK */
 234                                         5  13 1  0  2  0   /* GTX_CLK */
 235                                         1  1f 2  0  3  0   /* GTX125 */
 236                                         4  06 3  0  2  0   /* MDIO */
 237                                         4  05 1  0  2  0>; /* MDC */
 238                         };
 239                 };
 240         };
 241
 242         qe@e0080000 {
 243                 #address-cells = <1>;
 244                 #size-cells = <1>;
 245                 device_type = "qe";
 246                 model = "QE";
 247                 ranges = <0 e0080000 00040000>;
 248                 reg = <e0080000 480>;
 249                 brg-frequency = <0>;
 250                 bus-frequency = <179A7B00>;
 251
 252                 muram@10000 {
 253                         device_type = "muram";
 254                         ranges = <0 00010000 0000c000>;
 255
 256                         data-only@0{
 257                                 reg = <0 c000>;
 258                         };
 259                 };
 260
 261                 spi@4c0 {
 262                         device_type = "spi";
 263                         compatible = "fsl_spi";
 264                         reg = <4c0 40>;
 265                         interrupts = <2>;
 266                         interrupt-parent = <&qeic>;
 267                         mode = "cpu";
 268                 };
 269
 270                 spi@500 {
 271                         device_type = "spi";
 272                         compatible = "fsl_spi";
 273                         reg = <500 40>;
 274                         interrupts = <1>;
 275                         interrupt-parent = <&qeic>;
 276                         mode = "cpu";
 277                 };
 278
 279                 ucc@2000 {
 280                         device_type = "network";
 281                         compatible = "ucc_geth";
 282                         model = "UCC";
 283                         device-id = <1>;
 284                         reg = <2000 200>;
 285                         interrupts = <20>;
 286                         interrupt-parent = <&qeic>;
 287                         mac-address = [ 00 04 9f 00 23 23 ];
 288                         rx-clock = <0>;
 289                         tx-clock = <19>;
 290                         phy-handle = <&qe_phy0>;
 291                         pio-handle = <&pio1>;
 292                 };
 293
 294                 ucc@3000 {
 295                         device_type = "network";
 296                         compatible = "ucc_geth";
 297                         model = "UCC";
 298                         device-id = <2>;
 299                         reg = <3000 200>;
 300                         interrupts = <21>;
 301                         interrupt-parent = <&qeic>;
 302                         mac-address = [ 00 11 22 33 44 55 ];
 303                         rx-clock = <0>;
 304                         tx-clock = <14>;
 305                         phy-handle = <&qe_phy1>;
 306                         pio-handle = <&pio2>;
 307                 };
 308
 309                 mdio@2120 {
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                         reg = <2120 18>;
 313                         device_type = "mdio";
 314                         compatible = "ucc_geth_phy";
 315
 316                         /* These are the same PHYs as on
 317                          * gianfar's MDIO bus */
 318                         qe_phy0: ethernet-phy@00 {
 319                                 interrupt-parent = <&mpic>;
 320                                 interrupts = <31 1>;
 321                                 reg = <0>;
 322                                 device_type = "ethernet-phy";
 323                                 interface = <6>; //ENET_1000_GMII
 324                         };
 325                         qe_phy1: ethernet-phy@01 {
 326                                 interrupt-parent = <&mpic>;
 327                                 interrupts = <32 1>;
 328                                 reg = <1>;
 329                                 device_type = "ethernet-phy";
 330                                 interface = <6>;
 331                         };
 332                         qe_phy2: ethernet-phy@02 {
 333                                 interrupt-parent = <&mpic>;
 334                                 interrupts = <31 1>;
 335                                 reg = <2>;
 336                                 device_type = "ethernet-phy";
 337                                 interface = <6>; //ENET_1000_GMII
 338                         };
 339                         qe_phy3: ethernet-phy@03 {
 340                                 interrupt-parent = <&mpic>;
 341                                 interrupts = <32 1>;
 342                                 reg = <3>;
 343                                 device_type = "ethernet-phy";
 344                                 interface = <6>; //ENET_1000_GMII
 345                         };
 346                 };
 347
 348                 qeic: qeic@80 {
 349                         interrupt-controller;
 350                         device_type = "qeic";
 351                         #address-cells = <0>;
 352                         #interrupt-cells = <1>;
 353                         reg = <80 80>;
 354                         built-in;
 355                         big-endian;
 356                         interrupts = <1e 2 1e 2>; //high:30 low:30
 357                         interrupt-parent = <&mpic>;
 358                 };
 359
 360         };
 361 };