arch/powerpc/boot/dts/mpc8560ads.dts

   1 /*
   2  * MPC8560 ADS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8560ADS";
  15         compatible = "MPC8560ADS", "MPC85xxADS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8560@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <04ead9a0>;
  31                         bus-frequency = <13ab6680>;
  32                         clock-frequency = <312c8040>;
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 10000000>;
  40         };
  41
  42         soc8560@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00000200>;
  49                 bus-frequency = <13ab6680>;
  50
  51                 mdio@24520 {
  52                         device_type = "mdio";
  53                         compatible = "gianfar";
  54                         reg = <24520 20>;
  55                         #address-cells = <1>;
  56                         #size-cells = <0>;
  57                         phy0: ethernet-phy@0 {
  58                                 interrupt-parent = <&mpic>;
  59                                 interrupts = <35 1>;
  60                                 reg = <0>;
  61                                 device_type = "ethernet-phy";
  62                         };
  63                         phy1: ethernet-phy@1 {
  64                                 interrupt-parent = <&mpic>;
  65                                 interrupts = <35 1>;
  66                                 reg = <1>;
  67                                 device_type = "ethernet-phy";
  68                         };
  69                         phy2: ethernet-phy@2 {
  70                                 interrupt-parent = <&mpic>;
  71                                 interrupts = <37 1>;
  72                                 reg = <2>;
  73                                 device_type = "ethernet-phy";
  74                         };
  75                         phy3: ethernet-phy@3 {
  76                                 interrupt-parent = <&mpic>;
  77                                 interrupts = <37 1>;
  78                                 reg = <3>;
  79                                 device_type = "ethernet-phy";
  80                         };
  81                 };
  82
  83                 ethernet@24000 {
  84                         device_type = "network";
  85                         model = "TSEC";
  86                         compatible = "gianfar";
  87                         reg = <24000 1000>;
  88                         address = [ 00 00 0C 00 00 FD ];
  89                         interrupts = <d 2 e 2 12 2>;
  90                         interrupt-parent = <&mpic>;
  91                         phy-handle = <&phy0>;
  92                 };
  93
  94                 ethernet@25000 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         device_type = "network";
  98                         model = "TSEC";
  99                         compatible = "gianfar";
 100                         reg = <25000 1000>;
 101                         address = [ 00 00 0C 00 01 FD ];
 102                         interrupts = <13 2 14 2 18 2>;
 103                         interrupt-parent = <&mpic>;
 104                         phy-handle = <&phy1>;
 105                 };
 106
 107                 pci@8000 {
 108                         #interrupt-cells = <1>;
 109                         #size-cells = <2>;
 110                         #address-cells = <3>;
 111                         compatible = "85xx";
 112                         device_type = "pci";
 113                         reg = <8000 400>;
 114                         clock-frequency = <3f940aa>;
 115                         interrupt-map-mask = <f800 0 0 7>;
 116                         interrupt-map = <
 117
 118                                         /* IDSEL 0x2 */
 119                                          1000 0 0 1 &mpic 31 1
 120                                          1000 0 0 2 &mpic 32 1
 121                                          1000 0 0 3 &mpic 33 1
 122                                          1000 0 0 4 &mpic 34 1
 123
 124                                         /* IDSEL 0x3 */
 125                                          1800 0 0 1 &mpic 34 1
 126                                          1800 0 0 2 &mpic 31 1
 127                                          1800 0 0 3 &mpic 32 1
 128                                          1800 0 0 4 &mpic 33 1
 129
 130                                         /* IDSEL 0x4 */
 131                                          2000 0 0 1 &mpic 33 1
 132                                          2000 0 0 2 &mpic 34 1
 133                                          2000 0 0 3 &mpic 31 1
 134                                          2000 0 0 4 &mpic 32 1
 135
 136                                         /* IDSEL 0x5  */
 137                                          2800 0 0 1 &mpic 32 1
 138                                          2800 0 0 2 &mpic 33 1
 139                                          2800 0 0 3 &mpic 34 1
 140                                          2800 0 0 4 &mpic 31 1
 141
 142                                         /* IDSEL 12 */
 143                                          6000 0 0 1 &mpic 31 1
 144                                          6000 0 0 2 &mpic 32 1
 145                                          6000 0 0 3 &mpic 33 1
 146                                          6000 0 0 4 &mpic 34 1
 147
 148                                         /* IDSEL 13 */
 149                                          6800 0 0 1 &mpic 34 1
 150                                          6800 0 0 2 &mpic 31 1
 151                                          6800 0 0 3 &mpic 32 1
 152                                          6800 0 0 4 &mpic 33 1
 153
 154                                         /* IDSEL 14*/
 155                                          7000 0 0 1 &mpic 33 1
 156                                          7000 0 0 2 &mpic 34 1
 157                                          7000 0 0 3 &mpic 31 1
 158                                          7000 0 0 4 &mpic 32 1
 159
 160                                         /* IDSEL 15 */
 161                                          7800 0 0 1 &mpic 32 1
 162                                          7800 0 0 2 &mpic 33 1
 163                                          7800 0 0 3 &mpic 34 1
 164                                          7800 0 0 4 &mpic 31 1
 165
 166                                         /* IDSEL 18 */
 167                                          9000 0 0 1 &mpic 31 1
 168                                          9000 0 0 2 &mpic 32 1
 169                                          9000 0 0 3 &mpic 33 1
 170                                          9000 0 0 4 &mpic 34 1
 171
 172                                         /* IDSEL 19 */
 173                                          9800 0 0 1 &mpic 34 1
 174                                          9800 0 0 2 &mpic 31 1
 175                                          9800 0 0 3 &mpic 32 1
 176                                          9800 0 0 4 &mpic 33 1
 177
 178                                         /* IDSEL 20 */
 179                                          a000 0 0 1 &mpic 33 1
 180                                          a000 0 0 2 &mpic 34 1
 181                                          a000 0 0 3 &mpic 31 1
 182                                          a000 0 0 4 &mpic 32 1
 183
 184                                         /* IDSEL 21 */
 185                                          a800 0 0 1 &mpic 32 1
 186                                          a800 0 0 2 &mpic 33 1
 187                                          a800 0 0 3 &mpic 34 1
 188                                          a800 0 0 4 &mpic 31 1>;
 189
 190                         interrupt-parent = <&mpic>;
 191                         interrupts = <8 0>;
 192                         bus-range = <0 0>;
 193                         ranges = <02000000 0 80000000 80000000 0 20000000
 194                                   01000000 0 00000000 e2000000 0 01000000>;
 195                 };
 196
 197                 mpic: pic@40000 {
 198                         interrupt-controller;
 199                         #address-cells = <0>;
 200                         #interrupt-cells = <2>;
 201                         reg = <40000 40000>;
 202                         built-in;
 203                         device_type = "open-pic";
 204                 };
 205
 206                 cpm@e0000000 {
 207                         #address-cells = <1>;
 208                         #size-cells = <1>;
 209                         #interrupt-cells = <2>;
 210                         device_type = "cpm";
 211                         model = "CPM2";
 212                         ranges = <0 0 c0000>;
 213                         reg = <80000 40000>;
 214                         command-proc = <919c0>;
 215                         brg-frequency = <9d5b340>;
 216
 217                         cpmpic: pic@90c00 {
 218                                 interrupt-controller;
 219                                 #address-cells = <0>;
 220                                 #interrupt-cells = <2>;
 221                                 interrupts = <1e 0>;
 222                                 interrupt-parent = <&mpic>;
 223                                 reg = <90c00 80>;
 224                                 built-in;
 225                                 device_type = "cpm-pic";
 226                         };
 227
 228                         scc@91a00 {
 229                                 device_type = "serial";
 230                                 compatible = "cpm_uart";
 231                                 model = "SCC";
 232                                 device-id = <1>;
 233                                 reg = <91a00 20 88000 100>;
 234                                 clock-setup = <00ffffff 0>;
 235                                 rx-clock = <1>;
 236                                 tx-clock = <1>;
 237                                 current-speed = <1c200>;
 238                                 interrupts = <28 8>;
 239                                 interrupt-parent = <&cpmpic>;
 240                         };
 241
 242                         scc@91a20 {
 243                                 device_type = "serial";
 244                                 compatible = "cpm_uart";
 245                                 model = "SCC";
 246                                 device-id = <2>;
 247                                 reg = <91a20 20 88100 100>;
 248                                 clock-setup = <ff00ffff 90000>;
 249                                 rx-clock = <2>;
 250                                 tx-clock = <2>;
 251                                 current-speed = <1c200>;
 252                                 interrupts = <29 8>;
 253                                 interrupt-parent = <&cpmpic>;
 254                         };
 255
 256                         fcc@91320 {
 257                                 device_type = "network";
 258                                 compatible = "fs_enet";
 259                                 model = "FCC";
 260                                 device-id = <2>;
 261                                 reg = <91320 20 88500 100 913a0 30>;
 262                                 mac-address = [ 00 00 0C 00 02 FD ];
 263                                 clock-setup = <ff00ffff 250000>;
 264                                 rx-clock = <15>;
 265                                 tx-clock = <16>;
 266                                 interrupts = <21 8>;
 267                                 interrupt-parent = <&cpmpic>;
 268                                 phy-handle = <&phy2>;
 269                         };
 270
 271                         fcc@91340 {
 272                                 device_type = "network";
 273                                 compatible = "fs_enet";
 274                                 model = "FCC";
 275                                 device-id = <3>;
 276                                 reg = <91340 20 88600 100 913d0 30>;
 277                                 mac-address = [ 00 00 0C 00 03 FD ];
 278                                 clock-setup = <ffff00ff 3700>;
 279                                 rx-clock = <17>;
 280                                 tx-clock = <18>;
 281                                 interrupts = <22 8>;
 282                                 interrupt-parent = <&cpmpic>;
 283                                 phy-handle = <&phy3>;
 284                         };
 285                 };
 286         };
 287 };