arch/powerpc/boot/dts/fsl/b4si-post.dtsi

   1 /*
   2  * B4420 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * This software is provided by Freescale Semiconductor "as is" and any
  24  * express or implied warranties, including, but not limited to, the implied
  25  * warranties of merchantability and fitness for a particular purpose are
  26  * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27  * direct, indirect, incidental, special, exemplary, or consequential damages
  28  * (including, but not limited to, procurement of substitute goods or services;
  29  * loss of use, data, or profits; or business interruption) however caused and
  30  * on any theory of liability, whether in contract, strict liability, or tort
  31  * (including negligence or otherwise) arising in any way out of the use of
  32  * this software, even if advised of the possibility of such damage.
  33  */
  34
  35 &ifc {
  36         #address-cells = <2>;
  37         #size-cells = <1>;
  38         compatible = "fsl,ifc", "simple-bus";
  39         interrupts = <25 2 0 0>;
  40 };
  41
  42 /* controller at 0x200000 */
  43 &pci0 {
  44         compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
  45         device_type = "pci";
  46         #size-cells = <2>;
  47         #address-cells = <3>;
  48         bus-range = <0x0 0xff>;
  49         interrupts = <20 2 0 0>;
  50         fsl,iommu-parent = <&pamu0>;
  51         pcie@0 {
  52                 #interrupt-cells = <1>;
  53                 #size-cells = <2>;
  54                 #address-cells = <3>;
  55                 device_type = "pci";
  56                 reg = <0 0 0 0 0>;
  57                 interrupts = <20 2 0 0>;
  58                 interrupt-map-mask = <0xf800 0 0 7>;
  59                 interrupt-map = <
  60                         /* IDSEL 0x0 */
  61                         0000 0 0 1 &mpic 40 1 0 0
  62                         0000 0 0 2 &mpic 1 1 0 0
  63                         0000 0 0 3 &mpic 2 1 0 0
  64                         0000 0 0 4 &mpic 3 1 0 0
  65                         >;
  66         };
  67 };
  68
  69 &dcsr {
  70         #address-cells = <1>;
  71         #size-cells = <1>;
  72         compatible = "fsl,dcsr", "simple-bus";
  73
  74         dcsr-epu@0 {
  75                 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
  76                 interrupts = <52 2 0 0
  77                               84 2 0 0
  78                               85 2 0 0
  79                               94 2 0 0
  80                               95 2 0 0>;
  81                 reg = <0x0 0x1000>;
  82         };
  83         dcsr-npc {
  84                 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
  85                 reg = <0x1000 0x1000 0x1002000 0x10000>;
  86         };
  87         dcsr-nxc@2000 {
  88                 compatible = "fsl,dcsr-nxc";
  89                 reg = <0x2000 0x1000>;
  90         };
  91         dcsr-corenet {
  92                 compatible = "fsl,dcsr-corenet";
  93                 reg = <0x8000 0x1000 0x1A000 0x1000>;
  94         };
  95         dcsr-dpaa@9000 {
  96                 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
  97                 reg = <0x9000 0x1000>;
  98         };
  99         dcsr-ocn@11000 {
 100                 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
 101                 reg = <0x11000 0x1000>;
 102         };
 103         dcsr-ddr@12000 {
 104                 compatible = "fsl,dcsr-ddr";
 105                 dev-handle = <&ddr1>;
 106                 reg = <0x12000 0x1000>;
 107         };
 108         dcsr-nal@18000 {
 109                 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
 110                 reg = <0x18000 0x1000>;
 111         };
 112         dcsr-rcpm@22000 {
 113                 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
 114                 reg = <0x22000 0x1000>;
 115         };
 116         dcsr-snpc@30000 {
 117                 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
 118                 reg = <0x30000 0x1000 0x1022000 0x10000>;
 119         };
 120         dcsr-snpc@31000 {
 121                 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
 122                 reg = <0x31000 0x1000 0x1042000 0x10000>;
 123         };
 124         dcsr-cpu-sb-proxy@100000 {
 125                 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 126                 cpu-handle = <&cpu0>;
 127                 reg = <0x100000 0x1000 0x101000 0x1000>;
 128         };
 129 };
 130
 131 &soc {
 132         #address-cells = <1>;
 133         #size-cells = <1>;
 134         device_type = "soc";
 135         compatible = "simple-bus";
 136
 137         soc-sram-error {
 138                 compatible = "fsl,soc-sram-error";
 139                 interrupts = <16 2 1 2>;
 140         };
 141
 142         corenet-law@0 {
 143                 compatible = "fsl,corenet-law";
 144                 reg = <0x0 0x1000>;
 145                 fsl,num-laws = <32>;
 146         };
 147
 148         ddr1: memory-controller@8000 {
 149                 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 150                 reg = <0x8000 0x1000>;
 151                 interrupts = <16 2 1 8>;
 152         };
 153
 154         cpc: l3-cache-controller@10000 {
 155                 compatible = "fsl,b4-l3-cache-controller", "cache";
 156                 reg = <0x10000 0x1000>;
 157                 interrupts = <16 2 1 4>;
 158         };
 159
 160         corenet-cf@18000 {
 161                 compatible = "fsl,b4-corenet-cf";
 162                 reg = <0x18000 0x1000>;
 163                 interrupts = <16 2 1 0>;
 164                 fsl,ccf-num-csdids = <32>;
 165                 fsl,ccf-num-snoopids = <32>;
 166         };
 167
 168         iommu@20000 {
 169                 compatible =  "fsl,pamu-v1.0", "fsl,pamu";
 170                 reg = <0x20000 0x4000>;
 171                 #address-cells = <1>;
 172                 #size-cells = <1>;
 173                 interrupts = <
 174                         24 2 0 0
 175                         16 2 1 1>;
 176
 177
 178                 /* PCIe, DMA, SRIO */
 179                 pamu0: pamu@0 {
 180                         reg = <0 0x1000>;
 181                         fsl,primary-cache-geometry = <8 1>;
 182                         fsl,secondary-cache-geometry = <32 2>;
 183                 };
 184
 185                 /* AXI2, Maple */
 186                 pamu1: pamu@1000 {
 187                         reg = <0x1000 0x1000>;
 188                         fsl,primary-cache-geometry = <32 1>;
 189                         fsl,secondary-cache-geometry = <32 2>;
 190                 };
 191
 192                 /* Q/BMan */
 193                 pamu2: pamu@2000 {
 194                         reg = <0x2000 0x1000>;
 195                         fsl,primary-cache-geometry = <32 1>;
 196                         fsl,secondary-cache-geometry = <32 2>;
 197                 };
 198
 199                 /* AXI1, FMAN */
 200                 pamu3: pamu@3000 {
 201                         reg = <0x3000 0x1000>;
 202                         fsl,primary-cache-geometry = <32 1>;
 203                         fsl,secondary-cache-geometry = <32 2>;
 204                 };
 205         };
 206
 207 /include/ "qoriq-mpic4.3.dtsi"
 208
 209         guts: global-utilities@e0000 {
 210                 compatible = "fsl,b4-device-config";
 211                 reg = <0xe0000 0xe00>;
 212                 fsl,has-rstcr;
 213                 fsl,liodn-bits = <12>;
 214         };
 215
 216         clockgen: global-utilities@e1000 {
 217                 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
 218                 reg = <0xe1000 0x1000>;
 219         };
 220
 221         rcpm: global-utilities@e2000 {
 222                 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
 223                 reg = <0xe2000 0x1000>;
 224         };
 225
 226 /include/ "elo3-dma-0.dtsi"
 227         dma@100300 {
 228                 fsl,iommu-parent = <&pamu0>;
 229                 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
 230         };
 231
 232 /include/ "elo3-dma-1.dtsi"
 233         dma@101300 {
 234                 fsl,iommu-parent = <&pamu0>;
 235                 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
 236         };
 237
 238 /include/ "qonverge-usb2-dr-0.dtsi"
 239         usb0: usb@210000 {
 240                 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
 241                 fsl,iommu-parent = <&pamu1>;
 242                 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
 243         };
 244
 245 /include/ "qoriq-espi-0.dtsi"
 246         spi@110000 {
 247                 fsl,espi-num-chipselects = <4>;
 248         };
 249
 250 /include/ "qoriq-esdhc-0.dtsi"
 251         sdhc@114000 {
 252                 sdhci,auto-cmd12;
 253                 fsl,iommu-parent = <&pamu1>;
 254                 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
 255         };
 256
 257 /include/ "qoriq-i2c-0.dtsi"
 258 /include/ "qoriq-i2c-1.dtsi"
 259 /include/ "qoriq-duart-0.dtsi"
 260 /include/ "qoriq-duart-1.dtsi"
 261 /include/ "qoriq-sec5.3-0.dtsi"
 262
 263         L2: l2-cache-controller@c20000 {
 264                 compatible = "fsl,b4-l2-cache-controller";
 265                 reg = <0xc20000 0x1000>;
 266                 next-level-cache = <&cpc>;
 267         };
 268 };