arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c

   1 /*
   2  * Toshiba rbtx4927 specific setup
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * Copyright (C) 2000 RidgeRun, Inc.
  11  * Author: RidgeRun, Inc.
  12  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  13  *
  14  * Copyright 2001 MontaVista Software Inc.
  15  * Author: jsun@mvista.com or jsun@junsun.net
  16  *
  17  * Copyright 2002 MontaVista Software Inc.
  18  * Author: Michael Pruznick, michael_pruznick@mvista.com
  19  *
  20  * Copyright (C) 2000-2001 Toshiba Corporation
  21  *
  22  * Copyright (C) 2004 MontaVista Software Inc.
  23  * Author: Manish Lachwani, mlachwani@mvista.com
  24  *
  25  *  This program is free software; you can redistribute it and/or modify it
  26  *  under the terms of the GNU General Public License as published by the
  27  *  Free Software Foundation; either version 2 of the License, or (at your
  28  *  option) any later version.
  29  *
  30  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  31  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  32  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  33  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  34  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  36  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  38  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  39  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *  You should have received a copy of the GNU General Public License along
  42  *  with this program; if not, write to the Free Software Foundation, Inc.,
  43  *  675 Mass Ave, Cambridge, MA 02139, USA.
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/mm.h>
  49 #include <linux/swap.h>
  50 #include <linux/ioport.h>
  51 #include <linux/sched.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/timex.h>
  55 #include <linux/pm.h>
  56 #include <linux/platform_device.h>
  57
  58 #include <asm/bootinfo.h>
  59 #include <asm/page.h>
  60 #include <asm/io.h>
  61 #include <asm/irq.h>
  62 #include <asm/irq_regs.h>
  63 #include <asm/processor.h>
  64 #include <asm/reboot.h>
  65 #include <asm/time.h>
  66 #include <linux/bootmem.h>
  67 #include <linux/blkdev.h>
  68 #ifdef CONFIG_TOSHIBA_FPCIB0
  69 #include <asm/tx4927/smsc_fdc37m81x.h>
  70 #endif
  71 #include <asm/tx4927/toshiba_rbtx4927.h>
  72 #ifdef CONFIG_PCI
  73 #include <asm/tx4927/tx4927_pci.h>
  74 #endif
  75 #ifdef CONFIG_BLK_DEV_IDEPCI
  76 #include <linux/hdreg.h>
  77 #include <linux/ide.h>
  78 #endif
  79 #ifdef CONFIG_SERIAL_TXX9
  80 #include <linux/tty.h>
  81 #include <linux/serial.h>
  82 #include <linux/serial_core.h>
  83 #endif
  84
  85 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
  86
  87 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  88 #define TOSHIBA_RBTX4927_SETUP_NONE        0x00000000
  89
  90 #define TOSHIBA_RBTX4927_SETUP_INFO        ( 1 <<  0 )
  91 #define TOSHIBA_RBTX4927_SETUP_WARN        ( 1 <<  1 )
  92 #define TOSHIBA_RBTX4927_SETUP_EROR        ( 1 <<  2 )
  93
  94 #define TOSHIBA_RBTX4927_SETUP_EFWFU       ( 1 <<  3 )
  95 #define TOSHIBA_RBTX4927_SETUP_SETUP       ( 1 <<  4 )
  96 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT   ( 1 <<  5 )
  97 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 <<  6 )
  98 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS     ( 1 <<  7 )
  99 #define TOSHIBA_RBTX4927_SETUP_PCI1        ( 1 <<  8 )
 100 #define TOSHIBA_RBTX4927_SETUP_PCI2        ( 1 <<  9 )
 101 #define TOSHIBA_RBTX4927_SETUP_PCI66       ( 1 << 10 )
 102
 103 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 104 #endif
 105
 106 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 107 static const u32 toshiba_rbtx4927_setup_debug_flag =
 108     (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
 109      TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
 110      TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
 111      TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
 112      | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
 113      TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
 114 #endif
 115
 116 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 117 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
 118         if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
 119         { \
 120            char tmp[100]; \
 121            sprintf( tmp, str ); \
 122            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 123         }
 124 #else
 125 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
 126 #endif
 127
 128 /* These functions are used for rebooting or halting the machine*/
 129 extern void toshiba_rbtx4927_restart(char *command);
 130 extern void toshiba_rbtx4927_halt(void);
 131 extern void toshiba_rbtx4927_power_off(void);
 132
 133 int tx4927_using_backplane = 0;
 134
 135 extern void gt64120_time_init(void);
 136 extern void toshiba_rbtx4927_irq_setup(void);
 137
 138 char *prom_getcmdline(void);
 139
 140 #ifdef CONFIG_PCI
 141 #define CONFIG_TX4927BUG_WORKAROUND
 142 #undef TX4927_SUPPORT_COMMAND_IO
 143 #undef  TX4927_SUPPORT_PCI_66
 144 int tx4927_cpu_clock = 100000000;       /* 100MHz */
 145 unsigned long mips_pci_io_base;
 146 unsigned long mips_pci_io_size;
 147 unsigned long mips_pci_mem_base;
 148 unsigned long mips_pci_mem_size;
 149 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 150 unsigned long mips_pci_io_pciaddr = 0;
 151 unsigned long mips_memory_upper;
 152 static int tx4927_ccfg_toeon = 1;
 153 static int tx4927_pcic_trdyto = 0;      /* default: disabled */
 154 unsigned long tx4927_ce_base[8];
 155 void tx4927_pci_setup(void);
 156 void tx4927_reset_pci_pcic(void);
 157 int tx4927_pci66 = 0;           /* 0:auto */
 158 #endif
 159
 160 char *toshiba_name = "";
 161
 162 #ifdef CONFIG_PCI
 163 static void tx4927_pcierr_interrupt(int irq, void *dev_id)
 164 {
 165 #ifdef CONFIG_BLK_DEV_IDEPCI
 166         /* ignore MasterAbort for ide probing... */
 167         if (irq == TX4927_IRQ_IRC_PCIERR &&
 168             ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
 169             PCI_STATUS_REC_MASTER_ABORT) {
 170                 tx4927_pcicptr->pcistatus =
 171                     (tx4927_pcicptr->
 172                      pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
 173                                                 << 16);
 174
 175                 return;
 176         }
 177 #endif
 178         printk("PCI error interrupt (irq 0x%x).\n", irq);
 179
 180         printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
 181                (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
 182                tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
 183         printk("ccfg:%08lx, tear:%02lx_%08lx\n",
 184                (unsigned long) tx4927_ccfgptr->ccfg,
 185                (unsigned long) (tx4927_ccfgptr->tear >> 32),
 186                (unsigned long) tx4927_ccfgptr->tear);
 187         show_regs(get_irq_regs());
 188 }
 189
 190 void __init toshiba_rbtx4927_pci_irq_init(void)
 191 {
 192         return;
 193 }
 194
 195 void tx4927_reset_pci_pcic(void)
 196 {
 197         /* Reset PCI Bus */
 198         *tx4927_pcireset_ptr = 1;
 199         /* Reset PCIC */
 200         tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
 201         udelay(10000);
 202         /* clear PCIC reset */
 203         tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
 204         *tx4927_pcireset_ptr = 0;
 205 }
 206 #endif /* CONFIG_PCI */
 207
 208 #ifdef CONFIG_PCI
 209 void print_pci_status(void)
 210 {
 211         printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
 212         printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
 213 }
 214
 215 extern struct pci_controller tx4927_controller;
 216
 217 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
 218                                     int top_bus, int busnr, int devfn)
 219 {
 220         static struct pci_dev dev;
 221         static struct pci_bus bus;
 222
 223         dev.sysdata = (void *)hose;
 224         dev.devfn = devfn;
 225         bus.number = busnr;
 226         bus.ops = hose->pci_ops;
 227         bus.parent = NULL;
 228         dev.bus = &bus;
 229
 230         return &dev;
 231 }
 232
 233 #define EARLY_PCI_OP(rw, size, type)                                    \
 234 static int early_##rw##_config_##size(struct pci_controller *hose,      \
 235         int top_bus, int bus, int devfn, int offset, type value)        \
 236 {                                                                       \
 237         return pci_##rw##_config_##size(                                \
 238                 fake_pci_dev(hose, top_bus, bus, devfn),                \
 239                 offset, value);                                         \
 240 }
 241
 242 EARLY_PCI_OP(read, byte, u8 *)
 243 EARLY_PCI_OP(read, word, u16 *)
 244 EARLY_PCI_OP(read, dword, u32 *)
 245 EARLY_PCI_OP(write, byte, u8)
 246 EARLY_PCI_OP(write, word, u16)
 247 EARLY_PCI_OP(write, dword, u32)
 248
 249 static int __init tx4927_pcibios_init(void)
 250 {
 251         unsigned int id;
 252         u32 pci_devfn;
 253         int devfn_start = 0;
 254         int devfn_stop = 0xff;
 255         int busno = 0; /* One bus on the Toshiba */
 256         struct pci_controller *hose = &tx4927_controller;
 257
 258         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 259                                        "-\n");
 260
 261         for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
 262                 early_read_config_dword(hose, busno, busno, pci_devfn,
 263                                         PCI_VENDOR_ID, &id);
 264
 265                 if (id == 0xffffffff) {
 266                         continue;
 267                 }
 268
 269                 if (id == 0x94601055) {
 270                         u8 v08_64;
 271                         u32 v32_b0;
 272                         u8 v08_e1;
 273                         char *s = " sb/isa --";
 274
 275                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 276                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 277                              s);
 278
 279                         early_read_config_byte(hose, busno, busno,
 280                                                pci_devfn, 0x64, &v08_64);
 281                         early_read_config_dword(hose, busno, busno,
 282                                                 pci_devfn, 0xb0, &v32_b0);
 283                         early_read_config_byte(hose, busno, busno,
 284                                                pci_devfn, 0xe1, &v08_e1);
 285
 286                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 287                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 288                              ":%s beg 0x64 = 0x%02x\n", s, v08_64);
 289                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 290                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 291                              ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
 292                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 293                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 294                              ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
 295
 296                         /* serial irq control */
 297                         v08_64 = 0xd0;
 298
 299                         /* serial irq pin */
 300                         v32_b0 |= 0x00010000;
 301
 302                         /* ide irq on isa14 */
 303                         v08_e1 &= 0xf0;
 304                         v08_e1 |= 0x0d;
 305
 306                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 307                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 308                              ":%s mid 0x64 = 0x%02x\n", s, v08_64);
 309                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 310                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 311                              ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
 312                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 313                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 314                              ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
 315
 316                         early_write_config_byte(hose, busno, busno,
 317                                                 pci_devfn, 0x64, v08_64);
 318                         early_write_config_dword(hose, busno, busno,
 319                                                  pci_devfn, 0xb0, v32_b0);
 320                         early_write_config_byte(hose, busno, busno,
 321                                                 pci_devfn, 0xe1, v08_e1);
 322
 323 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 324                         {
 325                                 early_read_config_byte(hose, busno, busno,
 326                                                        pci_devfn, 0x64,
 327                                                        &v08_64);
 328                                 early_read_config_dword(hose, busno, busno,
 329                                                         pci_devfn, 0xb0,
 330                                                         &v32_b0);
 331                                 early_read_config_byte(hose, busno, busno,
 332                                                        pci_devfn, 0xe1,
 333                                                        &v08_e1);
 334
 335                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 336                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 337                                      ":%s end 0x64 = 0x%02x\n", s, v08_64);
 338                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 339                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 340                                      ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
 341                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 342                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 343                                      ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
 344                         }
 345 #endif
 346
 347                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 348                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 349                              s);
 350                 }
 351
 352                 if (id == 0x91301055) {
 353                         u8 v08_04;
 354                         u8 v08_09;
 355                         u8 v08_41;
 356                         u8 v08_43;
 357                         u8 v08_5c;
 358                         char *s = " sb/ide --";
 359
 360                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 361                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 362                              s);
 363
 364                         early_read_config_byte(hose, busno, busno,
 365                                                pci_devfn, 0x04, &v08_04);
 366                         early_read_config_byte(hose, busno, busno,
 367                                                pci_devfn, 0x09, &v08_09);
 368                         early_read_config_byte(hose, busno, busno,
 369                                                pci_devfn, 0x41, &v08_41);
 370                         early_read_config_byte(hose, busno, busno,
 371                                                pci_devfn, 0x43, &v08_43);
 372                         early_read_config_byte(hose, busno, busno,
 373                                                pci_devfn, 0x5c, &v08_5c);
 374
 375                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 376                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 377                              ":%s beg 0x04 = 0x%02x\n", s, v08_04);
 378                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 379                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 380                              ":%s beg 0x09 = 0x%02x\n", s, v08_09);
 381                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 382                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 383                              ":%s beg 0x41 = 0x%02x\n", s, v08_41);
 384                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 385                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 386                              ":%s beg 0x43 = 0x%02x\n", s, v08_43);
 387                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 388                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 389                              ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
 390
 391                         /* enable ide master/io */
 392                         v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 393
 394                         /* enable ide native mode */
 395                         v08_09 |= 0x05;
 396
 397                         /* enable primary ide */
 398                         v08_41 |= 0x80;
 399
 400                         /* enable secondary ide */
 401                         v08_43 |= 0x80;
 402
 403                         /*
 404                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 405                          *
 406                          * This line of code is intended to provide the user with a work
 407                          * around solution to the anomalies cited in SMSC's anomaly sheet
 408                          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 409                          *
 410                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 411                          */
 412                         v08_5c |= 0x01;
 413
 414                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 415                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 416                              ":%s mid 0x04 = 0x%02x\n", s, v08_04);
 417                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 418                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 419                              ":%s mid 0x09 = 0x%02x\n", s, v08_09);
 420                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 421                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 422                              ":%s mid 0x41 = 0x%02x\n", s, v08_41);
 423                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 424                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 425                              ":%s mid 0x43 = 0x%02x\n", s, v08_43);
 426                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 427                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 428                              ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
 429
 430                         early_write_config_byte(hose, busno, busno,
 431                                                 pci_devfn, 0x5c, v08_5c);
 432                         early_write_config_byte(hose, busno, busno,
 433                                                 pci_devfn, 0x04, v08_04);
 434                         early_write_config_byte(hose, busno, busno,
 435                                                 pci_devfn, 0x09, v08_09);
 436                         early_write_config_byte(hose, busno, busno,
 437                                                 pci_devfn, 0x41, v08_41);
 438                         early_write_config_byte(hose, busno, busno,
 439                                                 pci_devfn, 0x43, v08_43);
 440
 441 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 442                         {
 443                                 early_read_config_byte(hose, busno, busno,
 444                                                        pci_devfn, 0x04,
 445                                                        &v08_04);
 446                                 early_read_config_byte(hose, busno, busno,
 447                                                        pci_devfn, 0x09,
 448                                                        &v08_09);
 449                                 early_read_config_byte(hose, busno, busno,
 450                                                        pci_devfn, 0x41,
 451                                                        &v08_41);
 452                                 early_read_config_byte(hose, busno, busno,
 453                                                        pci_devfn, 0x43,
 454                                                        &v08_43);
 455                                 early_read_config_byte(hose, busno, busno,
 456                                                        pci_devfn, 0x5c,
 457                                                        &v08_5c);
 458
 459                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 460                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 461                                      ":%s end 0x04 = 0x%02x\n", s, v08_04);
 462                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 463                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 464                                      ":%s end 0x09 = 0x%02x\n", s, v08_09);
 465                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 466                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 467                                      ":%s end 0x41 = 0x%02x\n", s, v08_41);
 468                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 469                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 470                                      ":%s end 0x43 = 0x%02x\n", s, v08_43);
 471                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 472                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 473                                      ":%s end 0x5c = 0x%02x\n", s, v08_5c);
 474                         }
 475 #endif
 476
 477                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 478                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 479                              s);
 480                 }
 481
 482         }
 483
 484         register_pci_controller(&tx4927_controller);
 485         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 486                                        "+\n");
 487
 488         return 0;
 489 }
 490
 491 arch_initcall(tx4927_pcibios_init);
 492
 493 extern struct resource pci_io_resource;
 494 extern struct resource pci_mem_resource;
 495
 496 void tx4927_pci_setup(void)
 497 {
 498         static int called = 0;
 499         extern unsigned int tx4927_get_mem_size(void);
 500
 501         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
 502
 503         mips_memory_upper = tx4927_get_mem_size() << 20;
 504         mips_memory_upper += KSEG0;
 505         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 506                                        "0x%08lx=mips_memory_upper\n",
 507                                        mips_memory_upper);
 508         mips_pci_io_base = TX4927_PCIIO;
 509         mips_pci_io_size = TX4927_PCIIO_SIZE;
 510         mips_pci_mem_base = TX4927_PCIMEM;
 511         mips_pci_mem_size = TX4927_PCIMEM_SIZE;
 512
 513         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 514                                        "0x%08lx=mips_pci_io_base\n",
 515                                        mips_pci_io_base);
 516         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 517                                        "0x%08lx=mips_pci_io_size\n",
 518                                        mips_pci_io_size);
 519         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 520                                        "0x%08lx=mips_pci_mem_base\n",
 521                                        mips_pci_mem_base);
 522         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 523                                        "0x%08lx=mips_pci_mem_size\n",
 524                                        mips_pci_mem_size);
 525         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 526                                        "0x%08lx=pci_io_resource.start\n",
 527                                        pci_io_resource.start);
 528         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 529                                        "0x%08lx=pci_io_resource.end\n",
 530                                        pci_io_resource.end);
 531         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 532                                        "0x%08lx=pci_mem_resource.start\n",
 533                                        pci_mem_resource.start);
 534         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 535                                        "0x%08lx=pci_mem_resource.end\n",
 536                                        pci_mem_resource.end);
 537         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 538                                        "0x%08lx=mips_io_port_base",
 539                                        mips_io_port_base);
 540         if (!called) {
 541                 printk
 542                     ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
 543                      toshiba_name,
 544                      (unsigned short) (tx4927_pcicptr->pciid >> 16),
 545                      (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
 546                      (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
 547                      (!(tx4927_ccfgptr->
 548                         ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
 549                      "Internal");
 550                 called = 1;
 551         }
 552         printk("%s PCIC --%s PCICLK:",toshiba_name,
 553                (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
 554         if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
 555                 int pciclk = 0;
 556                 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 557                         switch ((unsigned long) tx4927_ccfgptr->
 558                                 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 559                         case TX4937_CCFG_PCIDIVMODE_4:
 560                                 pciclk = tx4927_cpu_clock / 4;
 561                                 break;
 562                         case TX4937_CCFG_PCIDIVMODE_4_5:
 563                                 pciclk = tx4927_cpu_clock * 2 / 9;
 564                                 break;
 565                         case TX4937_CCFG_PCIDIVMODE_5:
 566                                 pciclk = tx4927_cpu_clock / 5;
 567                                 break;
 568                         case TX4937_CCFG_PCIDIVMODE_5_5:
 569                                 pciclk = tx4927_cpu_clock * 2 / 11;
 570                                 break;
 571                         case TX4937_CCFG_PCIDIVMODE_8:
 572                                 pciclk = tx4927_cpu_clock / 8;
 573                                 break;
 574                         case TX4937_CCFG_PCIDIVMODE_9:
 575                                 pciclk = tx4927_cpu_clock / 9;
 576                                 break;
 577                         case TX4937_CCFG_PCIDIVMODE_10:
 578                                 pciclk = tx4927_cpu_clock / 10;
 579                                 break;
 580                         case TX4937_CCFG_PCIDIVMODE_11:
 581                                 pciclk = tx4927_cpu_clock / 11;
 582                                 break;
 583                         }
 584
 585                 else
 586                         switch ((unsigned long) tx4927_ccfgptr->
 587                                 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 588                         case TX4927_CCFG_PCIDIVMODE_2_5:
 589                                 pciclk = tx4927_cpu_clock * 2 / 5;
 590                                 break;
 591                         case TX4927_CCFG_PCIDIVMODE_3:
 592                                 pciclk = tx4927_cpu_clock / 3;
 593                                 break;
 594                         case TX4927_CCFG_PCIDIVMODE_5:
 595                                 pciclk = tx4927_cpu_clock / 5;
 596                                 break;
 597                         case TX4927_CCFG_PCIDIVMODE_6:
 598                                 pciclk = tx4927_cpu_clock / 6;
 599                                 break;
 600                         }
 601
 602                 printk("Internal(%dMHz)", pciclk / 1000000);
 603         } else {
 604                 int pciclk = 0;
 605                 int pciclk_setting = *tx4927_pci_clk_ptr;
 606                 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
 607                 case TX4927_PCI_CLK_33:
 608                         pciclk = 33333333;
 609                         break;
 610                 case TX4927_PCI_CLK_25:
 611                         pciclk = 25000000;
 612                         break;
 613                 case TX4927_PCI_CLK_66:
 614                         pciclk = 66666666;
 615                         break;
 616                 case TX4927_PCI_CLK_50:
 617                         pciclk = 50000000;
 618                         break;
 619                 }
 620                 printk("External(%dMHz)", pciclk / 1000000);
 621         }
 622         printk("\n");
 623
 624
 625
 626         /* GB->PCI mappings */
 627         tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
 628         tx4927_pcicptr->g2piogbase = mips_pci_io_base |
 629 #ifdef __BIG_ENDIAN
 630             TX4927_PCIC_G2PIOGBASE_ECHG
 631 #else
 632             TX4927_PCIC_G2PIOGBASE_BSDIS
 633 #endif
 634             ;
 635
 636         tx4927_pcicptr->g2piopbase = 0;
 637
 638         tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
 639         tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
 640 #ifdef __BIG_ENDIAN
 641             TX4927_PCIC_G2PMnGBASE_ECHG
 642 #else
 643             TX4927_PCIC_G2PMnGBASE_BSDIS
 644 #endif
 645             ;
 646         tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
 647
 648         tx4927_pcicptr->g2pmmask[1] = 0;
 649         tx4927_pcicptr->g2pmgbase[1] = 0;
 650         tx4927_pcicptr->g2pmpbase[1] = 0;
 651         tx4927_pcicptr->g2pmmask[2] = 0;
 652         tx4927_pcicptr->g2pmgbase[2] = 0;
 653         tx4927_pcicptr->g2pmpbase[2] = 0;
 654
 655
 656         /* PCI->GB mappings (I/O 256B) */
 657         tx4927_pcicptr->p2giopbase = 0; /* 256B */
 658
 659         /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
 660         tx4927_pcicptr->p2gm0plbase = 0;
 661         tx4927_pcicptr->p2gm0pubase = 0;
 662         tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
 663 #ifdef __BIG_ENDIAN
 664             TX4927_PCIC_P2GMnGBASE_TECHG
 665 #else
 666             TX4927_PCIC_P2GMnGBASE_TBSDIS
 667 #endif
 668             ;
 669
 670         /* PCI->GB mappings (MEM 16MB) -not used */
 671         tx4927_pcicptr->p2gm1plbase = 0xffffffff;
 672 #ifdef CONFIG_TX4927BUG_WORKAROUND
 673         /*
 674          * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
 675          * if P2GM0PUBASE was 0.
 676          */
 677         tx4927_pcicptr->p2gm1pubase = 0;
 678 #else
 679         tx4927_pcicptr->p2gm1pubase = 0xffffffff;
 680 #endif
 681         tx4927_pcicptr->p2gmgbase[1] = 0;
 682
 683         /* PCI->GB mappings (MEM 1MB) -not used */
 684         tx4927_pcicptr->p2gm2pbase = 0xffffffff;
 685         tx4927_pcicptr->p2gmgbase[2] = 0;
 686
 687
 688         /* Enable Initiator Memory 0 Space, I/O Space, Config */
 689         tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
 690         tx4927_pcicptr->pciccfg |=
 691             TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
 692             TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
 693
 694
 695         /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
 696         tx4927_pcicptr->pcicfg1 = 0;
 697
 698         if (tx4927_pcic_trdyto >= 0) {
 699                 tx4927_pcicptr->g2ptocnt &= ~0xff;
 700                 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
 701         }
 702
 703         /* Clear All Local Bus Status */
 704         tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
 705         /* Enable All Local Bus Interrupts */
 706         tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
 707         /* Clear All Initiator Status */
 708         tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
 709         /* Enable All Initiator Interrupts */
 710         tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
 711         /* Clear All PCI Status Error */
 712         tx4927_pcicptr->pcistatus =
 713             (tx4927_pcicptr->pcistatus & 0x0000ffff) |
 714             (TX4927_PCIC_PCISTATUS_ALL << 16);
 715         /* Enable All PCI Status Error Interrupts */
 716         tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
 717
 718         /* PCIC Int => IRC IRQ16 */
 719         tx4927_pcicptr->pcicfg2 =
 720             (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
 721
 722         if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
 723                 /* XXX */
 724         } else {
 725                 /* Reset Bus Arbiter */
 726                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
 727                 /* Enable Bus Arbiter */
 728                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
 729         }
 730
 731         tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
 732             PCI_COMMAND_MEMORY |
 733             PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 734
 735         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 736                                        ":pci setup complete:\n");
 737         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
 738 }
 739
 740 #endif /* CONFIG_PCI */
 741
 742 void toshiba_rbtx4927_restart(char *command)
 743 {
 744         printk(KERN_NOTICE "System Rebooting...\n");
 745
 746         /* enable the s/w reset register */
 747         reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
 748
 749         /* wait for enable to be seen */
 750         while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
 751                 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
 752
 753         /* do a s/w reset */
 754         reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
 755
 756         /* do something passive while waiting for reset */
 757         local_irq_disable();
 758         while (1)
 759                 asm_wait();
 760
 761         /* no return */
 762 }
 763
 764
 765 void toshiba_rbtx4927_halt(void)
 766 {
 767         printk(KERN_NOTICE "System Halted\n");
 768         local_irq_disable();
 769         while (1) {
 770                 asm_wait();
 771         }
 772         /* no return */
 773 }
 774
 775 void toshiba_rbtx4927_power_off(void)
 776 {
 777         toshiba_rbtx4927_halt();
 778         /* no return */
 779 }
 780
 781 void __init toshiba_rbtx4927_setup(void)
 782 {
 783         vu32 cp0_config;
 784         char *argptr;
 785
 786         printk("CPU is %s\n", toshiba_name);
 787
 788         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 789                                        "-\n");
 790
 791         /* f/w leaves this on at startup */
 792         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 793                                        ":Clearing STO_ERL.\n");
 794         clear_c0_status(ST0_ERL);
 795
 796         /* enable caches -- HCP5 does this, pmon does not */
 797         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 798                                        ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
 799         cp0_config = read_c0_config();
 800         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
 801         write_c0_config(cp0_config);
 802
 803 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 804         {
 805                 extern void dump_cp0(char *);
 806                 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
 807         }
 808 #endif
 809
 810         /* setup irq stuff */
 811         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 812                                        ":Setting up tx4927 pic.\n");
 813         TX4927_WR(0xff1ff604, 0x00000400);      /* irq trigger */
 814         TX4927_WR(0xff1ff608, 0x00000000);      /* irq trigger */
 815
 816         /* setup serial stuff */
 817         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 818                                        ":Setting up tx4927 sio.\n");
 819         TX4927_WR(0xff1ff314, 0x00000000);      /* h/w flow control off */
 820         TX4927_WR(0xff1ff414, 0x00000000);      /* h/w flow control off */
 821
 822         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 823                                        "+\n");
 824
 825         set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
 826         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 827                                        ":mips_io_port_base=0x%08lx\n",
 828                                        mips_io_port_base);
 829
 830         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 831                                        ":Resource\n");
 832         ioport_resource.end = 0xffffffff;
 833         iomem_resource.end = 0xffffffff;
 834
 835         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 836                                        ":ResetRoutines\n");
 837         _machine_restart = toshiba_rbtx4927_restart;
 838         _machine_halt = toshiba_rbtx4927_halt;
 839         pm_power_off = toshiba_rbtx4927_power_off;
 840
 841 #ifdef CONFIG_PCI
 842
 843         /* PCIC */
 844         /*
 845            * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
 846            *
 847            * For TX4927:
 848            * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
 849            * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
 850            * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
 851            * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
 852            * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
 853            * i.e. S9[3]: ON (83MHz), OFF (100MHz)
 854            *
 855            * For TX4937:
 856            * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
 857            * PCIDIVMODE[10] is 0.
 858            * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
 859            * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
 860            * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
 861            * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
 862            * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
 863            * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
 864            *
 865          */
 866         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 867                                        "ccfg is %lx, PCIDIVMODE is %x\n",
 868                                        (unsigned long) tx4927_ccfgptr->ccfg,
 869                                        (unsigned long) tx4927_ccfgptr->ccfg &
 870                                        (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
 871                                         TX4937_CCFG_PCIDIVMODE_MASK :
 872                                         TX4927_CCFG_PCIDIVMODE_MASK));
 873
 874         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 875                                        "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
 876                                        (unsigned long) tx4927_ccfgptr->
 877                                        ccfg & TX4927_CCFG_PCI66,
 878                                        (unsigned long) tx4927_ccfgptr->
 879                                        ccfg & TX4927_CCFG_PCIMIDE,
 880                                        (unsigned long) tx4927_ccfgptr->
 881                                        ccfg & TX4927_CCFG_PCIXARB);
 882
 883         if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 884                 switch ((unsigned long)tx4927_ccfgptr->
 885                         ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 886                 case TX4937_CCFG_PCIDIVMODE_8:
 887                 case TX4937_CCFG_PCIDIVMODE_4:
 888                         tx4927_cpu_clock = 266666666;   /* 266MHz */
 889                         break;
 890                 case TX4937_CCFG_PCIDIVMODE_9:
 891                 case TX4937_CCFG_PCIDIVMODE_4_5:
 892                         tx4927_cpu_clock = 300000000;   /* 300MHz */
 893                         break;
 894                 default:
 895                         tx4927_cpu_clock = 333333333;   /* 333MHz */
 896                 }
 897         else
 898                 switch ((unsigned long)tx4927_ccfgptr->
 899                         ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 900                 case TX4927_CCFG_PCIDIVMODE_2_5:
 901                 case TX4927_CCFG_PCIDIVMODE_5:
 902                         tx4927_cpu_clock = 166666666;   /* 166MHz */
 903                         break;
 904                 default:
 905                         tx4927_cpu_clock = 200000000;   /* 200MHz */
 906                 }
 907
 908         /* CCFG */
 909         /* enable Timeout BusError */
 910         if (tx4927_ccfg_toeon)
 911                 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
 912
 913         /* SDRAMC fixup */
 914 #ifdef CONFIG_TX4927BUG_WORKAROUND
 915         /*
 916          * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
 917          * G-bus timeout error detection is incorrect
 918          */
 919         if (tx4927_ccfg_toeon)
 920                 tx4927_sdramcptr->tr |= 0x02000000;     /* RCD:3tck */
 921 #endif
 922
 923         tx4927_pci_setup();
 924         if (tx4927_using_backplane == 1)
 925                 printk("backplane board IS installed\n");
 926         else
 927                 printk("No Backplane \n");
 928
 929         /* this is on ISA bus behind PCI bus, so need PCI up first */
 930 #ifdef CONFIG_TOSHIBA_FPCIB0
 931         {
 932                 if (tx4927_using_backplane) {
 933                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 934                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 935                              ":fpcibo=yes\n");
 936
 937                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 938                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 939                              ":smsc_fdc37m81x_init()\n");
 940                         smsc_fdc37m81x_init(0x3f0);
 941
 942                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 943                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 944                              ":smsc_fdc37m81x_config_beg()\n");
 945                         smsc_fdc37m81x_config_beg();
 946
 947                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 948                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 949                              ":smsc_fdc37m81x_config_set(KBD)\n");
 950                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 951                                                   SMSC_FDC37M81X_KBD);
 952                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 953                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 954                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 955                                                   1);
 956
 957                         smsc_fdc37m81x_config_end();
 958                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 959                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 960                              ":smsc_fdc37m81x_config_end()\n");
 961                 } else {
 962                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 963                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 964                              ":fpcibo=not_found\n");
 965                 }
 966         }
 967 #else
 968         {
 969                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 970                     (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
 971         }
 972 #endif
 973
 974 #endif /* CONFIG_PCI */
 975
 976 #ifdef CONFIG_SERIAL_TXX9
 977         {
 978                 extern int early_serial_txx9_setup(struct uart_port *port);
 979                 int i;
 980                 struct uart_port req;
 981                 for(i = 0; i < 2; i++) {
 982                         memset(&req, 0, sizeof(req));
 983                         req.line = i;
 984                         req.iotype = UPIO_MEM;
 985                         req.membase = (char *)(0xff1ff300 + i * 0x100);
 986                         req.mapbase = 0xff1ff300 + i * 0x100;
 987                         req.irq = 32 + i;
 988                         req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 989                         req.uartclk = 50000000;
 990                         early_serial_txx9_setup(&req);
 991                 }
 992         }
 993 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 994         argptr = prom_getcmdline();
 995         if (strstr(argptr, "console=") == NULL) {
 996                 strcat(argptr, " console=ttyS0,38400");
 997         }
 998 #endif
 999 #endif
1000
1001 #ifdef CONFIG_ROOT_NFS
1002         argptr = prom_getcmdline();
1003         if (strstr(argptr, "root=") == NULL) {
1004                 strcat(argptr, " root=/dev/nfs rw");
1005         }
1006 #endif
1007
1008
1009 #ifdef CONFIG_IP_PNP
1010         argptr = prom_getcmdline();
1011         if (strstr(argptr, "ip=") == NULL) {
1012                 strcat(argptr, " ip=any");
1013         }
1014 #endif
1015
1016
1017         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
1018                                "+\n");
1019 }
1020
1021 void __init
1022 toshiba_rbtx4927_time_init(void)
1023 {
1024         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
1025
1026         mips_hpt_frequency = tx4927_cpu_clock / 2;
1027
1028         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1029
1030 }
1031
1032 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1033 {
1034         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1035                                        "-\n");
1036         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1037                                        "+\n");
1038 }
1039
1040 static int __init toshiba_rbtx4927_rtc_init(void)
1041 {
1042         struct resource res = {
1043                 .start  = 0x1c010000,
1044                 .end    = 0x1c010000 + 0x800 - 1,
1045                 .flags  = IORESOURCE_MEM,
1046         };
1047         struct platform_device *dev =
1048                 platform_device_register_simple("ds1742", -1, &res, 1);
1049         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1050 }
1051 device_initcall(toshiba_rbtx4927_rtc_init);
1052
1053 static int __init rbtx4927_ne_init(void)
1054 {
1055         static struct resource __initdata res[] = {
1056                 {
1057                         .start  = RBTX4927_RTL_8019_BASE,
1058                         .end    = RBTX4927_RTL_8019_BASE + 0x20 - 1,
1059                         .flags  = IORESOURCE_IO,
1060                 }, {
1061                         .start  = RBTX4927_RTL_8019_IRQ,
1062                         .flags  = IORESOURCE_IRQ,
1063                 }
1064         };
1065         struct platform_device *dev =
1066                 platform_device_register_simple("ne", -1,
1067                                                 res, ARRAY_SIZE(res));
1068         return IS_ERR(dev) ? PTR_ERR(dev) : 0;
1069 }
1070 device_initcall(rbtx4927_ne_init);