arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c

   1 /*
   2  * Toshiba rbtx4927 specific setup
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * Copyright (C) 2000 RidgeRun, Inc.
  11  * Author: RidgeRun, Inc.
  12  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  13  *
  14  * Copyright 2001 MontaVista Software Inc.
  15  * Author: jsun@mvista.com or jsun@junsun.net
  16  *
  17  * Copyright 2002 MontaVista Software Inc.
  18  * Author: Michael Pruznick, michael_pruznick@mvista.com
  19  *
  20  * Copyright (C) 2000-2001 Toshiba Corporation
  21  *
  22  * Copyright (C) 2004 MontaVista Software Inc.
  23  * Author: Manish Lachwani, mlachwani@mvista.com
  24  *
  25  *  This program is free software; you can redistribute it and/or modify it
  26  *  under the terms of the GNU General Public License as published by the
  27  *  Free Software Foundation; either version 2 of the License, or (at your
  28  *  option) any later version.
  29  *
  30  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  31  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  32  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  33  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  34  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  36  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  38  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  39  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *  You should have received a copy of the GNU General Public License along
  42  *  with this program; if not, write to the Free Software Foundation, Inc.,
  43  *  675 Mass Ave, Cambridge, MA 02139, USA.
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/mm.h>
  49 #include <linux/swap.h>
  50 #include <linux/ioport.h>
  51 #include <linux/sched.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/timex.h>
  55 #include <linux/pm.h>
  56
  57 #include <asm/bootinfo.h>
  58 #include <asm/page.h>
  59 #include <asm/io.h>
  60 #include <asm/irq.h>
  61 #include <asm/irq_regs.h>
  62 #include <asm/processor.h>
  63 #include <asm/reboot.h>
  64 #include <asm/time.h>
  65 #include <linux/bootmem.h>
  66 #include <linux/blkdev.h>
  67 #ifdef CONFIG_RTC_DS1742
  68 #include <linux/ds1742rtc.h>
  69 #endif
  70 #ifdef CONFIG_TOSHIBA_FPCIB0
  71 #include <asm/tx4927/smsc_fdc37m81x.h>
  72 #endif
  73 #include <asm/tx4927/toshiba_rbtx4927.h>
  74 #ifdef CONFIG_PCI
  75 #include <asm/tx4927/tx4927_pci.h>
  76 #endif
  77 #ifdef CONFIG_BLK_DEV_IDEPCI
  78 #include <linux/hdreg.h>
  79 #include <linux/ide.h>
  80 #endif
  81 #ifdef CONFIG_SERIAL_TXX9
  82 #include <linux/tty.h>
  83 #include <linux/serial.h>
  84 #include <linux/serial_core.h>
  85 #endif
  86
  87 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
  88
  89 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  90 #define TOSHIBA_RBTX4927_SETUP_NONE        0x00000000
  91
  92 #define TOSHIBA_RBTX4927_SETUP_INFO        ( 1 <<  0 )
  93 #define TOSHIBA_RBTX4927_SETUP_WARN        ( 1 <<  1 )
  94 #define TOSHIBA_RBTX4927_SETUP_EROR        ( 1 <<  2 )
  95
  96 #define TOSHIBA_RBTX4927_SETUP_EFWFU       ( 1 <<  3 )
  97 #define TOSHIBA_RBTX4927_SETUP_SETUP       ( 1 <<  4 )
  98 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT   ( 1 <<  5 )
  99 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 <<  6 )
 100 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS     ( 1 <<  7 )
 101 #define TOSHIBA_RBTX4927_SETUP_PCI1        ( 1 <<  8 )
 102 #define TOSHIBA_RBTX4927_SETUP_PCI2        ( 1 <<  9 )
 103 #define TOSHIBA_RBTX4927_SETUP_PCI66       ( 1 << 10 )
 104
 105 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 106 #endif
 107
 108 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 109 static const u32 toshiba_rbtx4927_setup_debug_flag =
 110     (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
 111      TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
 112      TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
 113      TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
 114      | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
 115      TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
 116 #endif
 117
 118 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 119 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
 120         if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
 121         { \
 122            char tmp[100]; \
 123            sprintf( tmp, str ); \
 124            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 125         }
 126 #else
 127 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
 128 #endif
 129
 130 /* These functions are used for rebooting or halting the machine*/
 131 extern void toshiba_rbtx4927_restart(char *command);
 132 extern void toshiba_rbtx4927_halt(void);
 133 extern void toshiba_rbtx4927_power_off(void);
 134
 135 int tx4927_using_backplane = 0;
 136
 137 extern void gt64120_time_init(void);
 138 extern void toshiba_rbtx4927_irq_setup(void);
 139
 140 char *prom_getcmdline(void);
 141
 142 #ifdef CONFIG_PCI
 143 #define CONFIG_TX4927BUG_WORKAROUND
 144 #undef TX4927_SUPPORT_COMMAND_IO
 145 #undef  TX4927_SUPPORT_PCI_66
 146 int tx4927_cpu_clock = 100000000;       /* 100MHz */
 147 unsigned long mips_pci_io_base;
 148 unsigned long mips_pci_io_size;
 149 unsigned long mips_pci_mem_base;
 150 unsigned long mips_pci_mem_size;
 151 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 152 unsigned long mips_pci_io_pciaddr = 0;
 153 unsigned long mips_memory_upper;
 154 static int tx4927_ccfg_toeon = 1;
 155 static int tx4927_pcic_trdyto = 0;      /* default: disabled */
 156 unsigned long tx4927_ce_base[8];
 157 void tx4927_pci_setup(void);
 158 void tx4927_reset_pci_pcic(void);
 159 int tx4927_pci66 = 0;           /* 0:auto */
 160 #endif
 161
 162 char *toshiba_name = "";
 163
 164 #ifdef CONFIG_PCI
 165 static void tx4927_pcierr_interrupt(int irq, void *dev_id)
 166 {
 167 #ifdef CONFIG_BLK_DEV_IDEPCI
 168         /* ignore MasterAbort for ide probing... */
 169         if (irq == TX4927_IRQ_IRC_PCIERR &&
 170             ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
 171             PCI_STATUS_REC_MASTER_ABORT) {
 172                 tx4927_pcicptr->pcistatus =
 173                     (tx4927_pcicptr->
 174                      pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
 175                                                 << 16);
 176
 177                 return;
 178         }
 179 #endif
 180         printk("PCI error interrupt (irq 0x%x).\n", irq);
 181
 182         printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
 183                (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
 184                tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
 185         printk("ccfg:%08lx, tear:%02lx_%08lx\n",
 186                (unsigned long) tx4927_ccfgptr->ccfg,
 187                (unsigned long) (tx4927_ccfgptr->tear >> 32),
 188                (unsigned long) tx4927_ccfgptr->tear);
 189         show_regs(get_irq_regs());
 190 }
 191
 192 void __init toshiba_rbtx4927_pci_irq_init(void)
 193 {
 194         return;
 195 }
 196
 197 void tx4927_reset_pci_pcic(void)
 198 {
 199         /* Reset PCI Bus */
 200         *tx4927_pcireset_ptr = 1;
 201         /* Reset PCIC */
 202         tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
 203         udelay(10000);
 204         /* clear PCIC reset */
 205         tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
 206         *tx4927_pcireset_ptr = 0;
 207 }
 208 #endif /* CONFIG_PCI */
 209
 210 #ifdef CONFIG_PCI
 211 void print_pci_status(void)
 212 {
 213         printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
 214         printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
 215 }
 216
 217 extern struct pci_controller tx4927_controller;
 218
 219 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
 220                                     int top_bus, int busnr, int devfn)
 221 {
 222         static struct pci_dev dev;
 223         static struct pci_bus bus;
 224
 225         dev.sysdata = (void *)hose;
 226         dev.devfn = devfn;
 227         bus.number = busnr;
 228         bus.ops = hose->pci_ops;
 229         bus.parent = NULL;
 230         dev.bus = &bus;
 231
 232         return &dev;
 233 }
 234
 235 #define EARLY_PCI_OP(rw, size, type)                                    \
 236 static int early_##rw##_config_##size(struct pci_controller *hose,      \
 237         int top_bus, int bus, int devfn, int offset, type value)        \
 238 {                                                                       \
 239         return pci_##rw##_config_##size(                                \
 240                 fake_pci_dev(hose, top_bus, bus, devfn),                \
 241                 offset, value);                                         \
 242 }
 243
 244 EARLY_PCI_OP(read, byte, u8 *)
 245 EARLY_PCI_OP(read, word, u16 *)
 246 EARLY_PCI_OP(read, dword, u32 *)
 247 EARLY_PCI_OP(write, byte, u8)
 248 EARLY_PCI_OP(write, word, u16)
 249 EARLY_PCI_OP(write, dword, u32)
 250
 251 static int __init tx4927_pcibios_init(void)
 252 {
 253         unsigned int id;
 254         u32 pci_devfn;
 255         int devfn_start = 0;
 256         int devfn_stop = 0xff;
 257         int busno = 0; /* One bus on the Toshiba */
 258         struct pci_controller *hose = &tx4927_controller;
 259
 260         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 261                                        "-\n");
 262
 263         for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
 264                 early_read_config_dword(hose, busno, busno, pci_devfn,
 265                                         PCI_VENDOR_ID, &id);
 266
 267                 if (id == 0xffffffff) {
 268                         continue;
 269                 }
 270
 271                 if (id == 0x94601055) {
 272                         u8 v08_64;
 273                         u32 v32_b0;
 274                         u8 v08_e1;
 275                         char *s = " sb/isa --";
 276
 277                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 278                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 279                              s);
 280
 281                         early_read_config_byte(hose, busno, busno,
 282                                                pci_devfn, 0x64, &v08_64);
 283                         early_read_config_dword(hose, busno, busno,
 284                                                 pci_devfn, 0xb0, &v32_b0);
 285                         early_read_config_byte(hose, busno, busno,
 286                                                pci_devfn, 0xe1, &v08_e1);
 287
 288                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 289                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 290                              ":%s beg 0x64 = 0x%02x\n", s, v08_64);
 291                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 292                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 293                              ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
 294                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 295                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 296                              ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
 297
 298                         /* serial irq control */
 299                         v08_64 = 0xd0;
 300
 301                         /* serial irq pin */
 302                         v32_b0 |= 0x00010000;
 303
 304                         /* ide irq on isa14 */
 305                         v08_e1 &= 0xf0;
 306                         v08_e1 |= 0x0d;
 307
 308                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 309                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 310                              ":%s mid 0x64 = 0x%02x\n", s, v08_64);
 311                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 312                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 313                              ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
 314                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 315                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 316                              ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
 317
 318                         early_write_config_byte(hose, busno, busno,
 319                                                 pci_devfn, 0x64, v08_64);
 320                         early_write_config_dword(hose, busno, busno,
 321                                                  pci_devfn, 0xb0, v32_b0);
 322                         early_write_config_byte(hose, busno, busno,
 323                                                 pci_devfn, 0xe1, v08_e1);
 324
 325 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 326                         {
 327                                 early_read_config_byte(hose, busno, busno,
 328                                                        pci_devfn, 0x64,
 329                                                        &v08_64);
 330                                 early_read_config_dword(hose, busno, busno,
 331                                                         pci_devfn, 0xb0,
 332                                                         &v32_b0);
 333                                 early_read_config_byte(hose, busno, busno,
 334                                                        pci_devfn, 0xe1,
 335                                                        &v08_e1);
 336
 337                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 338                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 339                                      ":%s end 0x64 = 0x%02x\n", s, v08_64);
 340                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 341                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 342                                      ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
 343                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 344                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 345                                      ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
 346                         }
 347 #endif
 348
 349                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 350                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 351                              s);
 352                 }
 353
 354                 if (id == 0x91301055) {
 355                         u8 v08_04;
 356                         u8 v08_09;
 357                         u8 v08_41;
 358                         u8 v08_43;
 359                         u8 v08_5c;
 360                         char *s = " sb/ide --";
 361
 362                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 363                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 364                              s);
 365
 366                         early_read_config_byte(hose, busno, busno,
 367                                                pci_devfn, 0x04, &v08_04);
 368                         early_read_config_byte(hose, busno, busno,
 369                                                pci_devfn, 0x09, &v08_09);
 370                         early_read_config_byte(hose, busno, busno,
 371                                                pci_devfn, 0x41, &v08_41);
 372                         early_read_config_byte(hose, busno, busno,
 373                                                pci_devfn, 0x43, &v08_43);
 374                         early_read_config_byte(hose, busno, busno,
 375                                                pci_devfn, 0x5c, &v08_5c);
 376
 377                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 378                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 379                              ":%s beg 0x04 = 0x%02x\n", s, v08_04);
 380                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 381                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 382                              ":%s beg 0x09 = 0x%02x\n", s, v08_09);
 383                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 384                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 385                              ":%s beg 0x41 = 0x%02x\n", s, v08_41);
 386                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 387                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 388                              ":%s beg 0x43 = 0x%02x\n", s, v08_43);
 389                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 390                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 391                              ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
 392
 393                         /* enable ide master/io */
 394                         v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 395
 396                         /* enable ide native mode */
 397                         v08_09 |= 0x05;
 398
 399                         /* enable primary ide */
 400                         v08_41 |= 0x80;
 401
 402                         /* enable secondary ide */
 403                         v08_43 |= 0x80;
 404
 405                         /*
 406                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 407                          *
 408                          * This line of code is intended to provide the user with a work
 409                          * around solution to the anomalies cited in SMSC's anomaly sheet
 410                          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 411                          *
 412                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 413                          */
 414                         v08_5c |= 0x01;
 415
 416                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 417                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 418                              ":%s mid 0x04 = 0x%02x\n", s, v08_04);
 419                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 420                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 421                              ":%s mid 0x09 = 0x%02x\n", s, v08_09);
 422                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 423                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 424                              ":%s mid 0x41 = 0x%02x\n", s, v08_41);
 425                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 426                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 427                              ":%s mid 0x43 = 0x%02x\n", s, v08_43);
 428                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 429                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 430                              ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
 431
 432                         early_write_config_byte(hose, busno, busno,
 433                                                 pci_devfn, 0x5c, v08_5c);
 434                         early_write_config_byte(hose, busno, busno,
 435                                                 pci_devfn, 0x04, v08_04);
 436                         early_write_config_byte(hose, busno, busno,
 437                                                 pci_devfn, 0x09, v08_09);
 438                         early_write_config_byte(hose, busno, busno,
 439                                                 pci_devfn, 0x41, v08_41);
 440                         early_write_config_byte(hose, busno, busno,
 441                                                 pci_devfn, 0x43, v08_43);
 442
 443 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 444                         {
 445                                 early_read_config_byte(hose, busno, busno,
 446                                                        pci_devfn, 0x04,
 447                                                        &v08_04);
 448                                 early_read_config_byte(hose, busno, busno,
 449                                                        pci_devfn, 0x09,
 450                                                        &v08_09);
 451                                 early_read_config_byte(hose, busno, busno,
 452                                                        pci_devfn, 0x41,
 453                                                        &v08_41);
 454                                 early_read_config_byte(hose, busno, busno,
 455                                                        pci_devfn, 0x43,
 456                                                        &v08_43);
 457                                 early_read_config_byte(hose, busno, busno,
 458                                                        pci_devfn, 0x5c,
 459                                                        &v08_5c);
 460
 461                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 462                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 463                                      ":%s end 0x04 = 0x%02x\n", s, v08_04);
 464                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 465                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 466                                      ":%s end 0x09 = 0x%02x\n", s, v08_09);
 467                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 468                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 469                                      ":%s end 0x41 = 0x%02x\n", s, v08_41);
 470                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 471                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 472                                      ":%s end 0x43 = 0x%02x\n", s, v08_43);
 473                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 474                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 475                                      ":%s end 0x5c = 0x%02x\n", s, v08_5c);
 476                         }
 477 #endif
 478
 479                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 480                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 481                              s);
 482                 }
 483
 484         }
 485
 486         register_pci_controller(&tx4927_controller);
 487         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 488                                        "+\n");
 489
 490         return 0;
 491 }
 492
 493 arch_initcall(tx4927_pcibios_init);
 494
 495 extern struct resource pci_io_resource;
 496 extern struct resource pci_mem_resource;
 497
 498 void tx4927_pci_setup(void)
 499 {
 500         static int called = 0;
 501         extern unsigned int tx4927_get_mem_size(void);
 502
 503         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
 504
 505         mips_memory_upper = tx4927_get_mem_size() << 20;
 506         mips_memory_upper += KSEG0;
 507         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 508                                        "0x%08lx=mips_memory_upper\n",
 509                                        mips_memory_upper);
 510         mips_pci_io_base = TX4927_PCIIO;
 511         mips_pci_io_size = TX4927_PCIIO_SIZE;
 512         mips_pci_mem_base = TX4927_PCIMEM;
 513         mips_pci_mem_size = TX4927_PCIMEM_SIZE;
 514
 515         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 516                                        "0x%08lx=mips_pci_io_base\n",
 517                                        mips_pci_io_base);
 518         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 519                                        "0x%08lx=mips_pci_io_size\n",
 520                                        mips_pci_io_size);
 521         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 522                                        "0x%08lx=mips_pci_mem_base\n",
 523                                        mips_pci_mem_base);
 524         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 525                                        "0x%08lx=mips_pci_mem_size\n",
 526                                        mips_pci_mem_size);
 527         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 528                                        "0x%08lx=pci_io_resource.start\n",
 529                                        pci_io_resource.start);
 530         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 531                                        "0x%08lx=pci_io_resource.end\n",
 532                                        pci_io_resource.end);
 533         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 534                                        "0x%08lx=pci_mem_resource.start\n",
 535                                        pci_mem_resource.start);
 536         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 537                                        "0x%08lx=pci_mem_resource.end\n",
 538                                        pci_mem_resource.end);
 539         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 540                                        "0x%08lx=mips_io_port_base",
 541                                        mips_io_port_base);
 542         if (!called) {
 543                 printk
 544                     ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
 545                      toshiba_name,
 546                      (unsigned short) (tx4927_pcicptr->pciid >> 16),
 547                      (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
 548                      (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
 549                      (!(tx4927_ccfgptr->
 550                         ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
 551                      "Internal");
 552                 called = 1;
 553         }
 554         printk("%s PCIC --%s PCICLK:",toshiba_name,
 555                (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
 556         if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
 557                 int pciclk = 0;
 558                 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 559                         switch ((unsigned long) tx4927_ccfgptr->
 560                                 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 561                         case TX4937_CCFG_PCIDIVMODE_4:
 562                                 pciclk = tx4927_cpu_clock / 4;
 563                                 break;
 564                         case TX4937_CCFG_PCIDIVMODE_4_5:
 565                                 pciclk = tx4927_cpu_clock * 2 / 9;
 566                                 break;
 567                         case TX4937_CCFG_PCIDIVMODE_5:
 568                                 pciclk = tx4927_cpu_clock / 5;
 569                                 break;
 570                         case TX4937_CCFG_PCIDIVMODE_5_5:
 571                                 pciclk = tx4927_cpu_clock * 2 / 11;
 572                                 break;
 573                         case TX4937_CCFG_PCIDIVMODE_8:
 574                                 pciclk = tx4927_cpu_clock / 8;
 575                                 break;
 576                         case TX4937_CCFG_PCIDIVMODE_9:
 577                                 pciclk = tx4927_cpu_clock / 9;
 578                                 break;
 579                         case TX4937_CCFG_PCIDIVMODE_10:
 580                                 pciclk = tx4927_cpu_clock / 10;
 581                                 break;
 582                         case TX4937_CCFG_PCIDIVMODE_11:
 583                                 pciclk = tx4927_cpu_clock / 11;
 584                                 break;
 585                         }
 586
 587                 else
 588                         switch ((unsigned long) tx4927_ccfgptr->
 589                                 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 590                         case TX4927_CCFG_PCIDIVMODE_2_5:
 591                                 pciclk = tx4927_cpu_clock * 2 / 5;
 592                                 break;
 593                         case TX4927_CCFG_PCIDIVMODE_3:
 594                                 pciclk = tx4927_cpu_clock / 3;
 595                                 break;
 596                         case TX4927_CCFG_PCIDIVMODE_5:
 597                                 pciclk = tx4927_cpu_clock / 5;
 598                                 break;
 599                         case TX4927_CCFG_PCIDIVMODE_6:
 600                                 pciclk = tx4927_cpu_clock / 6;
 601                                 break;
 602                         }
 603
 604                 printk("Internal(%dMHz)", pciclk / 1000000);
 605         } else {
 606                 int pciclk = 0;
 607                 int pciclk_setting = *tx4927_pci_clk_ptr;
 608                 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
 609                 case TX4927_PCI_CLK_33:
 610                         pciclk = 33333333;
 611                         break;
 612                 case TX4927_PCI_CLK_25:
 613                         pciclk = 25000000;
 614                         break;
 615                 case TX4927_PCI_CLK_66:
 616                         pciclk = 66666666;
 617                         break;
 618                 case TX4927_PCI_CLK_50:
 619                         pciclk = 50000000;
 620                         break;
 621                 }
 622                 printk("External(%dMHz)", pciclk / 1000000);
 623         }
 624         printk("\n");
 625
 626
 627
 628         /* GB->PCI mappings */
 629         tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
 630         tx4927_pcicptr->g2piogbase = mips_pci_io_base |
 631 #ifdef __BIG_ENDIAN
 632             TX4927_PCIC_G2PIOGBASE_ECHG
 633 #else
 634             TX4927_PCIC_G2PIOGBASE_BSDIS
 635 #endif
 636             ;
 637
 638         tx4927_pcicptr->g2piopbase = 0;
 639
 640         tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
 641         tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
 642 #ifdef __BIG_ENDIAN
 643             TX4927_PCIC_G2PMnGBASE_ECHG
 644 #else
 645             TX4927_PCIC_G2PMnGBASE_BSDIS
 646 #endif
 647             ;
 648         tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
 649
 650         tx4927_pcicptr->g2pmmask[1] = 0;
 651         tx4927_pcicptr->g2pmgbase[1] = 0;
 652         tx4927_pcicptr->g2pmpbase[1] = 0;
 653         tx4927_pcicptr->g2pmmask[2] = 0;
 654         tx4927_pcicptr->g2pmgbase[2] = 0;
 655         tx4927_pcicptr->g2pmpbase[2] = 0;
 656
 657
 658         /* PCI->GB mappings (I/O 256B) */
 659         tx4927_pcicptr->p2giopbase = 0; /* 256B */
 660
 661         /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
 662         tx4927_pcicptr->p2gm0plbase = 0;
 663         tx4927_pcicptr->p2gm0pubase = 0;
 664         tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
 665 #ifdef __BIG_ENDIAN
 666             TX4927_PCIC_P2GMnGBASE_TECHG
 667 #else
 668             TX4927_PCIC_P2GMnGBASE_TBSDIS
 669 #endif
 670             ;
 671
 672         /* PCI->GB mappings (MEM 16MB) -not used */
 673         tx4927_pcicptr->p2gm1plbase = 0xffffffff;
 674 #ifdef CONFIG_TX4927BUG_WORKAROUND
 675         /*
 676          * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
 677          * if P2GM0PUBASE was 0.
 678          */
 679         tx4927_pcicptr->p2gm1pubase = 0;
 680 #else
 681         tx4927_pcicptr->p2gm1pubase = 0xffffffff;
 682 #endif
 683         tx4927_pcicptr->p2gmgbase[1] = 0;
 684
 685         /* PCI->GB mappings (MEM 1MB) -not used */
 686         tx4927_pcicptr->p2gm2pbase = 0xffffffff;
 687         tx4927_pcicptr->p2gmgbase[2] = 0;
 688
 689
 690         /* Enable Initiator Memory 0 Space, I/O Space, Config */
 691         tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
 692         tx4927_pcicptr->pciccfg |=
 693             TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
 694             TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
 695
 696
 697         /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
 698         tx4927_pcicptr->pcicfg1 = 0;
 699
 700         if (tx4927_pcic_trdyto >= 0) {
 701                 tx4927_pcicptr->g2ptocnt &= ~0xff;
 702                 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
 703         }
 704
 705         /* Clear All Local Bus Status */
 706         tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
 707         /* Enable All Local Bus Interrupts */
 708         tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
 709         /* Clear All Initiator Status */
 710         tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
 711         /* Enable All Initiator Interrupts */
 712         tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
 713         /* Clear All PCI Status Error */
 714         tx4927_pcicptr->pcistatus =
 715             (tx4927_pcicptr->pcistatus & 0x0000ffff) |
 716             (TX4927_PCIC_PCISTATUS_ALL << 16);
 717         /* Enable All PCI Status Error Interrupts */
 718         tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
 719
 720         /* PCIC Int => IRC IRQ16 */
 721         tx4927_pcicptr->pcicfg2 =
 722             (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
 723
 724         if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
 725                 /* XXX */
 726         } else {
 727                 /* Reset Bus Arbiter */
 728                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
 729                 /* Enable Bus Arbiter */
 730                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
 731         }
 732
 733         tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
 734             PCI_COMMAND_MEMORY |
 735             PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 736
 737         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 738                                        ":pci setup complete:\n");
 739         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
 740 }
 741
 742 #endif /* CONFIG_PCI */
 743
 744 void toshiba_rbtx4927_restart(char *command)
 745 {
 746         printk(KERN_NOTICE "System Rebooting...\n");
 747
 748         /* enable the s/w reset register */
 749         reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
 750
 751         /* wait for enable to be seen */
 752         while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
 753                 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
 754
 755         /* do a s/w reset */
 756         reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
 757
 758         /* do something passive while waiting for reset */
 759         local_irq_disable();
 760         while (1)
 761                 asm_wait();
 762
 763         /* no return */
 764 }
 765
 766
 767 void toshiba_rbtx4927_halt(void)
 768 {
 769         printk(KERN_NOTICE "System Halted\n");
 770         local_irq_disable();
 771         while (1) {
 772                 asm_wait();
 773         }
 774         /* no return */
 775 }
 776
 777 void toshiba_rbtx4927_power_off(void)
 778 {
 779         toshiba_rbtx4927_halt();
 780         /* no return */
 781 }
 782
 783 void __init toshiba_rbtx4927_setup(void)
 784 {
 785         vu32 cp0_config;
 786         char *argptr;
 787
 788         printk("CPU is %s\n", toshiba_name);
 789
 790         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 791                                        "-\n");
 792
 793         /* f/w leaves this on at startup */
 794         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 795                                        ":Clearing STO_ERL.\n");
 796         clear_c0_status(ST0_ERL);
 797
 798         /* enable caches -- HCP5 does this, pmon does not */
 799         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 800                                        ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
 801         cp0_config = read_c0_config();
 802         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
 803         write_c0_config(cp0_config);
 804
 805 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 806         {
 807                 extern void dump_cp0(char *);
 808                 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
 809         }
 810 #endif
 811
 812         /* setup irq stuff */
 813         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 814                                        ":Setting up tx4927 pic.\n");
 815         TX4927_WR(0xff1ff604, 0x00000400);      /* irq trigger */
 816         TX4927_WR(0xff1ff608, 0x00000000);      /* irq trigger */
 817
 818         /* setup serial stuff */
 819         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 820                                        ":Setting up tx4927 sio.\n");
 821         TX4927_WR(0xff1ff314, 0x00000000);      /* h/w flow control off */
 822         TX4927_WR(0xff1ff414, 0x00000000);      /* h/w flow control off */
 823
 824         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 825                                        "+\n");
 826
 827         set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
 828         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 829                                        ":mips_io_port_base=0x%08lx\n",
 830                                        mips_io_port_base);
 831
 832         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 833                                        ":Resource\n");
 834         ioport_resource.end = 0xffffffff;
 835         iomem_resource.end = 0xffffffff;
 836
 837         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 838                                        ":ResetRoutines\n");
 839         _machine_restart = toshiba_rbtx4927_restart;
 840         _machine_halt = toshiba_rbtx4927_halt;
 841         pm_power_off = toshiba_rbtx4927_power_off;
 842
 843 #ifdef CONFIG_PCI
 844
 845         /* PCIC */
 846         /*
 847            * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
 848            *
 849            * For TX4927:
 850            * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
 851            * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
 852            * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
 853            * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
 854            * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
 855            * i.e. S9[3]: ON (83MHz), OFF (100MHz)
 856            *
 857            * For TX4937:
 858            * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
 859            * PCIDIVMODE[10] is 0.
 860            * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
 861            * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
 862            * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
 863            * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
 864            * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
 865            * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
 866            *
 867          */
 868         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 869                                        "ccfg is %lx, PCIDIVMODE is %x\n",
 870                                        (unsigned long) tx4927_ccfgptr->ccfg,
 871                                        (unsigned long) tx4927_ccfgptr->ccfg &
 872                                        (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
 873                                         TX4937_CCFG_PCIDIVMODE_MASK :
 874                                         TX4927_CCFG_PCIDIVMODE_MASK));
 875
 876         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 877                                        "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
 878                                        (unsigned long) tx4927_ccfgptr->
 879                                        ccfg & TX4927_CCFG_PCI66,
 880                                        (unsigned long) tx4927_ccfgptr->
 881                                        ccfg & TX4927_CCFG_PCIMIDE,
 882                                        (unsigned long) tx4927_ccfgptr->
 883                                        ccfg & TX4927_CCFG_PCIXARB);
 884
 885         if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 886                 switch ((unsigned long)tx4927_ccfgptr->
 887                         ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 888                 case TX4937_CCFG_PCIDIVMODE_8:
 889                 case TX4937_CCFG_PCIDIVMODE_4:
 890                         tx4927_cpu_clock = 266666666;   /* 266MHz */
 891                         break;
 892                 case TX4937_CCFG_PCIDIVMODE_9:
 893                 case TX4937_CCFG_PCIDIVMODE_4_5:
 894                         tx4927_cpu_clock = 300000000;   /* 300MHz */
 895                         break;
 896                 default:
 897                         tx4927_cpu_clock = 333333333;   /* 333MHz */
 898                 }
 899         else
 900                 switch ((unsigned long)tx4927_ccfgptr->
 901                         ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 902                 case TX4927_CCFG_PCIDIVMODE_2_5:
 903                 case TX4927_CCFG_PCIDIVMODE_5:
 904                         tx4927_cpu_clock = 166666666;   /* 166MHz */
 905                         break;
 906                 default:
 907                         tx4927_cpu_clock = 200000000;   /* 200MHz */
 908                 }
 909
 910         /* CCFG */
 911         /* enable Timeout BusError */
 912         if (tx4927_ccfg_toeon)
 913                 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
 914
 915         /* SDRAMC fixup */
 916 #ifdef CONFIG_TX4927BUG_WORKAROUND
 917         /*
 918          * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
 919          * G-bus timeout error detection is incorrect
 920          */
 921         if (tx4927_ccfg_toeon)
 922                 tx4927_sdramcptr->tr |= 0x02000000;     /* RCD:3tck */
 923 #endif
 924
 925         tx4927_pci_setup();
 926         if (tx4927_using_backplane == 1)
 927                 printk("backplane board IS installed\n");
 928         else
 929                 printk("No Backplane \n");
 930
 931         /* this is on ISA bus behind PCI bus, so need PCI up first */
 932 #ifdef CONFIG_TOSHIBA_FPCIB0
 933         {
 934                 if (tx4927_using_backplane) {
 935                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 936                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 937                              ":fpcibo=yes\n");
 938
 939                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 940                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 941                              ":smsc_fdc37m81x_init()\n");
 942                         smsc_fdc37m81x_init(0x3f0);
 943
 944                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 945                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 946                              ":smsc_fdc37m81x_config_beg()\n");
 947                         smsc_fdc37m81x_config_beg();
 948
 949                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 950                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 951                              ":smsc_fdc37m81x_config_set(KBD)\n");
 952                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 953                                                   SMSC_FDC37M81X_KBD);
 954                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 955                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 956                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 957                                                   1);
 958
 959                         smsc_fdc37m81x_config_end();
 960                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 961                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 962                              ":smsc_fdc37m81x_config_end()\n");
 963                 } else {
 964                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 965                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 966                              ":fpcibo=not_found\n");
 967                 }
 968         }
 969 #else
 970         {
 971                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 972                     (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
 973         }
 974 #endif
 975
 976 #endif /* CONFIG_PCI */
 977
 978 #ifdef CONFIG_SERIAL_TXX9
 979         {
 980                 extern int early_serial_txx9_setup(struct uart_port *port);
 981                 int i;
 982                 struct uart_port req;
 983                 for(i = 0; i < 2; i++) {
 984                         memset(&req, 0, sizeof(req));
 985                         req.line = i;
 986                         req.iotype = UPIO_MEM;
 987                         req.membase = (char *)(0xff1ff300 + i * 0x100);
 988                         req.mapbase = 0xff1ff300 + i * 0x100;
 989                         req.irq = 32 + i;
 990                         req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 991                         req.uartclk = 50000000;
 992                         early_serial_txx9_setup(&req);
 993                 }
 994         }
 995 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 996         argptr = prom_getcmdline();
 997         if (strstr(argptr, "console=") == NULL) {
 998                 strcat(argptr, " console=ttyS0,38400");
 999         }
1000 #endif
1001 #endif
1002
1003 #ifdef CONFIG_ROOT_NFS
1004         argptr = prom_getcmdline();
1005         if (strstr(argptr, "root=") == NULL) {
1006                 strcat(argptr, " root=/dev/nfs rw");
1007         }
1008 #endif
1009
1010
1011 #ifdef CONFIG_IP_PNP
1012         argptr = prom_getcmdline();
1013         if (strstr(argptr, "ip=") == NULL) {
1014                 strcat(argptr, " ip=any");
1015         }
1016 #endif
1017
1018
1019         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
1020                                "+\n");
1021 }
1022
1023 #ifdef CONFIG_RTC_DS1742
1024 extern unsigned long rtc_ds1742_get_time(void);
1025 extern int rtc_ds1742_set_time(unsigned long);
1026 extern void rtc_ds1742_wait(void);
1027 #endif
1028
1029 void __init
1030 toshiba_rbtx4927_time_init(void)
1031 {
1032         u32 c1;
1033         u32 c2;
1034
1035         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
1036
1037 #ifdef CONFIG_RTC_DS1742
1038
1039         rtc_mips_get_time = rtc_ds1742_get_time;
1040         rtc_mips_set_time = rtc_ds1742_set_time;
1041
1042         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1043                                        ":rtc_ds1742_init()-\n");
1044         rtc_ds1742_init(0xbc010000);
1045         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1046                                        ":rtc_ds1742_init()+\n");
1047
1048         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1049                                        ":Calibrate mips_hpt_frequency-\n");
1050         rtc_ds1742_wait();
1051
1052         /* get the count */
1053         c1 = read_c0_count();
1054
1055         /* wait for the seconds to change again */
1056         rtc_ds1742_wait();
1057
1058         /* get the count again */
1059         c2 = read_c0_count();
1060
1061         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1062                                        ":Calibrate mips_hpt_frequency+\n");
1063         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1064                                        ":c1=%12u\n", c1);
1065         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1066                                        ":c2=%12u\n", c2);
1067
1068         /* this diff is as close as we are going to get to counter ticks per sec */
1069         mips_hpt_frequency = abs(c2 - c1);
1070         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1071                                        ":f1=%12u\n", mips_hpt_frequency);
1072
1073         /* round to 1/10th of a MHz */
1074         mips_hpt_frequency /= (100 * 1000);
1075         mips_hpt_frequency *= (100 * 1000);
1076         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1077                                        ":f2=%12u\n", mips_hpt_frequency);
1078
1079         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
1080                                        ":mips_hpt_frequency=%uHz (%uMHz)\n",
1081                                        mips_hpt_frequency,
1082                                        mips_hpt_frequency / 1000000);
1083 #else
1084         mips_hpt_frequency = 100000000;
1085 #endif
1086
1087         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1088
1089 }
1090
1091 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1092 {
1093         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1094                                        "-\n");
1095         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1096                                        "+\n");
1097 }