arch/mips/sibyte/common/sb_tbprof.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License
   4  * as published by the Free Software Foundation; either version 2
   5  * of the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  15  *
  16  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
  17  * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
  18  * Copyright (C) 2007 MIPS Technologies, Inc.
  19  *    written by Ralf Baechle <ralf@linux-mips.org>
  20  */
  21
  22 #undef DEBUG
  23
  24 #include <linux/device.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/slab.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/fs.h>
  33 #include <linux/errno.h>
  34 #include <linux/wait.h>
  35 #include <asm/io.h>
  36 #include <asm/sibyte/sb1250.h>
  37
  38 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  39 #include <asm/sibyte/bcm1480_regs.h>
  40 #include <asm/sibyte/bcm1480_scd.h>
  41 #include <asm/sibyte/bcm1480_int.h>
  42 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  43 #include <asm/sibyte/sb1250_regs.h>
  44 #include <asm/sibyte/sb1250_scd.h>
  45 #include <asm/sibyte/sb1250_int.h>
  46 #else
  47 #error invalid SiByte UART configuation
  48 #endif
  49
  50 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  51 #undef K_INT_TRACE_FREEZE
  52 #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
  53 #undef K_INT_PERF_CNT
  54 #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
  55 #endif
  56
  57 #include <asm/system.h>
  58 #include <asm/uaccess.h>
  59
  60 #define SBPROF_TB_MAJOR 240
  61
  62 typedef u64 tb_sample_t[6*256];
  63
  64 enum open_status {
  65         SB_CLOSED,
  66         SB_OPENING,
  67         SB_OPEN
  68 };
  69
  70 struct sbprof_tb {
  71         wait_queue_head_t       tb_sync;
  72         wait_queue_head_t       tb_read;
  73         struct mutex            lock;
  74         enum open_status        open;
  75         tb_sample_t             *sbprof_tbbuf;
  76         int                     next_tb_sample;
  77
  78         volatile int            tb_enable;
  79         volatile int            tb_armed;
  80
  81 };
  82
  83 static struct sbprof_tb sbp;
  84
  85 #define MAX_SAMPLE_BYTES (24*1024*1024)
  86 #define MAX_TBSAMPLE_BYTES (12*1024*1024)
  87
  88 #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
  89 #define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
  90 #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
  91
  92 /* ioctls */
  93 #define SBPROF_ZBSTART          _IOW('s', 0, int)
  94 #define SBPROF_ZBSTOP           _IOW('s', 1, int)
  95 #define SBPROF_ZBWAITFULL       _IOW('s', 2, int)
  96
  97 /*
  98  * Routines for using 40-bit SCD cycle counter
  99  *
 100  * Client responsible for either handling interrupts or making sure
 101  * the cycles counter never saturates, e.g., by doing
 102  * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
 103  */
 104
 105 /*
 106  * Configures SCD counter 0 to count ZCLKs starting from val;
 107  * Configures SCD counters1,2,3 to count nothing.
 108  * Must not be called while gathering ZBbus profiles.
 109  */
 110
 111 #define zclk_timer_init(val) \
 112   __asm__ __volatile__ (".set push;" \
 113                         ".set mips64;" \
 114                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 115                         "sd   %0, 0x10($8);"   /* write val to counter0 */ \
 116                         "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
 117                         ".set pop" \
 118                         : /* no outputs */ \
 119                                                      /* enable, counter0 */ \
 120                         : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
 121                         : /* modifies */ "$8" )
 122
 123
 124 /* Reads SCD counter 0 and puts result in value
 125    unsigned long long val; */
 126 #define zclk_get(val) \
 127   __asm__ __volatile__ (".set push;" \
 128                         ".set mips64;" \
 129                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 130                         "ld   %0, 0x10($8);"   /* write val to counter0 */ \
 131                         ".set pop" \
 132                         : /* outputs */ "=r"(val) \
 133                         : /* inputs */ \
 134                         : /* modifies */ "$8" )
 135
 136 #define DEVNAME "sb_tbprof"
 137
 138 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
 139
 140 /*
 141  * Support for ZBbus sampling using the trace buffer
 142  *
 143  * We use the SCD performance counter interrupt, caused by a Zclk counter
 144  * overflow, to trigger the start of tracing.
 145  *
 146  * We set the trace buffer to sample everything and freeze on
 147  * overflow.
 148  *
 149  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
 150  *
 151  */
 152
 153 static u64 tb_period;
 154
 155 static void arm_tb(void)
 156 {
 157         u64 scdperfcnt;
 158         u64 next = (1ULL << 40) - tb_period;
 159         u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
 160
 161         /*
 162          * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
 163          * trigger start of trace.  XXX vary sampling period
 164          */
 165         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
 166         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 167
 168         /*
 169          * Unfortunately, in Pass 2 we must clear all counters to knock down
 170          * a previous interrupt request.  This means that bus profiling
 171          * requires ALL of the SCD perf counters.
 172          */
 173 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 174         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 175                                                 /* keep counters 0,2,3,4,5,6,7 as is */
 176                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 177                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
 178         __raw_writeq(
 179                      M_SPC_CFG_ENABLE |         /* enable counting */
 180                      M_SPC_CFG_CLEAR |          /* clear all counters */
 181                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 182                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
 183 #else
 184         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 185                                                 /* keep counters 0,2,3 as is */
 186                      M_SPC_CFG_ENABLE |         /* enable counting */
 187                      M_SPC_CFG_CLEAR |          /* clear all counters */
 188                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 189                      IOADDR(A_SCD_PERF_CNT_CFG));
 190 #endif
 191         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
 192         /* Reset the trace buffer */
 193         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 194 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
 195         /* XXXKW may want to expose control to the data-collector */
 196         tb_options |= M_SCD_TRACE_CFG_FORCECNT;
 197 #endif
 198         __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
 199         sbp.tb_armed = 1;
 200 }
 201
 202 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
 203 {
 204         int i;
 205
 206         pr_debug(DEVNAME ": tb_intr\n");
 207
 208         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
 209                 /* XXX should use XKPHYS to make writes bypass L2 */
 210                 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
 211                 /* Read out trace */
 212                 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
 213                              IOADDR(A_SCD_TRACE_CFG));
 214                 __asm__ __volatile__ ("sync" : : : "memory");
 215                 /* Loop runs backwards because bundles are read out in reverse order */
 216                 for (i = 256 * 6; i > 0; i -= 6) {
 217                         /* Subscripts decrease to put bundle in the order */
 218                         /*   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
 219                         p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 220                         /* read t2 hi */
 221                         p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 222                         /* read t2 lo */
 223                         p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 224                         /* read t1 hi */
 225                         p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 226                         /* read t1 lo */
 227                         p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 228                         /* read t0 hi */
 229                         p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 230                         /* read t0 lo */
 231                 }
 232                 if (!sbp.tb_enable) {
 233                         pr_debug(DEVNAME ": tb_intr shutdown\n");
 234                         __raw_writeq(M_SCD_TRACE_CFG_RESET,
 235                                      IOADDR(A_SCD_TRACE_CFG));
 236                         sbp.tb_armed = 0;
 237                         wake_up_interruptible(&sbp.tb_sync);
 238                 } else {
 239                         /* knock down current interrupt and get another one later */
 240                         arm_tb();
 241                 }
 242         } else {
 243                 /* No more trace buffer samples */
 244                 pr_debug(DEVNAME ": tb_intr full\n");
 245                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 246                 sbp.tb_armed = 0;
 247                 if (!sbp.tb_enable)
 248                         wake_up_interruptible(&sbp.tb_sync);
 249                 wake_up_interruptible(&sbp.tb_read);
 250         }
 251         return IRQ_HANDLED;
 252 }
 253
 254 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
 255 {
 256         printk(DEVNAME ": unexpected pc_intr");
 257         return IRQ_NONE;
 258 }
 259
 260 /*
 261  * Requires: Already called zclk_timer_init with a value that won't
 262  *           saturate 40 bits.  No subsequent use of SCD performance counters
 263  *           or trace buffer.
 264  */
 265
 266 static int sbprof_zbprof_start(struct file *filp)
 267 {
 268         u64 scdperfcnt;
 269         int err;
 270
 271         if (xchg(&sbp.tb_enable, 1))
 272                 return -EBUSY;
 273
 274         pr_debug(DEVNAME ": starting\n");
 275
 276         sbp.next_tb_sample = 0;
 277         filp->f_pos = 0;
 278
 279         err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
 280                            DEVNAME " trace freeze", &sbp);
 281         if (err)
 282                 return -EBUSY;
 283
 284         /* Make sure there isn't a perf-cnt interrupt waiting */
 285         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 286         /* Disable and clear counters, override SRC_1 */
 287         __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
 288                      M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
 289                      IOADDR(A_SCD_PERF_CNT_CFG));
 290
 291         /*
 292          * We grab this interrupt to prevent others from trying to use
 293          * it, even though we don't want to service the interrupts
 294          * (they only feed into the trace-on-interrupt mechanism)
 295          */
 296         if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
 297                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 298                 return -EBUSY;
 299         }
 300
 301         /*
 302          * I need the core to mask these, but the interrupt mapper to
 303          *  pass them through.  I am exploiting my knowledge that
 304          *  cp0_status masks out IP[5]. krw
 305          */
 306 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 307         __raw_writeq(K_BCM1480_INT_MAP_I3,
 308                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
 309                             ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
 310 #else
 311         __raw_writeq(K_INT_MAP_I3,
 312                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 313                             (K_INT_PERF_CNT << 3)));
 314 #endif
 315
 316         /* Initialize address traps */
 317         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
 318         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
 319         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
 320         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
 321
 322         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
 323         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
 324         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
 325         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
 326
 327         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
 328         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
 329         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
 330         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 331
 332         /* Initialize Trace Event 0-7 */
 333         /*                              when interrupt  */
 334         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
 335         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
 336         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
 337         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
 338         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
 339         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
 340         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
 341         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 342
 343         /* Initialize Trace Sequence 0-7 */
 344         /*                                   Start on event 0 (interrupt) */
 345         __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
 346                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
 347         /*                        dsamp when d used | asamp when a used */
 348         __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
 349                      K_SCD_TRSEQ_TRIGGER_ALL,
 350                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
 351         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
 352         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
 353         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
 354         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
 355         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
 356         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 357
 358         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
 359 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 360         __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
 361                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
 362 #else
 363         __raw_writeq(1ULL << K_INT_PERF_CNT,
 364                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
 365 #endif
 366         arm_tb();
 367
 368         pr_debug(DEVNAME ": done starting\n");
 369
 370         return 0;
 371 }
 372
 373 static int sbprof_zbprof_stop(void)
 374 {
 375         int err = 0;
 376
 377         pr_debug(DEVNAME ": stopping\n");
 378
 379         if (sbp.tb_enable) {
 380                 /*
 381                  * XXXKW there is a window here where the intr handler may run,
 382                  * see the disable, and do the wake_up before this sleep
 383                  * happens.
 384                  */
 385                 pr_debug(DEVNAME ": wait for disarm\n");
 386                 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
 387                 pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
 388
 389                 if (err)
 390                         return err;
 391
 392                 sbp.tb_enable = 0;
 393                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 394                 free_irq(K_INT_PERF_CNT, &sbp);
 395         }
 396
 397         pr_debug(DEVNAME ": done stopping\n");
 398
 399         return err;
 400 }
 401
 402 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 403 {
 404         int minor;
 405
 406         minor = iminor(inode);
 407         if (minor != 0)
 408                 return -ENODEV;
 409
 410         if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
 411                 return -EBUSY;
 412
 413         memset(&sbp, 0, sizeof(struct sbprof_tb));
 414         sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
 415         if (!sbp.sbprof_tbbuf)
 416                 return -ENOMEM;
 417         memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
 418         init_waitqueue_head(&sbp.tb_sync);
 419         init_waitqueue_head(&sbp.tb_read);
 420         mutex_init(&sbp.lock);
 421
 422         sbp.open = SB_OPEN;
 423
 424         return 0;
 425 }
 426
 427 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 428 {
 429         int minor;
 430
 431         minor = iminor(inode);
 432         if (minor != 0 || !sbp.open)
 433                 return -ENODEV;
 434
 435         mutex_lock(&sbp.lock);
 436
 437         if (sbp.tb_armed || sbp.tb_enable)
 438                 sbprof_zbprof_stop();
 439
 440         vfree(sbp.sbprof_tbbuf);
 441         sbp.open = 0;
 442
 443         mutex_unlock(&sbp.lock);
 444
 445         return 0;
 446 }
 447
 448 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
 449                               size_t size, loff_t *offp)
 450 {
 451         int cur_sample, sample_off, cur_count, sample_left;
 452         char *src;
 453         int   count   =  0;
 454         char *dest    =  buf;
 455         long  cur_off = *offp;
 456
 457         if (!access_ok(VERIFY_WRITE, buf, size))
 458                 return -EFAULT;
 459
 460         mutex_lock(&sbp.lock);
 461
 462         count = 0;
 463         cur_sample = cur_off / TB_SAMPLE_SIZE;
 464         sample_off = cur_off % TB_SAMPLE_SIZE;
 465         sample_left = TB_SAMPLE_SIZE - sample_off;
 466
 467         while (size && (cur_sample < sbp.next_tb_sample)) {
 468                 int err;
 469
 470                 cur_count = size < sample_left ? size : sample_left;
 471                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
 472                 err = __copy_to_user(dest, src, cur_count);
 473                 if (err) {
 474                         *offp = cur_off + cur_count - err;
 475                         mutex_unlock(&sbp.lock);
 476                         return err;
 477                 }
 478                 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
 479                          cur_sample, cur_count);
 480                 size -= cur_count;
 481                 sample_left -= cur_count;
 482                 if (!sample_left) {
 483                         cur_sample++;
 484                         sample_off = 0;
 485                         sample_left = TB_SAMPLE_SIZE;
 486                 } else {
 487                         sample_off += cur_count;
 488                 }
 489                 cur_off += cur_count;
 490                 dest += cur_count;
 491                 count += cur_count;
 492         }
 493         *offp = cur_off;
 494         mutex_unlock(&sbp.lock);
 495
 496         return count;
 497 }
 498
 499 static long sbprof_tb_ioctl(struct file *filp,
 500                             unsigned int command,
 501                             unsigned long arg)
 502 {
 503         int err = 0;
 504
 505         switch (command) {
 506         case SBPROF_ZBSTART:
 507                 mutex_lock(&sbp.lock);
 508                 err = sbprof_zbprof_start(filp);
 509                 mutex_unlock(&sbp.lock);
 510                 break;
 511
 512         case SBPROF_ZBSTOP:
 513                 mutex_lock(&sbp.lock);
 514                 err = sbprof_zbprof_stop();
 515                 mutex_unlock(&sbp.lock);
 516                 break;
 517
 518         case SBPROF_ZBWAITFULL: {
 519                 err = wait_event_interruptible(sbp.tb_read, TB_FULL);
 520                 if (err)
 521                         break;
 522
 523                 err = put_user(TB_FULL, (int *) arg);
 524                 break;
 525         }
 526
 527         default:
 528                 err = -EINVAL;
 529                 break;
 530         }
 531
 532         return err;
 533 }
 534
 535 static const struct file_operations sbprof_tb_fops = {
 536         .owner          = THIS_MODULE,
 537         .open           = sbprof_tb_open,
 538         .release        = sbprof_tb_release,
 539         .read           = sbprof_tb_read,
 540         .unlocked_ioctl = sbprof_tb_ioctl,
 541         .compat_ioctl   = sbprof_tb_ioctl,
 542         .mmap           = NULL,
 543 };
 544
 545 static struct class *tb_class;
 546 static struct device *tb_dev;
 547
 548 static int __init sbprof_tb_init(void)
 549 {
 550         struct device *dev;
 551         struct class *tbc;
 552         int err;
 553
 554         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
 555                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
 556                        SBPROF_TB_MAJOR);
 557                 return -EIO;
 558         }
 559
 560         tbc = class_create(THIS_MODULE, "sb_tracebuffer");
 561         if (IS_ERR(tbc)) {
 562                 err = PTR_ERR(tbc);
 563                 goto out_chrdev;
 564         }
 565
 566         tb_class = tbc;
 567
 568         dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), "tb");
 569         if (IS_ERR(dev)) {
 570                 err = PTR_ERR(dev);
 571                 goto out_class;
 572         }
 573         tb_dev = dev;
 574
 575         sbp.open = 0;
 576         tb_period = zbbus_mhz * 10000LL;
 577         pr_info(DEVNAME ": initialized - tb_period = %lld\n",
 578                 (long long) tb_period);
 579         return 0;
 580
 581 out_class:
 582         class_destroy(tb_class);
 583 out_chrdev:
 584         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 585
 586         return err;
 587 }
 588
 589 static void __exit sbprof_tb_cleanup(void)
 590 {
 591         device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
 592         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 593         class_destroy(tb_class);
 594 }
 595
 596 module_init(sbprof_tb_init);
 597 module_exit(sbprof_tb_cleanup);
 598
 599 MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
 600 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
 601 MODULE_LICENSE("GPL");