arch/mips/sibyte/common/sb_tbprof.c

   1 /*
   2  * This program is free software; you can redistribute it and/or
   3  * modify it under the terms of the GNU General Public License
   4  * as published by the Free Software Foundation; either version 2
   5  * of the License, or (at your option) any later version.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  15  *
  16  * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
  17  * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
  18  * Copyright (C) 2007 MIPS Technologies, Inc.
  19  *    written by Ralf Baechle <ralf@linux-mips.org>
  20  */
  21
  22 #undef DEBUG
  23
  24 #include <linux/device.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/vmalloc.h>
  31 #include <linux/fs.h>
  32 #include <linux/errno.h>
  33 #include <linux/wait.h>
  34 #include <asm/io.h>
  35 #include <asm/sibyte/sb1250.h>
  36
  37 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  38 #include <asm/sibyte/bcm1480_regs.h>
  39 #include <asm/sibyte/bcm1480_scd.h>
  40 #include <asm/sibyte/bcm1480_int.h>
  41 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
  42 #include <asm/sibyte/sb1250_regs.h>
  43 #include <asm/sibyte/sb1250_scd.h>
  44 #include <asm/sibyte/sb1250_int.h>
  45 #else
  46 #error invalid SiByte UART configuration
  47 #endif
  48
  49 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
  50 #undef K_INT_TRACE_FREEZE
  51 #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE
  52 #undef K_INT_PERF_CNT
  53 #define K_INT_PERF_CNT K_BCM1480_INT_PERF_CNT
  54 #endif
  55
  56 #include <asm/uaccess.h>
  57
  58 #define SBPROF_TB_MAJOR 240
  59
  60 typedef u64 tb_sample_t[6*256];
  61
  62 enum open_status {
  63         SB_CLOSED,
  64         SB_OPENING,
  65         SB_OPEN
  66 };
  67
  68 struct sbprof_tb {
  69         wait_queue_head_t       tb_sync;
  70         wait_queue_head_t       tb_read;
  71         struct mutex            lock;
  72         enum open_status        open;
  73         tb_sample_t             *sbprof_tbbuf;
  74         int                     next_tb_sample;
  75
  76         volatile int            tb_enable;
  77         volatile int            tb_armed;
  78
  79 };
  80
  81 static struct sbprof_tb sbp;
  82
  83 #define MAX_SAMPLE_BYTES (24*1024*1024)
  84 #define MAX_TBSAMPLE_BYTES (12*1024*1024)
  85
  86 #define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
  87 #define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
  88 #define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
  89
  90 /* ioctls */
  91 #define SBPROF_ZBSTART          _IOW('s', 0, int)
  92 #define SBPROF_ZBSTOP           _IOW('s', 1, int)
  93 #define SBPROF_ZBWAITFULL       _IOW('s', 2, int)
  94
  95 /*
  96  * Routines for using 40-bit SCD cycle counter
  97  *
  98  * Client responsible for either handling interrupts or making sure
  99  * the cycles counter never saturates, e.g., by doing
 100  * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
 101  */
 102
 103 /*
 104  * Configures SCD counter 0 to count ZCLKs starting from val;
 105  * Configures SCD counters1,2,3 to count nothing.
 106  * Must not be called while gathering ZBbus profiles.
 107  */
 108
 109 #define zclk_timer_init(val) \
 110   __asm__ __volatile__ (".set push;" \
 111                         ".set mips64;" \
 112                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 113                         "sd   %0, 0x10($8);"   /* write val to counter0 */ \
 114                         "sd   %1, 0($8);"      /* config counter0 for zclks*/ \
 115                         ".set pop" \
 116                         : /* no outputs */ \
 117                                                      /* enable, counter0 */ \
 118                         : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
 119                         : /* modifies */ "$8" )
 120
 121
 122 /* Reads SCD counter 0 and puts result in value
 123    unsigned long long val; */
 124 #define zclk_get(val) \
 125   __asm__ __volatile__ (".set push;" \
 126                         ".set mips64;" \
 127                         "la   $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
 128                         "ld   %0, 0x10($8);"   /* write val to counter0 */ \
 129                         ".set pop" \
 130                         : /* outputs */ "=r"(val) \
 131                         : /* inputs */ \
 132                         : /* modifies */ "$8" )
 133
 134 #define DEVNAME "sb_tbprof"
 135
 136 #define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
 137
 138 /*
 139  * Support for ZBbus sampling using the trace buffer
 140  *
 141  * We use the SCD performance counter interrupt, caused by a Zclk counter
 142  * overflow, to trigger the start of tracing.
 143  *
 144  * We set the trace buffer to sample everything and freeze on
 145  * overflow.
 146  *
 147  * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
 148  *
 149  */
 150
 151 static u64 tb_period;
 152
 153 static void arm_tb(void)
 154 {
 155         u64 scdperfcnt;
 156         u64 next = (1ULL << 40) - tb_period;
 157         u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
 158
 159         /*
 160          * Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
 161          * trigger start of trace.  XXX vary sampling period
 162          */
 163         __raw_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
 164         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 165
 166         /*
 167          * Unfortunately, in Pass 2 we must clear all counters to knock down
 168          * a previous interrupt request.  This means that bus profiling
 169          * requires ALL of the SCD perf counters.
 170          */
 171 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 172         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 173                                                 /* keep counters 0,2,3,4,5,6,7 as is */
 174                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 175                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG0));
 176         __raw_writeq(
 177                      M_SPC_CFG_ENABLE |         /* enable counting */
 178                      M_SPC_CFG_CLEAR |          /* clear all counters */
 179                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 180                      IOADDR(A_BCM1480_SCD_PERF_CNT_CFG1));
 181 #else
 182         __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) |
 183                                                 /* keep counters 0,2,3 as is */
 184                      M_SPC_CFG_ENABLE |         /* enable counting */
 185                      M_SPC_CFG_CLEAR |          /* clear all counters */
 186                      V_SPC_CFG_SRC1(1),         /* counter 1 counts cycles */
 187                      IOADDR(A_SCD_PERF_CNT_CFG));
 188 #endif
 189         __raw_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
 190         /* Reset the trace buffer */
 191         __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 192 #if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
 193         /* XXXKW may want to expose control to the data-collector */
 194         tb_options |= M_SCD_TRACE_CFG_FORCECNT;
 195 #endif
 196         __raw_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
 197         sbp.tb_armed = 1;
 198 }
 199
 200 static irqreturn_t sbprof_tb_intr(int irq, void *dev_id)
 201 {
 202         int i;
 203
 204         pr_debug(DEVNAME ": tb_intr\n");
 205
 206         if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
 207                 /* XXX should use XKPHYS to make writes bypass L2 */
 208                 u64 *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
 209                 /* Read out trace */
 210                 __raw_writeq(M_SCD_TRACE_CFG_START_READ,
 211                              IOADDR(A_SCD_TRACE_CFG));
 212                 __asm__ __volatile__ ("sync" : : : "memory");
 213                 /* Loop runs backwards because bundles are read out in reverse order */
 214                 for (i = 256 * 6; i > 0; i -= 6) {
 215                         /* Subscripts decrease to put bundle in the order */
 216                         /*   t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi */
 217                         p[i - 1] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 218                         /* read t2 hi */
 219                         p[i - 2] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 220                         /* read t2 lo */
 221                         p[i - 3] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 222                         /* read t1 hi */
 223                         p[i - 4] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 224                         /* read t1 lo */
 225                         p[i - 5] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 226                         /* read t0 hi */
 227                         p[i - 6] = __raw_readq(IOADDR(A_SCD_TRACE_READ));
 228                         /* read t0 lo */
 229                 }
 230                 if (!sbp.tb_enable) {
 231                         pr_debug(DEVNAME ": tb_intr shutdown\n");
 232                         __raw_writeq(M_SCD_TRACE_CFG_RESET,
 233                                      IOADDR(A_SCD_TRACE_CFG));
 234                         sbp.tb_armed = 0;
 235                         wake_up_interruptible(&sbp.tb_sync);
 236                 } else {
 237                         /* knock down current interrupt and get another one later */
 238                         arm_tb();
 239                 }
 240         } else {
 241                 /* No more trace buffer samples */
 242                 pr_debug(DEVNAME ": tb_intr full\n");
 243                 __raw_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
 244                 sbp.tb_armed = 0;
 245                 if (!sbp.tb_enable)
 246                         wake_up_interruptible(&sbp.tb_sync);
 247                 wake_up_interruptible(&sbp.tb_read);
 248         }
 249         return IRQ_HANDLED;
 250 }
 251
 252 static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
 253 {
 254         printk(DEVNAME ": unexpected pc_intr");
 255         return IRQ_NONE;
 256 }
 257
 258 /*
 259  * Requires: Already called zclk_timer_init with a value that won't
 260  *           saturate 40 bits.  No subsequent use of SCD performance counters
 261  *           or trace buffer.
 262  */
 263
 264 static int sbprof_zbprof_start(struct file *filp)
 265 {
 266         u64 scdperfcnt;
 267         int err;
 268
 269         if (xchg(&sbp.tb_enable, 1))
 270                 return -EBUSY;
 271
 272         pr_debug(DEVNAME ": starting\n");
 273
 274         sbp.next_tb_sample = 0;
 275         filp->f_pos = 0;
 276
 277         err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
 278                           DEVNAME " trace freeze", &sbp);
 279         if (err)
 280                 return -EBUSY;
 281
 282         /* Make sure there isn't a perf-cnt interrupt waiting */
 283         scdperfcnt = __raw_readq(IOADDR(A_SCD_PERF_CNT_CFG));
 284         /* Disable and clear counters, override SRC_1 */
 285         __raw_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
 286                      M_SPC_CFG_ENABLE | M_SPC_CFG_CLEAR | V_SPC_CFG_SRC1(1),
 287                      IOADDR(A_SCD_PERF_CNT_CFG));
 288
 289         /*
 290          * We grab this interrupt to prevent others from trying to use
 291          * it, even though we don't want to service the interrupts
 292          * (they only feed into the trace-on-interrupt mechanism)
 293          */
 294         if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
 295                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 296                 return -EBUSY;
 297         }
 298
 299         /*
 300          * I need the core to mask these, but the interrupt mapper to
 301          *  pass them through.  I am exploiting my knowledge that
 302          *  cp0_status masks out IP[5]. krw
 303          */
 304 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 305         __raw_writeq(K_BCM1480_INT_MAP_I3,
 306                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) +
 307                             ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3)));
 308 #else
 309         __raw_writeq(K_INT_MAP_I3,
 310                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 311                             (K_INT_PERF_CNT << 3)));
 312 #endif
 313
 314         /* Initialize address traps */
 315         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
 316         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
 317         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
 318         __raw_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
 319
 320         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
 321         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
 322         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
 323         __raw_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
 324
 325         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
 326         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
 327         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
 328         __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 329
 330         /* Initialize Trace Event 0-7 */
 331         /*                              when interrupt  */
 332         __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
 333         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
 334         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
 335         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
 336         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
 337         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
 338         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
 339         __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
 340
 341         /* Initialize Trace Sequence 0-7 */
 342         /*                                   Start on event 0 (interrupt) */
 343         __raw_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
 344                      IOADDR(A_SCD_TRACE_SEQUENCE_0));
 345         /*                        dsamp when d used | asamp when a used */
 346         __raw_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
 347                      K_SCD_TRSEQ_TRIGGER_ALL,
 348                      IOADDR(A_SCD_TRACE_SEQUENCE_1));
 349         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
 350         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
 351         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
 352         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
 353         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
 354         __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
 355
 356         /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
 357 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 358         __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f),
 359                      IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L)));
 360 #else
 361         __raw_writeq(1ULL << K_INT_PERF_CNT,
 362                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
 363 #endif
 364         arm_tb();
 365
 366         pr_debug(DEVNAME ": done starting\n");
 367
 368         return 0;
 369 }
 370
 371 static int sbprof_zbprof_stop(void)
 372 {
 373         int err = 0;
 374
 375         pr_debug(DEVNAME ": stopping\n");
 376
 377         if (sbp.tb_enable) {
 378                 /*
 379                  * XXXKW there is a window here where the intr handler may run,
 380                  * see the disable, and do the wake_up before this sleep
 381                  * happens.
 382                  */
 383                 pr_debug(DEVNAME ": wait for disarm\n");
 384                 err = wait_event_interruptible(sbp.tb_sync, !sbp.tb_armed);
 385                 pr_debug(DEVNAME ": disarm complete, stat %d\n", err);
 386
 387                 if (err)
 388                         return err;
 389
 390                 sbp.tb_enable = 0;
 391                 free_irq(K_INT_TRACE_FREEZE, &sbp);
 392                 free_irq(K_INT_PERF_CNT, &sbp);
 393         }
 394
 395         pr_debug(DEVNAME ": done stopping\n");
 396
 397         return err;
 398 }
 399
 400 static int sbprof_tb_open(struct inode *inode, struct file *filp)
 401 {
 402         int minor;
 403
 404         minor = iminor(inode);
 405         if (minor != 0)
 406                 return -ENODEV;
 407
 408         if (xchg(&sbp.open, SB_OPENING) != SB_CLOSED)
 409                 return -EBUSY;
 410
 411         memset(&sbp, 0, sizeof(struct sbprof_tb));
 412         sbp.sbprof_tbbuf = vzalloc(MAX_TBSAMPLE_BYTES);
 413         if (!sbp.sbprof_tbbuf) {
 414                 sbp.open = SB_CLOSED;
 415                 wmb();
 416                 return -ENOMEM;
 417         }
 418
 419         init_waitqueue_head(&sbp.tb_sync);
 420         init_waitqueue_head(&sbp.tb_read);
 421         mutex_init(&sbp.lock);
 422
 423         sbp.open = SB_OPEN;
 424         wmb();
 425
 426         return 0;
 427 }
 428
 429 static int sbprof_tb_release(struct inode *inode, struct file *filp)
 430 {
 431         int minor;
 432
 433         minor = iminor(inode);
 434         if (minor != 0 || sbp.open != SB_CLOSED)
 435                 return -ENODEV;
 436
 437         mutex_lock(&sbp.lock);
 438
 439         if (sbp.tb_armed || sbp.tb_enable)
 440                 sbprof_zbprof_stop();
 441
 442         vfree(sbp.sbprof_tbbuf);
 443         sbp.open = SB_CLOSED;
 444         wmb();
 445
 446         mutex_unlock(&sbp.lock);
 447
 448         return 0;
 449 }
 450
 451 static ssize_t sbprof_tb_read(struct file *filp, char *buf,
 452                               size_t size, loff_t *offp)
 453 {
 454         int cur_sample, sample_off, cur_count, sample_left;
 455         char *src;
 456         int   count   =  0;
 457         char *dest    =  buf;
 458         long  cur_off = *offp;
 459
 460         if (!access_ok(VERIFY_WRITE, buf, size))
 461                 return -EFAULT;
 462
 463         mutex_lock(&sbp.lock);
 464
 465         count = 0;
 466         cur_sample = cur_off / TB_SAMPLE_SIZE;
 467         sample_off = cur_off % TB_SAMPLE_SIZE;
 468         sample_left = TB_SAMPLE_SIZE - sample_off;
 469
 470         while (size && (cur_sample < sbp.next_tb_sample)) {
 471                 int err;
 472
 473                 cur_count = size < sample_left ? size : sample_left;
 474                 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
 475                 err = __copy_to_user(dest, src, cur_count);
 476                 if (err) {
 477                         *offp = cur_off + cur_count - err;
 478                         mutex_unlock(&sbp.lock);
 479                         return err;
 480                 }
 481                 pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
 482                          cur_sample, cur_count);
 483                 size -= cur_count;
 484                 sample_left -= cur_count;
 485                 if (!sample_left) {
 486                         cur_sample++;
 487                         sample_off = 0;
 488                         sample_left = TB_SAMPLE_SIZE;
 489                 } else {
 490                         sample_off += cur_count;
 491                 }
 492                 cur_off += cur_count;
 493                 dest += cur_count;
 494                 count += cur_count;
 495         }
 496         *offp = cur_off;
 497         mutex_unlock(&sbp.lock);
 498
 499         return count;
 500 }
 501
 502 static long sbprof_tb_ioctl(struct file *filp,
 503                             unsigned int command,
 504                             unsigned long arg)
 505 {
 506         int err = 0;
 507
 508         switch (command) {
 509         case SBPROF_ZBSTART:
 510                 mutex_lock(&sbp.lock);
 511                 err = sbprof_zbprof_start(filp);
 512                 mutex_unlock(&sbp.lock);
 513                 break;
 514
 515         case SBPROF_ZBSTOP:
 516                 mutex_lock(&sbp.lock);
 517                 err = sbprof_zbprof_stop();
 518                 mutex_unlock(&sbp.lock);
 519                 break;
 520
 521         case SBPROF_ZBWAITFULL: {
 522                 err = wait_event_interruptible(sbp.tb_read, TB_FULL);
 523                 if (err)
 524                         break;
 525
 526                 err = put_user(TB_FULL, (int *) arg);
 527                 break;
 528         }
 529
 530         default:
 531                 err = -EINVAL;
 532                 break;
 533         }
 534
 535         return err;
 536 }
 537
 538 static const struct file_operations sbprof_tb_fops = {
 539         .owner          = THIS_MODULE,
 540         .open           = sbprof_tb_open,
 541         .release        = sbprof_tb_release,
 542         .read           = sbprof_tb_read,
 543         .unlocked_ioctl = sbprof_tb_ioctl,
 544         .compat_ioctl   = sbprof_tb_ioctl,
 545         .mmap           = NULL,
 546         .llseek         = default_llseek,
 547 };
 548
 549 static struct class *tb_class;
 550 static struct device *tb_dev;
 551
 552 static int __init sbprof_tb_init(void)
 553 {
 554         struct device *dev;
 555         struct class *tbc;
 556         int err;
 557
 558         if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
 559                 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
 560                        SBPROF_TB_MAJOR);
 561                 return -EIO;
 562         }
 563
 564         tbc = class_create(THIS_MODULE, "sb_tracebuffer");
 565         if (IS_ERR(tbc)) {
 566                 err = PTR_ERR(tbc);
 567                 goto out_chrdev;
 568         }
 569
 570         tb_class = tbc;
 571
 572         dev = device_create(tbc, NULL, MKDEV(SBPROF_TB_MAJOR, 0), NULL, "tb");
 573         if (IS_ERR(dev)) {
 574                 err = PTR_ERR(dev);
 575                 goto out_class;
 576         }
 577         tb_dev = dev;
 578
 579         sbp.open = SB_CLOSED;
 580         wmb();
 581         tb_period = zbbus_mhz * 10000LL;
 582         pr_info(DEVNAME ": initialized - tb_period = %lld\n",
 583                 (long long) tb_period);
 584         return 0;
 585
 586 out_class:
 587         class_destroy(tb_class);
 588 out_chrdev:
 589         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 590
 591         return err;
 592 }
 593
 594 static void __exit sbprof_tb_cleanup(void)
 595 {
 596         device_destroy(tb_class, MKDEV(SBPROF_TB_MAJOR, 0));
 597         unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
 598         class_destroy(tb_class);
 599 }
 600
 601 module_init(sbprof_tb_init);
 602 module_exit(sbprof_tb_cleanup);
 603
 604 MODULE_ALIAS_CHARDEV_MAJOR(SBPROF_TB_MAJOR);
 605 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
 606 MODULE_LICENSE("GPL");