arch/mips/oprofile/op_model_mipsxx.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004, 05, 06 by Ralf Baechle
   7  * Copyright (C) 2005 by MIPS Technologies, Inc.
   8  */
   9 #include <linux/oprofile.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/smp.h>
  12 #include <asm/irq_regs.h>
  13
  14 #include "op_impl.h"
  15
  16 #define M_PERFCTL_EXL                   (1UL      <<  0)
  17 #define M_PERFCTL_KERNEL                (1UL      <<  1)
  18 #define M_PERFCTL_SUPERVISOR            (1UL      <<  2)
  19 #define M_PERFCTL_USER                  (1UL      <<  3)
  20 #define M_PERFCTL_INTERRUPT_ENABLE      (1UL      <<  4)
  21 #define M_PERFCTL_EVENT(event)          ((event)  << 5)
  22 #define M_PERFCTL_VPEID(vpe)            ((vpe)    << 16)
  23 #define M_PERFCTL_MT_EN(filter)         ((filter) << 20)
  24 #define    M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
  25 #define    M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
  26 #define    M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
  27 #define M_PERFCTL_TCID(tcid)            ((tcid)   << 22)
  28 #define M_PERFCTL_WIDE                  (1UL      << 30)
  29 #define M_PERFCTL_MORE                  (1UL      << 31)
  30
  31 #define M_COUNTER_OVERFLOW              (1UL      << 31)
  32
  33 #ifdef CONFIG_MIPS_MT_SMP
  34 #define WHAT            (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id()))
  35 #define vpe_id()        smp_processor_id()
  36 #else
  37 #define WHAT            0
  38 #define vpe_id()        smp_processor_id()
  39 #endif
  40
  41 #define __define_perf_accessors(r, n, np)                               \
  42                                                                         \
  43 static inline unsigned int r_c0_ ## r ## n(void)                        \
  44 {                                                                       \
  45         unsigned int cpu = vpe_id();                                    \
  46                                                                         \
  47         switch (cpu) {                                                  \
  48         case 0:                                                         \
  49                 return read_c0_ ## r ## n();                            \
  50         case 1:                                                         \
  51                 return read_c0_ ## r ## np();                           \
  52         default:                                                        \
  53                 BUG();                                                  \
  54         }                                                               \
  55         return 0;                                                       \
  56 }                                                                       \
  57                                                                         \
  58 static inline void w_c0_ ## r ## n(unsigned int value)                  \
  59 {                                                                       \
  60         unsigned int cpu = vpe_id();                                    \
  61                                                                         \
  62         switch (cpu) {                                                  \
  63         case 0:                                                         \
  64                 write_c0_ ## r ## n(value);                             \
  65                 return;                                                 \
  66         case 1:                                                         \
  67                 write_c0_ ## r ## np(value);                            \
  68                 return;                                                 \
  69         default:                                                        \
  70                 BUG();                                                  \
  71         }                                                               \
  72         return;                                                         \
  73 }                                                                       \
  74
  75 __define_perf_accessors(perfcntr, 0, 2)
  76 __define_perf_accessors(perfcntr, 1, 3)
  77 __define_perf_accessors(perfcntr, 2, 2)
  78 __define_perf_accessors(perfcntr, 3, 2)
  79
  80 __define_perf_accessors(perfctrl, 0, 2)
  81 __define_perf_accessors(perfctrl, 1, 3)
  82 __define_perf_accessors(perfctrl, 2, 2)
  83 __define_perf_accessors(perfctrl, 3, 2)
  84
  85 struct op_mips_model op_model_mipsxx_ops;
  86
  87 static struct mipsxx_register_config {
  88         unsigned int control[4];
  89         unsigned int counter[4];
  90 } reg;
  91
  92 /* Compute all of the registers in preparation for enabling profiling.  */
  93
  94 static void mipsxx_reg_setup(struct op_counter_config *ctr)
  95 {
  96         unsigned int counters = op_model_mipsxx_ops.num_counters;
  97         int i;
  98
  99         /* Compute the performance counter control word.  */
 100         /* For now count kernel and user mode */
 101         for (i = 0; i < counters; i++) {
 102                 reg.control[i] = 0;
 103                 reg.counter[i] = 0;
 104
 105                 if (!ctr[i].enabled)
 106                         continue;
 107
 108                 reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
 109                                  M_PERFCTL_INTERRUPT_ENABLE;
 110                 if (ctr[i].kernel)
 111                         reg.control[i] |= M_PERFCTL_KERNEL;
 112                 if (ctr[i].user)
 113                         reg.control[i] |= M_PERFCTL_USER;
 114                 if (ctr[i].exl)
 115                         reg.control[i] |= M_PERFCTL_EXL;
 116                 reg.counter[i] = 0x80000000 - ctr[i].count;
 117         }
 118 }
 119
 120 /* Program all of the registers in preparation for enabling profiling.  */
 121
 122 static void mipsxx_cpu_setup (void *args)
 123 {
 124         unsigned int counters = op_model_mipsxx_ops.num_counters;
 125
 126         switch (counters) {
 127         case 4:
 128                 w_c0_perfctrl3(0);
 129                 w_c0_perfcntr3(reg.counter[3]);
 130         case 3:
 131                 w_c0_perfctrl2(0);
 132                 w_c0_perfcntr2(reg.counter[2]);
 133         case 2:
 134                 w_c0_perfctrl1(0);
 135                 w_c0_perfcntr1(reg.counter[1]);
 136         case 1:
 137                 w_c0_perfctrl0(0);
 138                 w_c0_perfcntr0(reg.counter[0]);
 139         }
 140 }
 141
 142 /* Start all counters on current CPU */
 143 static void mipsxx_cpu_start(void *args)
 144 {
 145         unsigned int counters = op_model_mipsxx_ops.num_counters;
 146
 147         switch (counters) {
 148         case 4:
 149                 w_c0_perfctrl3(WHAT | reg.control[3]);
 150         case 3:
 151                 w_c0_perfctrl2(WHAT | reg.control[2]);
 152         case 2:
 153                 w_c0_perfctrl1(WHAT | reg.control[1]);
 154         case 1:
 155                 w_c0_perfctrl0(WHAT | reg.control[0]);
 156         }
 157 }
 158
 159 /* Stop all counters on current CPU */
 160 static void mipsxx_cpu_stop(void *args)
 161 {
 162         unsigned int counters = op_model_mipsxx_ops.num_counters;
 163
 164         switch (counters) {
 165         case 4:
 166                 w_c0_perfctrl3(0);
 167         case 3:
 168                 w_c0_perfctrl2(0);
 169         case 2:
 170                 w_c0_perfctrl1(0);
 171         case 1:
 172                 w_c0_perfctrl0(0);
 173         }
 174 }
 175
 176 static int mipsxx_perfcount_handler(void)
 177 {
 178         unsigned int counters = op_model_mipsxx_ops.num_counters;
 179         unsigned int control;
 180         unsigned int counter;
 181         int handled = 0;
 182
 183         switch (counters) {
 184 #define HANDLE_COUNTER(n)                                               \
 185         case n + 1:                                                     \
 186                 control = r_c0_perfctrl ## n();                         \
 187                 counter = r_c0_perfcntr ## n();                         \
 188                 if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&           \
 189                     (counter & M_COUNTER_OVERFLOW)) {                   \
 190                         oprofile_add_sample(get_irq_regs(), n);         \
 191                         w_c0_perfcntr ## n(reg.counter[n]);             \
 192                         handled = 1;                                    \
 193                 }
 194         HANDLE_COUNTER(3)
 195         HANDLE_COUNTER(2)
 196         HANDLE_COUNTER(1)
 197         HANDLE_COUNTER(0)
 198         }
 199
 200         return handled;
 201 }
 202
 203 #define M_CONFIG1_PC    (1 << 4)
 204
 205 static inline int __n_counters(void)
 206 {
 207         if (!(read_c0_config1() & M_CONFIG1_PC))
 208                 return 0;
 209         if (!(r_c0_perfctrl0() & M_PERFCTL_MORE))
 210                 return 1;
 211         if (!(r_c0_perfctrl1() & M_PERFCTL_MORE))
 212                 return 2;
 213         if (!(r_c0_perfctrl2() & M_PERFCTL_MORE))
 214                 return 3;
 215
 216         return 4;
 217 }
 218
 219 static inline int n_counters(void)
 220 {
 221         int counters = __n_counters();
 222
 223 #ifdef CONFIG_MIPS_MT_SMP
 224         if (current_cpu_data.cputype == CPU_34K)
 225                 return counters >> 1;
 226 #endif
 227
 228         return counters;
 229 }
 230
 231 static inline void reset_counters(int counters)
 232 {
 233         switch (counters) {
 234         case 4:
 235                 w_c0_perfctrl3(0);
 236                 w_c0_perfcntr3(0);
 237         case 3:
 238                 w_c0_perfctrl2(0);
 239                 w_c0_perfcntr2(0);
 240         case 2:
 241                 w_c0_perfctrl1(0);
 242                 w_c0_perfcntr1(0);
 243         case 1:
 244                 w_c0_perfctrl0(0);
 245                 w_c0_perfcntr0(0);
 246         }
 247 }
 248
 249 static int __init mipsxx_init(void)
 250 {
 251         int counters;
 252
 253         counters = n_counters();
 254         if (counters == 0) {
 255                 printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
 256                 return -ENODEV;
 257         }
 258
 259         reset_counters(counters);
 260
 261         op_model_mipsxx_ops.num_counters = counters;
 262         switch (current_cpu_data.cputype) {
 263         case CPU_20KC:
 264                 op_model_mipsxx_ops.cpu_type = "mips/20K";
 265                 break;
 266
 267         case CPU_24K:
 268                 op_model_mipsxx_ops.cpu_type = "mips/24K";
 269                 break;
 270
 271         case CPU_25KF:
 272                 op_model_mipsxx_ops.cpu_type = "mips/25K";
 273                 break;
 274
 275         case CPU_34K:
 276                 op_model_mipsxx_ops.cpu_type = "mips/34K";
 277                 break;
 278
 279         case CPU_74K:
 280                 op_model_mipsxx_ops.cpu_type = "mips/74K";
 281                 break;
 282
 283         case CPU_5KC:
 284                 op_model_mipsxx_ops.cpu_type = "mips/5K";
 285                 break;
 286
 287         case CPU_SB1:
 288         case CPU_SB1A:
 289                 op_model_mipsxx_ops.cpu_type = "mips/sb1";
 290                 break;
 291
 292         default:
 293                 printk(KERN_ERR "Profiling unsupported for this CPU\n");
 294
 295                 return -ENODEV;
 296         }
 297
 298         perf_irq = mipsxx_perfcount_handler;
 299
 300         return 0;
 301 }
 302
 303 static void mipsxx_exit(void)
 304 {
 305         reset_counters(op_model_mipsxx_ops.num_counters);
 306
 307         perf_irq = null_perf_irq;
 308 }
 309
 310 struct op_mips_model op_model_mipsxx_ops = {
 311         .reg_setup      = mipsxx_reg_setup,
 312         .cpu_setup      = mipsxx_cpu_setup,
 313         .init           = mipsxx_init,
 314         .exit           = mipsxx_exit,
 315         .cpu_start      = mipsxx_cpu_start,
 316         .cpu_stop       = mipsxx_cpu_stop,
 317 };