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35 #include <linux/init.h>
38 #include <asm/asm-offsets.h>
39 #include <asm/cacheops.h>
40 #include <asm/regdef.h>
41 #include <asm/mipsregs.h>
42 #include <asm/stackframe.h>
43 #include <asm/asmmacro.h>
44 #include <asm/addrspace.h>
46 #include <asm/netlogic/common.h>
48 #include <asm/netlogic/xlp-hal/iomap.h>
49 #include <asm/netlogic/xlp-hal/xlp.h>
50 #include <asm/netlogic/xlp-hal/sys.h>
51 #include <asm/netlogic/xlp-hal/cpucontrol.h>
54 #define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
55 XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \
56 SYS_CPU_NONCOHERENT_MODE * 4
58 /* Enable XLP features and workarounds in the LSU */
63 lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */
69 ori t1, 0x1000 /* Enable Icache partitioning */
72 li t0, SCHED_DEFEATURE
73 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
78 * L1D cache has to be flushed before enabling threads in XLP.
79 * On XLP8xx/XLP3xx, we do a low level flush using processor control
80 * registers. On XLPII CPUs, usual cache instructions work.
82 .macro xlp_flush_l1_dcache
89 /* XLP8xx low level cache flush */
90 li t0, LSU_DEBUG_DATA0
93 li t3, 0x1000 /* loop count */
97 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
101 andi v1, 0x1 /* wait for write_active == 0 */
105 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
109 andi v1, 0x1 /* wait for write_active == 0 */
118 /* XLPII CPUs, Invalidate all 64k of L1 D-cache */
122 16: cache Index_Writeback_Inv_D, 0(t0)
130 * nlm_reset_entry will be copied to the reset entry point for
131 * XLR and XLP. The XLP cores start here when they are woken up. This
132 * is also the NMI entry point.
134 * We use scratch reg 6/7 to save k0/k1 and check for NMI first.
136 * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
137 * location, this will have the thread mask (used when core is woken up)
138 * and the current NMI handler in case we reached here for an NMI.
140 * When a core or thread is newly woken up, it marks itself ready and
141 * loops in a 'wait'. When the CPU really needs waking up, we send an NMI
142 * IPI to it, with the NMI handler set to prom_boot_secondary_cpus
146 .set arch=xlr /* for mfcr/mtcr, XLR is sufficient */
148 FEXPORT(nlm_reset_entry)
154 beqz k1, 1f /* go to real reset entry */
156 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
157 ld k0, BOOT_NMI_HANDLER(k1)
161 1: /* Entry point on core wakeup */
162 mfc0 t0, CP0_EBASE, 0 /* processor ID */
164 li t1, 0x1500 /* XLP 9xx */
165 beq t0, t1, 2f /* does not need to set coherent */
168 /* set bit in SYS coherent register for the core */
169 mfc0 t0, CP0_EBASE, 1
170 mfc0 t1, CP0_EBASE, 1
172 andi t1, 0x3 /* t1 <- node */
174 mul t3, t2, t1 /* t3 = node * 0x40000 */
176 and t0, t0, 0x7 /* t0 <- core */
179 nor t0, t0, zero /* t0 <- ~(1 << core) */
180 li t2, SYS_CPU_COHERENT_BASE
181 add t2, t2, t3 /* t2 <- SYS offset for node */
186 /* read back to ensure complete */
191 /* Configure LSU on Non-0 Cores. */
196 * Wake up sibling threads from the initial thread in a core.
198 EXPORT(nlm_boot_siblings)
199 /* core L1D flush before enable threads */
201 /* Enable hw threads by writing to MAP_THREADMODE of the core */
202 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
203 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
204 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
210 * The new hardware thread starts at the next instruction
211 * For all the cases other than core 0 thread 0, we will
212 * jump to the secondary wait function.
214 * NOTE: All GPR contents are lost after the mtcr above!
216 mfc0 v0, CP0_EBASE, 1
217 andi v0, 0x3ff /* v0 <- node/core */
219 beqz v0, 4f /* boot cpu (cpuid == 0)? */
222 /* setup status reg */
230 li t3, CKSEG1ADDR(RESET_DATA_PHYS)
231 ADDIU t1, t3, BOOT_CPU_READY
236 /* Wait until NMI hits */
242 * For the boot CPU, we have to restore registers and
245 4: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
247 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
248 PTR_SUBU sp, t0, PT_SIZE
252 EXPORT(nlm_reset_entry_end)
254 LEAF(nlm_init_boot_cpu)
255 #ifdef CONFIG_CPU_XLP
260 END(nlm_init_boot_cpu)