2 * Copyright (C) 1999, 2000, 2006 MIPS Technologies, Inc.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
7 * ########################################################################
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 * ########################################################################
24 * Routines for generic manipulation of the interrupts found on the MIPS
28 #include <linux/compiler.h>
29 #include <linux/init.h>
30 #include <linux/irq.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/kernel_stat.h>
36 #include <asm/gdb-stub.h>
38 #include <asm/irq_cpu.h>
39 #include <asm/msc01_ic.h>
41 #include <asm/mips-boards/atlas.h>
42 #include <asm/mips-boards/atlasint.h>
43 #include <asm/mips-boards/generic.h>
45 static struct atlas_ictrl_regs *atlas_hw0_icregs;
48 #define DEBUG_INT(x...) printk(x)
50 #define DEBUG_INT(x...)
53 void disable_atlas_irq(unsigned int irq_nr)
55 atlas_hw0_icregs->intrsten = 1 << (irq_nr - ATLAS_INT_BASE);
59 void enable_atlas_irq(unsigned int irq_nr)
61 atlas_hw0_icregs->intseten = 1 << (irq_nr - ATLAS_INT_BASE);
65 static void end_atlas_irq(unsigned int irq)
67 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
68 enable_atlas_irq(irq);
71 static struct irq_chip atlas_irq_type = {
73 .ack = disable_atlas_irq,
74 .mask = disable_atlas_irq,
75 .mask_ack = disable_atlas_irq,
76 .unmask = enable_atlas_irq,
77 .eoi = enable_atlas_irq,
81 static inline int ls1bit32(unsigned int x)
85 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
86 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
87 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
88 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
89 s = 1; if (x << 1 == 0) s = 0; b -= s;
94 static inline void atlas_hw0_irqdispatch(void)
96 unsigned long int_status;
99 int_status = atlas_hw0_icregs->intstatus;
101 /* if int_status == 0, then the interrupt has already been cleared */
102 if (unlikely(int_status == 0))
105 irq = ATLAS_INT_BASE + ls1bit32(int_status);
107 DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
112 static inline int clz(unsigned long x)
126 * Version of ffs that only looks at bits 12..15.
128 static inline unsigned int irq_ffs(unsigned int pending)
130 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
131 return -clz(pending) + 31 - CAUSEB_IP;
159 * IRQs on the Atlas board look basically like (all external interrupt
160 * sources are combined together on hardware interrupt 0 (MIPS IRQ 2)):
164 * 0 Software 0 (reschedule IPI on MT)
165 * 1 Software 1 (remote call IPI on MT)
166 * 2 Combined Atlas hardware interrupt (hw0)
167 * 3 Hardware (ignored)
168 * 4 Hardware (ignored)
169 * 5 Hardware (ignored)
170 * 6 Hardware (ignored)
171 * 7 R4k timer (what we use)
173 * We handle the IRQ according to _our_ priority which is:
175 * Highest ---- R4k Timer
176 * Lowest ---- Software 0
178 * then we just return, if multiple IRQs are pending then we will just take
179 * another exception, big deal.
181 asmlinkage void plat_irq_dispatch(void)
183 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
186 irq = irq_ffs(pending);
188 if (irq == MIPSCPU_INT_ATLAS)
189 atlas_hw0_irqdispatch();
191 do_IRQ(MIPSCPU_INT_BASE + irq);
193 spurious_interrupt();
196 static inline void init_atlas_irqs (int base)
200 atlas_hw0_icregs = (struct atlas_ictrl_regs *)
201 ioremap(ATLAS_ICTRL_REGS_BASE,
202 sizeof(struct atlas_ictrl_regs *));
205 * Mask out all interrupt by writing "1" to all bit position in
206 * the interrupt reset reg.
208 atlas_hw0_icregs->intrsten = 0xffffffff;
210 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
211 set_irq_chip_and_handler(i, &atlas_irq_type, handle_level_irq);
214 static struct irqaction atlasirq = {
215 .handler = no_action,
216 .name = "Atlas cascade"
219 msc_irqmap_t __initdata msc_irqmap[] = {
220 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
221 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
223 int __initdata msc_nr_irqs = sizeof(msc_irqmap) / sizeof(*msc_irqmap);
225 msc_irqmap_t __initdata msc_eicirqmap[] = {
226 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
227 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
228 {MSC01E_INT_ATLAS, MSC01_IRQ_LEVEL, 0},
229 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
230 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
231 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
232 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
234 int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap) / sizeof(*msc_eicirqmap);
236 void __init arch_init_irq(void)
238 init_atlas_irqs(ATLAS_INT_BASE);
241 mips_cpu_irq_init(MIPSCPU_INT_BASE);
243 switch(mips_revision_corid) {
244 case MIPS_REVISION_CORID_CORE_MSC:
245 case MIPS_REVISION_CORID_CORE_FPGA2:
246 case MIPS_REVISION_CORID_CORE_FPGA3:
247 case MIPS_REVISION_CORID_CORE_24K:
248 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
250 init_msc_irqs (MSC01E_INT_BASE,
251 msc_eicirqmap, msc_nr_eicirqs);
253 init_msc_irqs (MSC01C_INT_BASE,
254 msc_irqmap, msc_nr_irqs);
259 set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
260 setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
261 } else if (cpu_has_vint) {
262 set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
263 #ifdef CONFIG_MIPS_MT_SMTC
264 setup_irq_smtc (MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS,
265 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
267 setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
268 #endif /* CONFIG_MIPS_MT_SMTC */
270 setup_irq(MIPSCPU_INT_BASE + MIPSCPU_INT_ATLAS, &atlasirq);