1 #include <asm/branch.h>
2 #include <asm/cacheflush.h>
3 #include <asm/fpu_emulator.h>
5 #include <asm/mipsregs.h>
6 #include <asm/uaccess.h>
11 * Emulate the arbritrary instruction ir at xcp->cp0_epc. Required when
12 * we have to emulate the instruction in a COP1 branch delay slot. Do
13 * not change cp0_epc due to the instruction
15 * According to the spec:
16 * 1) it shouldn't be a branch :-)
17 * 2) it can be a COP instruction :-(
18 * 3) if we are tring to run a protected memory space we must take
19 * special care on memory access instructions :-(
23 * "Trampoline" return routine to catch exception following
24 * execution of delay-slot instruction execution.
28 mips_instruction emul;
29 mips_instruction badinst;
30 mips_instruction cookie;
35 * Set up an emulation frame for instruction IR, from a delay slot of
36 * a branch jumping to CPC. Return 0 if successful, -1 if no emulation
37 * required, otherwise a signal number causing a frame setup failure.
39 int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
41 mips_instruction break_math;
42 struct emuframe __user *fr;
46 if ((get_isa16_mode(regs->cp0_epc) && ((ir >> 16) == MM_NOP16)) ||
50 pr_debug("dsemul %lx %lx\n", regs->cp0_epc, cpc);
53 * The strategy is to push the instruction onto the user stack
54 * and put a trap after it which we can catch and jump to
55 * the required address any alternative apart from full
56 * instruction emulation!!.
58 * Algorithmics used a system call instruction, and
59 * borrowed that vector. MIPS/Linux version is a bit
60 * more heavyweight in the interests of portability and
61 * multiprocessor support. For Linux we generate a
62 * an unaligned access and force an address error exception.
64 * For embedded systems (stand-alone) we prefer to use a
65 * non-existing CP1 instruction. This prevents us from emulating
66 * branches, but gives us a cleaner interface to the exception
67 * handler (single entry point).
69 break_math = BREAK_MATH(get_isa16_mode(regs->cp0_epc));
71 /* Ensure that the two instructions are in the same cache line */
72 fr = (struct emuframe __user *)
73 ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
75 /* Verify that the stack pointer is not competely insane */
76 if (unlikely(!access_ok(VERIFY_WRITE, fr, sizeof(struct emuframe))))
79 if (get_isa16_mode(regs->cp0_epc)) {
80 err = __put_user(ir >> 16,
81 (u16 __user *)(&fr->emul));
82 err |= __put_user(ir & 0xffff,
83 (u16 __user *)((long)(&fr->emul) + 2));
84 err |= __put_user(break_math >> 16,
85 (u16 __user *)(&fr->badinst));
86 err |= __put_user(break_math & 0xffff,
87 (u16 __user *)((long)(&fr->badinst) + 2));
89 err = __put_user(ir, &fr->emul);
90 err |= __put_user(break_math, &fr->badinst);
93 err |= __put_user((mips_instruction)BD_COOKIE, &fr->cookie);
94 err |= __put_user(cpc, &fr->epc);
97 MIPS_FPU_EMU_INC_STATS(errors);
101 regs->cp0_epc = ((unsigned long) &fr->emul) |
102 get_isa16_mode(regs->cp0_epc);
104 flush_cache_sigtramp((unsigned long)&fr->emul);
109 int do_dsemulret(struct pt_regs *xcp)
111 struct emuframe __user *fr;
117 fr = (struct emuframe __user *)
118 (msk_isa16_mode(xcp->cp0_epc) - sizeof(mips_instruction));
121 * If we can't even access the area, something is very wrong, but we'll
122 * leave that to the default handling
124 if (!access_ok(VERIFY_READ, fr, sizeof(struct emuframe)))
128 * Do some sanity checking on the stackframe:
130 * - Is the instruction pointed to by the EPC an BREAK_MATH?
131 * - Is the following memory word the BD_COOKIE?
133 if (get_isa16_mode(xcp->cp0_epc)) {
134 err = __get_user(instr[0],
135 (u16 __user *)(&fr->badinst));
136 err |= __get_user(instr[1],
137 (u16 __user *)((long)(&fr->badinst) + 2));
138 insn = (instr[0] << 16) | instr[1];
140 err = __get_user(insn, &fr->badinst);
142 err |= __get_user(cookie, &fr->cookie);
144 if (unlikely(err || insn != BREAK_MATH(get_isa16_mode(xcp->cp0_epc)) ||
145 cookie != BD_COOKIE)) {
146 MIPS_FPU_EMU_INC_STATS(errors);
151 * At this point, we are satisfied that it's a BD emulation trap. Yes,
152 * a user might have deliberately put two malformed and useless
153 * instructions in a row in his program, in which case he's in for a
154 * nasty surprise - the next instruction will be treated as a
155 * continuation address! Alas, this seems to be the only way that we
156 * can handle signals, recursion, and longjmps() in the context of
157 * emulating the branch delay instruction.
160 pr_debug("dsemulret\n");
162 if (__get_user(epc, &fr->epc)) { /* Saved EPC */
163 /* This is not a good situation to be in */
164 force_sig(SIGBUS, current);
169 /* Set EPC to return to post-branch instruction */
171 MIPS_FPU_EMU_INC_STATS(ds_emul);