MIPS: math-emu: Add support for the CMP.condn.fmt R6 instruction
[linux-drm-fsl-dcu.git] / arch / mips / math-emu / cp1emu.c
1 /*
2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3  *
4  * MIPS floating point support
5  * Copyright (C) 1994-2000 Algorithmics Ltd.
6  *
7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8  * Copyright (C) 2000  MIPS Technologies, Inc.
9  *
10  *  This program is free software; you can distribute it and/or modify it
11  *  under the terms of the GNU General Public License (Version 2) as
12  *  published by the Free Software Foundation.
13  *
14  *  This program is distributed in the hope it will be useful, but WITHOUT
15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
17  *  for more details.
18  *
19  *  You should have received a copy of the GNU General Public License along
20  *  with this program; if not, write to the Free Software Foundation, Inc.,
21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
22  *
23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
24  * required for #float(switch) or #float(trap), where it catches all
25  * COP1 instructions via the "CoProcessor Unusable" exception.
26  *
27  * More surprisingly it is also required for #float(ieee), to help out
28  * the hardware FPU at the boundaries of the IEEE-754 representation
29  * (denormalised values, infinities, underflow, etc).  It is made
30  * quite nasty because emulation of some non-COP1 instructions is
31  * required, e.g. in branch delay slots.
32  *
33  * Note if you know that you won't have an FPU, then you'll get much
34  * better performance by compiling with -msoft-float!
35  */
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
41
42 #include <asm/branch.h>
43 #include <asm/inst.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
47
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
51 #include <asm/fpu.h>
52 #include <asm/mips-r2-to-r6-emul.h>
53
54 #include "ieee754.h"
55
56 /* Function which emulates a floating point instruction. */
57
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
59         mips_instruction);
60
61 static int fpux_emu(struct pt_regs *,
62         struct mips_fpu_struct *, mips_instruction, void *__user *);
63
64 /* Control registers */
65
66 #define FPCREG_RID      0       /* $0  = revision id */
67 #define FPCREG_FCCR     25      /* $25 = fccr */
68 #define FPCREG_FEXR     26      /* $26 = fexr */
69 #define FPCREG_FENR     28      /* $28 = fenr */
70 #define FPCREG_CSR      31      /* $31 = csr */
71
72 /* convert condition code register number to csr bit */
73 const unsigned int fpucondbit[8] = {
74         FPU_CSR_COND,
75         FPU_CSR_COND1,
76         FPU_CSR_COND2,
77         FPU_CSR_COND3,
78         FPU_CSR_COND4,
79         FPU_CSR_COND5,
80         FPU_CSR_COND6,
81         FPU_CSR_COND7
82 };
83
84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
89
90 /*
91  * This functions translates a 32-bit microMIPS instruction
92  * into a 32-bit MIPS32 instruction. Returns 0 on success
93  * and SIGILL otherwise.
94  */
95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
96 {
97         union mips_instruction insn = *insn_ptr;
98         union mips_instruction mips32_insn = insn;
99         int func, fmt, op;
100
101         switch (insn.mm_i_format.opcode) {
102         case mm_ldc132_op:
103                 mips32_insn.mm_i_format.opcode = ldc1_op;
104                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
105                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
106                 break;
107         case mm_lwc132_op:
108                 mips32_insn.mm_i_format.opcode = lwc1_op;
109                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
110                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
111                 break;
112         case mm_sdc132_op:
113                 mips32_insn.mm_i_format.opcode = sdc1_op;
114                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
115                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
116                 break;
117         case mm_swc132_op:
118                 mips32_insn.mm_i_format.opcode = swc1_op;
119                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
120                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
121                 break;
122         case mm_pool32i_op:
123                 /* NOTE: offset is << by 1 if in microMIPS mode. */
124                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
125                     (insn.mm_i_format.rt == mm_bc1t_op)) {
126                         mips32_insn.fb_format.opcode = cop1_op;
127                         mips32_insn.fb_format.bc = bc_op;
128                         mips32_insn.fb_format.flag =
129                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
130                 } else
131                         return SIGILL;
132                 break;
133         case mm_pool32f_op:
134                 switch (insn.mm_fp0_format.func) {
135                 case mm_32f_01_op:
136                 case mm_32f_11_op:
137                 case mm_32f_02_op:
138                 case mm_32f_12_op:
139                 case mm_32f_41_op:
140                 case mm_32f_51_op:
141                 case mm_32f_42_op:
142                 case mm_32f_52_op:
143                         op = insn.mm_fp0_format.func;
144                         if (op == mm_32f_01_op)
145                                 func = madd_s_op;
146                         else if (op == mm_32f_11_op)
147                                 func = madd_d_op;
148                         else if (op == mm_32f_02_op)
149                                 func = nmadd_s_op;
150                         else if (op == mm_32f_12_op)
151                                 func = nmadd_d_op;
152                         else if (op == mm_32f_41_op)
153                                 func = msub_s_op;
154                         else if (op == mm_32f_51_op)
155                                 func = msub_d_op;
156                         else if (op == mm_32f_42_op)
157                                 func = nmsub_s_op;
158                         else
159                                 func = nmsub_d_op;
160                         mips32_insn.fp6_format.opcode = cop1x_op;
161                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
162                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
163                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
164                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
165                         mips32_insn.fp6_format.func = func;
166                         break;
167                 case mm_32f_10_op:
168                         func = -1;      /* Invalid */
169                         op = insn.mm_fp5_format.op & 0x7;
170                         if (op == mm_ldxc1_op)
171                                 func = ldxc1_op;
172                         else if (op == mm_sdxc1_op)
173                                 func = sdxc1_op;
174                         else if (op == mm_lwxc1_op)
175                                 func = lwxc1_op;
176                         else if (op == mm_swxc1_op)
177                                 func = swxc1_op;
178
179                         if (func != -1) {
180                                 mips32_insn.r_format.opcode = cop1x_op;
181                                 mips32_insn.r_format.rs =
182                                         insn.mm_fp5_format.base;
183                                 mips32_insn.r_format.rt =
184                                         insn.mm_fp5_format.index;
185                                 mips32_insn.r_format.rd = 0;
186                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
187                                 mips32_insn.r_format.func = func;
188                         } else
189                                 return SIGILL;
190                         break;
191                 case mm_32f_40_op:
192                         op = -1;        /* Invalid */
193                         if (insn.mm_fp2_format.op == mm_fmovt_op)
194                                 op = 1;
195                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
196                                 op = 0;
197                         if (op != -1) {
198                                 mips32_insn.fp0_format.opcode = cop1_op;
199                                 mips32_insn.fp0_format.fmt =
200                                         sdps_format[insn.mm_fp2_format.fmt];
201                                 mips32_insn.fp0_format.ft =
202                                         (insn.mm_fp2_format.cc<<2) + op;
203                                 mips32_insn.fp0_format.fs =
204                                         insn.mm_fp2_format.fs;
205                                 mips32_insn.fp0_format.fd =
206                                         insn.mm_fp2_format.fd;
207                                 mips32_insn.fp0_format.func = fmovc_op;
208                         } else
209                                 return SIGILL;
210                         break;
211                 case mm_32f_60_op:
212                         func = -1;      /* Invalid */
213                         if (insn.mm_fp0_format.op == mm_fadd_op)
214                                 func = fadd_op;
215                         else if (insn.mm_fp0_format.op == mm_fsub_op)
216                                 func = fsub_op;
217                         else if (insn.mm_fp0_format.op == mm_fmul_op)
218                                 func = fmul_op;
219                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
220                                 func = fdiv_op;
221                         if (func != -1) {
222                                 mips32_insn.fp0_format.opcode = cop1_op;
223                                 mips32_insn.fp0_format.fmt =
224                                         sdps_format[insn.mm_fp0_format.fmt];
225                                 mips32_insn.fp0_format.ft =
226                                         insn.mm_fp0_format.ft;
227                                 mips32_insn.fp0_format.fs =
228                                         insn.mm_fp0_format.fs;
229                                 mips32_insn.fp0_format.fd =
230                                         insn.mm_fp0_format.fd;
231                                 mips32_insn.fp0_format.func = func;
232                         } else
233                                 return SIGILL;
234                         break;
235                 case mm_32f_70_op:
236                         func = -1;      /* Invalid */
237                         if (insn.mm_fp0_format.op == mm_fmovn_op)
238                                 func = fmovn_op;
239                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
240                                 func = fmovz_op;
241                         if (func != -1) {
242                                 mips32_insn.fp0_format.opcode = cop1_op;
243                                 mips32_insn.fp0_format.fmt =
244                                         sdps_format[insn.mm_fp0_format.fmt];
245                                 mips32_insn.fp0_format.ft =
246                                         insn.mm_fp0_format.ft;
247                                 mips32_insn.fp0_format.fs =
248                                         insn.mm_fp0_format.fs;
249                                 mips32_insn.fp0_format.fd =
250                                         insn.mm_fp0_format.fd;
251                                 mips32_insn.fp0_format.func = func;
252                         } else
253                                 return SIGILL;
254                         break;
255                 case mm_32f_73_op:    /* POOL32FXF */
256                         switch (insn.mm_fp1_format.op) {
257                         case mm_movf0_op:
258                         case mm_movf1_op:
259                         case mm_movt0_op:
260                         case mm_movt1_op:
261                                 if ((insn.mm_fp1_format.op & 0x7f) ==
262                                     mm_movf0_op)
263                                         op = 0;
264                                 else
265                                         op = 1;
266                                 mips32_insn.r_format.opcode = spec_op;
267                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
268                                 mips32_insn.r_format.rt =
269                                         (insn.mm_fp4_format.cc << 2) + op;
270                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
271                                 mips32_insn.r_format.re = 0;
272                                 mips32_insn.r_format.func = movc_op;
273                                 break;
274                         case mm_fcvtd0_op:
275                         case mm_fcvtd1_op:
276                         case mm_fcvts0_op:
277                         case mm_fcvts1_op:
278                                 if ((insn.mm_fp1_format.op & 0x7f) ==
279                                     mm_fcvtd0_op) {
280                                         func = fcvtd_op;
281                                         fmt = swl_format[insn.mm_fp3_format.fmt];
282                                 } else {
283                                         func = fcvts_op;
284                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
285                                 }
286                                 mips32_insn.fp0_format.opcode = cop1_op;
287                                 mips32_insn.fp0_format.fmt = fmt;
288                                 mips32_insn.fp0_format.ft = 0;
289                                 mips32_insn.fp0_format.fs =
290                                         insn.mm_fp3_format.fs;
291                                 mips32_insn.fp0_format.fd =
292                                         insn.mm_fp3_format.rt;
293                                 mips32_insn.fp0_format.func = func;
294                                 break;
295                         case mm_fmov0_op:
296                         case mm_fmov1_op:
297                         case mm_fabs0_op:
298                         case mm_fabs1_op:
299                         case mm_fneg0_op:
300                         case mm_fneg1_op:
301                                 if ((insn.mm_fp1_format.op & 0x7f) ==
302                                     mm_fmov0_op)
303                                         func = fmov_op;
304                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
305                                          mm_fabs0_op)
306                                         func = fabs_op;
307                                 else
308                                         func = fneg_op;
309                                 mips32_insn.fp0_format.opcode = cop1_op;
310                                 mips32_insn.fp0_format.fmt =
311                                         sdps_format[insn.mm_fp3_format.fmt];
312                                 mips32_insn.fp0_format.ft = 0;
313                                 mips32_insn.fp0_format.fs =
314                                         insn.mm_fp3_format.fs;
315                                 mips32_insn.fp0_format.fd =
316                                         insn.mm_fp3_format.rt;
317                                 mips32_insn.fp0_format.func = func;
318                                 break;
319                         case mm_ffloorl_op:
320                         case mm_ffloorw_op:
321                         case mm_fceill_op:
322                         case mm_fceilw_op:
323                         case mm_ftruncl_op:
324                         case mm_ftruncw_op:
325                         case mm_froundl_op:
326                         case mm_froundw_op:
327                         case mm_fcvtl_op:
328                         case mm_fcvtw_op:
329                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
330                                         func = ffloorl_op;
331                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
332                                         func = ffloor_op;
333                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
334                                         func = fceill_op;
335                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
336                                         func = fceil_op;
337                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
338                                         func = ftruncl_op;
339                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
340                                         func = ftrunc_op;
341                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
342                                         func = froundl_op;
343                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
344                                         func = fround_op;
345                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346                                         func = fcvtl_op;
347                                 else
348                                         func = fcvtw_op;
349                                 mips32_insn.fp0_format.opcode = cop1_op;
350                                 mips32_insn.fp0_format.fmt =
351                                         sd_format[insn.mm_fp1_format.fmt];
352                                 mips32_insn.fp0_format.ft = 0;
353                                 mips32_insn.fp0_format.fs =
354                                         insn.mm_fp1_format.fs;
355                                 mips32_insn.fp0_format.fd =
356                                         insn.mm_fp1_format.rt;
357                                 mips32_insn.fp0_format.func = func;
358                                 break;
359                         case mm_frsqrt_op:
360                         case mm_fsqrt_op:
361                         case mm_frecip_op:
362                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
363                                         func = frsqrt_op;
364                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365                                         func = fsqrt_op;
366                                 else
367                                         func = frecip_op;
368                                 mips32_insn.fp0_format.opcode = cop1_op;
369                                 mips32_insn.fp0_format.fmt =
370                                         sdps_format[insn.mm_fp1_format.fmt];
371                                 mips32_insn.fp0_format.ft = 0;
372                                 mips32_insn.fp0_format.fs =
373                                         insn.mm_fp1_format.fs;
374                                 mips32_insn.fp0_format.fd =
375                                         insn.mm_fp1_format.rt;
376                                 mips32_insn.fp0_format.func = func;
377                                 break;
378                         case mm_mfc1_op:
379                         case mm_mtc1_op:
380                         case mm_cfc1_op:
381                         case mm_ctc1_op:
382                         case mm_mfhc1_op:
383                         case mm_mthc1_op:
384                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
385                                         op = mfc_op;
386                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
387                                         op = mtc_op;
388                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
389                                         op = cfc_op;
390                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
391                                         op = ctc_op;
392                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393                                         op = mfhc_op;
394                                 else
395                                         op = mthc_op;
396                                 mips32_insn.fp1_format.opcode = cop1_op;
397                                 mips32_insn.fp1_format.op = op;
398                                 mips32_insn.fp1_format.rt =
399                                         insn.mm_fp1_format.rt;
400                                 mips32_insn.fp1_format.fs =
401                                         insn.mm_fp1_format.fs;
402                                 mips32_insn.fp1_format.fd = 0;
403                                 mips32_insn.fp1_format.func = 0;
404                                 break;
405                         default:
406                                 return SIGILL;
407                         }
408                         break;
409                 case mm_32f_74_op:      /* c.cond.fmt */
410                         mips32_insn.fp0_format.opcode = cop1_op;
411                         mips32_insn.fp0_format.fmt =
412                                 sdps_format[insn.mm_fp4_format.fmt];
413                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
414                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
415                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
416                         mips32_insn.fp0_format.func =
417                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
418                         break;
419                 default:
420                         return SIGILL;
421                 }
422                 break;
423         default:
424                 return SIGILL;
425         }
426
427         *insn_ptr = mips32_insn;
428         return 0;
429 }
430
431 /*
432  * Redundant with logic already in kernel/branch.c,
433  * embedded in compute_return_epc.  At some point,
434  * a single subroutine should be used across both
435  * modules.
436  */
437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
438                          unsigned long *contpc)
439 {
440         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
441         unsigned int fcr31;
442         unsigned int bit = 0;
443
444         switch (insn.i_format.opcode) {
445         case spec_op:
446                 switch (insn.r_format.func) {
447                 case jalr_op:
448                         regs->regs[insn.r_format.rd] =
449                                 regs->cp0_epc + dec_insn.pc_inc +
450                                 dec_insn.next_pc_inc;
451                         /* Fall through */
452                 case jr_op:
453                         /* For R6, JR already emulated in jalr_op */
454                         if (NO_R6EMU && insn.r_format.func == jr_op)
455                                 break;
456                         *contpc = regs->regs[insn.r_format.rs];
457                         return 1;
458                 }
459                 break;
460         case bcond_op:
461                 switch (insn.i_format.rt) {
462                 case bltzal_op:
463                 case bltzall_op:
464                         if (NO_R6EMU && (insn.i_format.rs ||
465                             insn.i_format.rt == bltzall_op))
466                                 break;
467
468                         regs->regs[31] = regs->cp0_epc +
469                                 dec_insn.pc_inc +
470                                 dec_insn.next_pc_inc;
471                         /* Fall through */
472                 case bltzl_op:
473                         if (NO_R6EMU)
474                                 break;
475                 case bltz_op:
476                         if ((long)regs->regs[insn.i_format.rs] < 0)
477                                 *contpc = regs->cp0_epc +
478                                         dec_insn.pc_inc +
479                                         (insn.i_format.simmediate << 2);
480                         else
481                                 *contpc = regs->cp0_epc +
482                                         dec_insn.pc_inc +
483                                         dec_insn.next_pc_inc;
484                         return 1;
485                 case bgezal_op:
486                 case bgezall_op:
487                         if (NO_R6EMU && (insn.i_format.rs ||
488                             insn.i_format.rt == bgezall_op))
489                                 break;
490
491                         regs->regs[31] = regs->cp0_epc +
492                                 dec_insn.pc_inc +
493                                 dec_insn.next_pc_inc;
494                         /* Fall through */
495                 case bgezl_op:
496                         if (NO_R6EMU)
497                                 break;
498                 case bgez_op:
499                         if ((long)regs->regs[insn.i_format.rs] >= 0)
500                                 *contpc = regs->cp0_epc +
501                                         dec_insn.pc_inc +
502                                         (insn.i_format.simmediate << 2);
503                         else
504                                 *contpc = regs->cp0_epc +
505                                         dec_insn.pc_inc +
506                                         dec_insn.next_pc_inc;
507                         return 1;
508                 }
509                 break;
510         case jalx_op:
511                 set_isa16_mode(bit);
512         case jal_op:
513                 regs->regs[31] = regs->cp0_epc +
514                         dec_insn.pc_inc +
515                         dec_insn.next_pc_inc;
516                 /* Fall through */
517         case j_op:
518                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
519                 *contpc >>= 28;
520                 *contpc <<= 28;
521                 *contpc |= (insn.j_format.target << 2);
522                 /* Set microMIPS mode bit: XOR for jalx. */
523                 *contpc ^= bit;
524                 return 1;
525         case beql_op:
526                 if (NO_R6EMU)
527                         break;
528         case beq_op:
529                 if (regs->regs[insn.i_format.rs] ==
530                     regs->regs[insn.i_format.rt])
531                         *contpc = regs->cp0_epc +
532                                 dec_insn.pc_inc +
533                                 (insn.i_format.simmediate << 2);
534                 else
535                         *contpc = regs->cp0_epc +
536                                 dec_insn.pc_inc +
537                                 dec_insn.next_pc_inc;
538                 return 1;
539         case bnel_op:
540                 if (NO_R6EMU)
541                         break;
542         case bne_op:
543                 if (regs->regs[insn.i_format.rs] !=
544                     regs->regs[insn.i_format.rt])
545                         *contpc = regs->cp0_epc +
546                                 dec_insn.pc_inc +
547                                 (insn.i_format.simmediate << 2);
548                 else
549                         *contpc = regs->cp0_epc +
550                                 dec_insn.pc_inc +
551                                 dec_insn.next_pc_inc;
552                 return 1;
553         case blezl_op:
554                 if (!insn.i_format.rt && NO_R6EMU)
555                         break;
556         case blez_op:
557
558                 /*
559                  * Compact branches for R6 for the
560                  * blez and blezl opcodes.
561                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
562                  * BLEZ  | rs = rt != 0      == BGEZALC
563                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
564                  * BLEZL | rs = 0 | rt != 0  == BLEZC
565                  * BLEZL | rs = rt != 0      == BGEZC
566                  * BLEZL | rs != 0 | rt != 0 == BGEC
567                  *
568                  * For real BLEZ{,L}, rt is always 0.
569                  */
570                 if (cpu_has_mips_r6 && insn.i_format.rt) {
571                         if ((insn.i_format.opcode == blez_op) &&
572                             ((!insn.i_format.rs && insn.i_format.rt) ||
573                              (insn.i_format.rs == insn.i_format.rt)))
574                                 regs->regs[31] = regs->cp0_epc +
575                                         dec_insn.pc_inc;
576                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
577                                 dec_insn.next_pc_inc;
578
579                         return 1;
580                 }
581                 if ((long)regs->regs[insn.i_format.rs] <= 0)
582                         *contpc = regs->cp0_epc +
583                                 dec_insn.pc_inc +
584                                 (insn.i_format.simmediate << 2);
585                 else
586                         *contpc = regs->cp0_epc +
587                                 dec_insn.pc_inc +
588                                 dec_insn.next_pc_inc;
589                 return 1;
590         case bgtzl_op:
591                 if (!insn.i_format.rt && NO_R6EMU)
592                         break;
593         case bgtz_op:
594                 /*
595                  * Compact branches for R6 for the
596                  * bgtz and bgtzl opcodes.
597                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
598                  * BGTZ  | rs = rt != 0      == BLTZALC
599                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
600                  * BGTZL | rs = 0 | rt != 0  == BGTZC
601                  * BGTZL | rs = rt != 0      == BLTZC
602                  * BGTZL | rs != 0 | rt != 0 == BLTC
603                  *
604                  * *ZALC varint for BGTZ &&& rt != 0
605                  * For real GTZ{,L}, rt is always 0.
606                  */
607                 if (cpu_has_mips_r6 && insn.i_format.rt) {
608                         if ((insn.i_format.opcode == blez_op) &&
609                             ((!insn.i_format.rs && insn.i_format.rt) ||
610                              (insn.i_format.rs == insn.i_format.rt)))
611                                 regs->regs[31] = regs->cp0_epc +
612                                         dec_insn.pc_inc;
613                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
614                                 dec_insn.next_pc_inc;
615
616                         return 1;
617                 }
618
619                 if ((long)regs->regs[insn.i_format.rs] > 0)
620                         *contpc = regs->cp0_epc +
621                                 dec_insn.pc_inc +
622                                 (insn.i_format.simmediate << 2);
623                 else
624                         *contpc = regs->cp0_epc +
625                                 dec_insn.pc_inc +
626                                 dec_insn.next_pc_inc;
627                 return 1;
628         case cbcond0_op:
629         case cbcond1_op:
630                 if (!cpu_has_mips_r6)
631                         break;
632                 if (insn.i_format.rt && !insn.i_format.rs)
633                         regs->regs[31] = regs->cp0_epc + 4;
634                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
635                         dec_insn.next_pc_inc;
636
637                 return 1;
638 #ifdef CONFIG_CPU_CAVIUM_OCTEON
639         case lwc2_op: /* This is bbit0 on Octeon */
640                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
641                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
642                 else
643                         *contpc = regs->cp0_epc + 8;
644                 return 1;
645         case ldc2_op: /* This is bbit032 on Octeon */
646                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
647                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
648                 else
649                         *contpc = regs->cp0_epc + 8;
650                 return 1;
651         case swc2_op: /* This is bbit1 on Octeon */
652                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
653                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
654                 else
655                         *contpc = regs->cp0_epc + 8;
656                 return 1;
657         case sdc2_op: /* This is bbit132 on Octeon */
658                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
659                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
660                 else
661                         *contpc = regs->cp0_epc + 8;
662                 return 1;
663 #else
664         case bc6_op:
665                 /*
666                  * Only valid for MIPS R6 but we can still end up
667                  * here from a broken userland so just tell emulator
668                  * this is not a branch and let it break later on.
669                  */
670                 if  (!cpu_has_mips_r6)
671                         break;
672                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
673                         dec_insn.next_pc_inc;
674
675                 return 1;
676         case balc6_op:
677                 if (!cpu_has_mips_r6)
678                         break;
679                 regs->regs[31] = regs->cp0_epc + 4;
680                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
681                         dec_insn.next_pc_inc;
682
683                 return 1;
684         case beqzcjic_op:
685                 if (!cpu_has_mips_r6)
686                         break;
687                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
688                         dec_insn.next_pc_inc;
689
690                 return 1;
691         case bnezcjialc_op:
692                 if (!cpu_has_mips_r6)
693                         break;
694                 if (!insn.i_format.rs)
695                         regs->regs[31] = regs->cp0_epc + 4;
696                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
697                         dec_insn.next_pc_inc;
698
699                 return 1;
700 #endif
701         case cop0_op:
702         case cop1_op:
703                 /* Need to check for R6 bc1nez and bc1eqz branches */
704                 if (cpu_has_mips_r6 &&
705                     ((insn.i_format.rs == bc1eqz_op) ||
706                      (insn.i_format.rs == bc1nez_op))) {
707                         bit = 0;
708                         switch (insn.i_format.rs) {
709                         case bc1eqz_op:
710                                 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
711                                     bit = 1;
712                                 break;
713                         case bc1nez_op:
714                                 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
715                                     bit = 1;
716                                 break;
717                         }
718                         if (bit)
719                                 *contpc = regs->cp0_epc +
720                                         dec_insn.pc_inc +
721                                         (insn.i_format.simmediate << 2);
722                         else
723                                 *contpc = regs->cp0_epc +
724                                         dec_insn.pc_inc +
725                                         dec_insn.next_pc_inc;
726
727                         return 1;
728                 }
729                 /* R2/R6 compatible cop1 instruction. Fall through */
730         case cop2_op:
731         case cop1x_op:
732                 if (insn.i_format.rs == bc_op) {
733                         preempt_disable();
734                         if (is_fpu_owner())
735                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
736                         else
737                                 fcr31 = current->thread.fpu.fcr31;
738                         preempt_enable();
739
740                         bit = (insn.i_format.rt >> 2);
741                         bit += (bit != 0);
742                         bit += 23;
743                         switch (insn.i_format.rt & 3) {
744                         case 0: /* bc1f */
745                         case 2: /* bc1fl */
746                                 if (~fcr31 & (1 << bit))
747                                         *contpc = regs->cp0_epc +
748                                                 dec_insn.pc_inc +
749                                                 (insn.i_format.simmediate << 2);
750                                 else
751                                         *contpc = regs->cp0_epc +
752                                                 dec_insn.pc_inc +
753                                                 dec_insn.next_pc_inc;
754                                 return 1;
755                         case 1: /* bc1t */
756                         case 3: /* bc1tl */
757                                 if (fcr31 & (1 << bit))
758                                         *contpc = regs->cp0_epc +
759                                                 dec_insn.pc_inc +
760                                                 (insn.i_format.simmediate << 2);
761                                 else
762                                         *contpc = regs->cp0_epc +
763                                                 dec_insn.pc_inc +
764                                                 dec_insn.next_pc_inc;
765                                 return 1;
766                         }
767                 }
768                 break;
769         }
770         return 0;
771 }
772
773 /*
774  * In the Linux kernel, we support selection of FPR format on the
775  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
776  * is hardwired to zero, which would imply a 32-bit FPU even for
777  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
778  * FPU emu is slow and bulky and optimizing this function offers fairly
779  * sizeable benefits so we try to be clever and make this function return
780  * a constant whenever possible, that is on 64-bit kernels without O32
781  * compatibility enabled and on 32-bit without 64-bit FPU support.
782  */
783 static inline int cop1_64bit(struct pt_regs *xcp)
784 {
785         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
786                 return 1;
787         else if (config_enabled(CONFIG_32BIT) &&
788                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
789                 return 0;
790
791         return !test_thread_flag(TIF_32BIT_FPREGS);
792 }
793
794 static inline bool hybrid_fprs(void)
795 {
796         return test_thread_flag(TIF_HYBRID_FPREGS);
797 }
798
799 #define SIFROMREG(si, x)                                                \
800 do {                                                                    \
801         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
802                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
803         else                                                            \
804                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
805 } while (0)
806
807 #define SITOREG(si, x)                                                  \
808 do {                                                                    \
809         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
810                 unsigned i;                                             \
811                 set_fpr32(&ctx->fpr[x], 0, si);                         \
812                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
813                         set_fpr32(&ctx->fpr[x], i, 0);                  \
814         } else {                                                        \
815                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
816         }                                                               \
817 } while (0)
818
819 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
820
821 #define SITOHREG(si, x)                                                 \
822 do {                                                                    \
823         unsigned i;                                                     \
824         set_fpr32(&ctx->fpr[x], 1, si);                                 \
825         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
826                 set_fpr32(&ctx->fpr[x], i, 0);                          \
827 } while (0)
828
829 #define DIFROMREG(di, x)                                                \
830         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
831
832 #define DITOREG(di, x)                                                  \
833 do {                                                                    \
834         unsigned fpr, i;                                                \
835         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
836         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
837         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
838                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
839 } while (0)
840
841 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
842 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
843 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
844 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
845
846 /*
847  * Emulate a CFC1 instruction.
848  */
849 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
850                             mips_instruction ir)
851 {
852         u32 fcr31 = ctx->fcr31;
853         u32 value = 0;
854
855         switch (MIPSInst_RD(ir)) {
856         case FPCREG_CSR:
857                 value = fcr31;
858                 pr_debug("%p gpr[%d]<-csr=%08x\n",
859                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
860                 break;
861
862         case FPCREG_FENR:
863                 if (!cpu_has_mips_r)
864                         break;
865                 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
866                         MIPS_FENR_FS;
867                 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
868                 pr_debug("%p gpr[%d]<-enr=%08x\n",
869                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
870                 break;
871
872         case FPCREG_FEXR:
873                 if (!cpu_has_mips_r)
874                         break;
875                 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
876                 pr_debug("%p gpr[%d]<-exr=%08x\n",
877                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
878                 break;
879
880         case FPCREG_FCCR:
881                 if (!cpu_has_mips_r)
882                         break;
883                 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
884                         MIPS_FCCR_COND0;
885                 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
886                          (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
887                 pr_debug("%p gpr[%d]<-ccr=%08x\n",
888                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
889                 break;
890
891         case FPCREG_RID:
892                 value = boot_cpu_data.fpu_id;
893                 break;
894
895         default:
896                 break;
897         }
898
899         if (MIPSInst_RT(ir))
900                 xcp->regs[MIPSInst_RT(ir)] = value;
901 }
902
903 /*
904  * Emulate a CTC1 instruction.
905  */
906 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
907                             mips_instruction ir)
908 {
909         u32 fcr31 = ctx->fcr31;
910         u32 value;
911         u32 mask;
912
913         if (MIPSInst_RT(ir) == 0)
914                 value = 0;
915         else
916                 value = xcp->regs[MIPSInst_RT(ir)];
917
918         switch (MIPSInst_RD(ir)) {
919         case FPCREG_CSR:
920                 pr_debug("%p gpr[%d]->csr=%08x\n",
921                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
922
923                 /* Preserve read-only bits.  */
924                 mask = boot_cpu_data.fpu_msk31;
925                 fcr31 = (value & ~mask) | (fcr31 & mask);
926                 break;
927
928         case FPCREG_FENR:
929                 if (!cpu_has_mips_r)
930                         break;
931                 pr_debug("%p gpr[%d]->enr=%08x\n",
932                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
933                 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
934                 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
935                          FPU_CSR_FS;
936                 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
937                 break;
938
939         case FPCREG_FEXR:
940                 if (!cpu_has_mips_r)
941                         break;
942                 pr_debug("%p gpr[%d]->exr=%08x\n",
943                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
944                 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
945                 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
946                 break;
947
948         case FPCREG_FCCR:
949                 if (!cpu_has_mips_r)
950                         break;
951                 pr_debug("%p gpr[%d]->ccr=%08x\n",
952                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
953                 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
954                 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
955                          FPU_CSR_COND;
956                 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
957                          FPU_CSR_CONDX;
958                 break;
959
960         default:
961                 break;
962         }
963
964         ctx->fcr31 = fcr31;
965 }
966
967 /*
968  * Emulate the single floating point instruction pointed at by EPC.
969  * Two instructions if the instruction is in a branch delay slot.
970  */
971
972 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
973                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
974 {
975         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
976         unsigned int cond, cbit;
977         mips_instruction ir;
978         int likely, pc_inc;
979         u32 __user *wva;
980         u64 __user *dva;
981         u32 wval;
982         u64 dval;
983         int sig;
984
985         /*
986          * These are giving gcc a gentle hint about what to expect in
987          * dec_inst in order to do better optimization.
988          */
989         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
990                 unreachable();
991
992         /* XXX NEC Vr54xx bug workaround */
993         if (delay_slot(xcp)) {
994                 if (dec_insn.micro_mips_mode) {
995                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
996                                 clear_delay_slot(xcp);
997                 } else {
998                         if (!isBranchInstr(xcp, dec_insn, &contpc))
999                                 clear_delay_slot(xcp);
1000                 }
1001         }
1002
1003         if (delay_slot(xcp)) {
1004                 /*
1005                  * The instruction to be emulated is in a branch delay slot
1006                  * which means that we have to  emulate the branch instruction
1007                  * BEFORE we do the cop1 instruction.
1008                  *
1009                  * This branch could be a COP1 branch, but in that case we
1010                  * would have had a trap for that instruction, and would not
1011                  * come through this route.
1012                  *
1013                  * Linux MIPS branch emulator operates on context, updating the
1014                  * cp0_epc.
1015                  */
1016                 ir = dec_insn.next_insn;  /* process delay slot instr */
1017                 pc_inc = dec_insn.next_pc_inc;
1018         } else {
1019                 ir = dec_insn.insn;       /* process current instr */
1020                 pc_inc = dec_insn.pc_inc;
1021         }
1022
1023         /*
1024          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1025          * instructions, we want to convert microMIPS FPU instructions
1026          * into MIPS32 instructions so that we could reuse all of the
1027          * FPU emulation code.
1028          *
1029          * NOTE: We cannot do this for branch instructions since they
1030          *       are not a subset. Example: Cannot emulate a 16-bit
1031          *       aligned target address with a MIPS32 instruction.
1032          */
1033         if (dec_insn.micro_mips_mode) {
1034                 /*
1035                  * If next instruction is a 16-bit instruction, then it
1036                  * it cannot be a FPU instruction. This could happen
1037                  * since we can be called for non-FPU instructions.
1038                  */
1039                 if ((pc_inc == 2) ||
1040                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1041                          == SIGILL))
1042                         return SIGILL;
1043         }
1044
1045 emul:
1046         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1047         MIPS_FPU_EMU_INC_STATS(emulated);
1048         switch (MIPSInst_OPCODE(ir)) {
1049         case ldc1_op:
1050                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1051                                      MIPSInst_SIMM(ir));
1052                 MIPS_FPU_EMU_INC_STATS(loads);
1053
1054                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1055                         MIPS_FPU_EMU_INC_STATS(errors);
1056                         *fault_addr = dva;
1057                         return SIGBUS;
1058                 }
1059                 if (__get_user(dval, dva)) {
1060                         MIPS_FPU_EMU_INC_STATS(errors);
1061                         *fault_addr = dva;
1062                         return SIGSEGV;
1063                 }
1064                 DITOREG(dval, MIPSInst_RT(ir));
1065                 break;
1066
1067         case sdc1_op:
1068                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1069                                       MIPSInst_SIMM(ir));
1070                 MIPS_FPU_EMU_INC_STATS(stores);
1071                 DIFROMREG(dval, MIPSInst_RT(ir));
1072                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1073                         MIPS_FPU_EMU_INC_STATS(errors);
1074                         *fault_addr = dva;
1075                         return SIGBUS;
1076                 }
1077                 if (__put_user(dval, dva)) {
1078                         MIPS_FPU_EMU_INC_STATS(errors);
1079                         *fault_addr = dva;
1080                         return SIGSEGV;
1081                 }
1082                 break;
1083
1084         case lwc1_op:
1085                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1086                                       MIPSInst_SIMM(ir));
1087                 MIPS_FPU_EMU_INC_STATS(loads);
1088                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1089                         MIPS_FPU_EMU_INC_STATS(errors);
1090                         *fault_addr = wva;
1091                         return SIGBUS;
1092                 }
1093                 if (__get_user(wval, wva)) {
1094                         MIPS_FPU_EMU_INC_STATS(errors);
1095                         *fault_addr = wva;
1096                         return SIGSEGV;
1097                 }
1098                 SITOREG(wval, MIPSInst_RT(ir));
1099                 break;
1100
1101         case swc1_op:
1102                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1103                                       MIPSInst_SIMM(ir));
1104                 MIPS_FPU_EMU_INC_STATS(stores);
1105                 SIFROMREG(wval, MIPSInst_RT(ir));
1106                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1107                         MIPS_FPU_EMU_INC_STATS(errors);
1108                         *fault_addr = wva;
1109                         return SIGBUS;
1110                 }
1111                 if (__put_user(wval, wva)) {
1112                         MIPS_FPU_EMU_INC_STATS(errors);
1113                         *fault_addr = wva;
1114                         return SIGSEGV;
1115                 }
1116                 break;
1117
1118         case cop1_op:
1119                 switch (MIPSInst_RS(ir)) {
1120                 case dmfc_op:
1121                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1122                                 return SIGILL;
1123
1124                         /* copregister fs -> gpr[rt] */
1125                         if (MIPSInst_RT(ir) != 0) {
1126                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1127                                         MIPSInst_RD(ir));
1128                         }
1129                         break;
1130
1131                 case dmtc_op:
1132                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1133                                 return SIGILL;
1134
1135                         /* copregister fs <- rt */
1136                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1137                         break;
1138
1139                 case mfhc_op:
1140                         if (!cpu_has_mips_r2_r6)
1141                                 goto sigill;
1142
1143                         /* copregister rd -> gpr[rt] */
1144                         if (MIPSInst_RT(ir) != 0) {
1145                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1146                                         MIPSInst_RD(ir));
1147                         }
1148                         break;
1149
1150                 case mthc_op:
1151                         if (!cpu_has_mips_r2_r6)
1152                                 goto sigill;
1153
1154                         /* copregister rd <- gpr[rt] */
1155                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1156                         break;
1157
1158                 case mfc_op:
1159                         /* copregister rd -> gpr[rt] */
1160                         if (MIPSInst_RT(ir) != 0) {
1161                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1162                                         MIPSInst_RD(ir));
1163                         }
1164                         break;
1165
1166                 case mtc_op:
1167                         /* copregister rd <- rt */
1168                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1169                         break;
1170
1171                 case cfc_op:
1172                         /* cop control register rd -> gpr[rt] */
1173                         cop1_cfc(xcp, ctx, ir);
1174                         break;
1175
1176                 case ctc_op:
1177                         /* copregister rd <- rt */
1178                         cop1_ctc(xcp, ctx, ir);
1179                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1180                                 return SIGFPE;
1181                         }
1182                         break;
1183
1184                 case bc1eqz_op:
1185                 case bc1nez_op:
1186                         if (!cpu_has_mips_r6 || delay_slot(xcp))
1187                                 return SIGILL;
1188
1189                         cond = likely = 0;
1190                         switch (MIPSInst_RS(ir)) {
1191                         case bc1eqz_op:
1192                                 if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)
1193                                     cond = 1;
1194                                 break;
1195                         case bc1nez_op:
1196                                 if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))
1197                                     cond = 1;
1198                                 break;
1199                         }
1200                         goto branch_common;
1201
1202                 case bc_op:
1203                         if (delay_slot(xcp))
1204                                 return SIGILL;
1205
1206                         if (cpu_has_mips_4_5_r)
1207                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1208                         else
1209                                 cbit = FPU_CSR_COND;
1210                         cond = ctx->fcr31 & cbit;
1211
1212                         likely = 0;
1213                         switch (MIPSInst_RT(ir) & 3) {
1214                         case bcfl_op:
1215                                 if (cpu_has_mips_2_3_4_5_r)
1216                                         likely = 1;
1217                                 /* Fall through */
1218                         case bcf_op:
1219                                 cond = !cond;
1220                                 break;
1221                         case bctl_op:
1222                                 if (cpu_has_mips_2_3_4_5_r)
1223                                         likely = 1;
1224                                 /* Fall through */
1225                         case bct_op:
1226                                 break;
1227                         }
1228 branch_common:
1229                         set_delay_slot(xcp);
1230                         if (cond) {
1231                                 /*
1232                                  * Branch taken: emulate dslot instruction
1233                                  */
1234                                 unsigned long bcpc;
1235
1236                                 /*
1237                                  * Remember EPC at the branch to point back
1238                                  * at so that any delay-slot instruction
1239                                  * signal is not silently ignored.
1240                                  */
1241                                 bcpc = xcp->cp0_epc;
1242                                 xcp->cp0_epc += dec_insn.pc_inc;
1243
1244                                 contpc = MIPSInst_SIMM(ir);
1245                                 ir = dec_insn.next_insn;
1246                                 if (dec_insn.micro_mips_mode) {
1247                                         contpc = (xcp->cp0_epc + (contpc << 1));
1248
1249                                         /* If 16-bit instruction, not FPU. */
1250                                         if ((dec_insn.next_pc_inc == 2) ||
1251                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1252
1253                                                 /*
1254                                                  * Since this instruction will
1255                                                  * be put on the stack with
1256                                                  * 32-bit words, get around
1257                                                  * this problem by putting a
1258                                                  * NOP16 as the second one.
1259                                                  */
1260                                                 if (dec_insn.next_pc_inc == 2)
1261                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1262
1263                                                 /*
1264                                                  * Single step the non-CP1
1265                                                  * instruction in the dslot.
1266                                                  */
1267                                                 sig = mips_dsemul(xcp, ir,
1268                                                                   contpc);
1269                                                 if (sig)
1270                                                         xcp->cp0_epc = bcpc;
1271                                                 /*
1272                                                  * SIGILL forces out of
1273                                                  * the emulation loop.
1274                                                  */
1275                                                 return sig ? sig : SIGILL;
1276                                         }
1277                                 } else
1278                                         contpc = (xcp->cp0_epc + (contpc << 2));
1279
1280                                 switch (MIPSInst_OPCODE(ir)) {
1281                                 case lwc1_op:
1282                                 case swc1_op:
1283                                         goto emul;
1284
1285                                 case ldc1_op:
1286                                 case sdc1_op:
1287                                         if (cpu_has_mips_2_3_4_5_r)
1288                                                 goto emul;
1289
1290                                         goto bc_sigill;
1291
1292                                 case cop1_op:
1293                                         goto emul;
1294
1295                                 case cop1x_op:
1296                                         if (cpu_has_mips_4_5_64_r2_r6)
1297                                                 /* its one of ours */
1298                                                 goto emul;
1299
1300                                         goto bc_sigill;
1301
1302                                 case spec_op:
1303                                         switch (MIPSInst_FUNC(ir)) {
1304                                         case movc_op:
1305                                                 if (cpu_has_mips_4_5_r)
1306                                                         goto emul;
1307
1308                                                 goto bc_sigill;
1309                                         }
1310                                         break;
1311
1312                                 bc_sigill:
1313                                         xcp->cp0_epc = bcpc;
1314                                         return SIGILL;
1315                                 }
1316
1317                                 /*
1318                                  * Single step the non-cp1
1319                                  * instruction in the dslot
1320                                  */
1321                                 sig = mips_dsemul(xcp, ir, contpc);
1322                                 if (sig)
1323                                         xcp->cp0_epc = bcpc;
1324                                 /* SIGILL forces out of the emulation loop.  */
1325                                 return sig ? sig : SIGILL;
1326                         } else if (likely) {    /* branch not taken */
1327                                 /*
1328                                  * branch likely nullifies
1329                                  * dslot if not taken
1330                                  */
1331                                 xcp->cp0_epc += dec_insn.pc_inc;
1332                                 contpc += dec_insn.pc_inc;
1333                                 /*
1334                                  * else continue & execute
1335                                  * dslot as normal insn
1336                                  */
1337                         }
1338                         break;
1339
1340                 default:
1341                         if (!(MIPSInst_RS(ir) & 0x10))
1342                                 return SIGILL;
1343
1344                         /* a real fpu computation instruction */
1345                         if ((sig = fpu_emu(xcp, ctx, ir)))
1346                                 return sig;
1347                 }
1348                 break;
1349
1350         case cop1x_op:
1351                 if (!cpu_has_mips_4_5_64_r2_r6)
1352                         return SIGILL;
1353
1354                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1355                 if (sig)
1356                         return sig;
1357                 break;
1358
1359         case spec_op:
1360                 if (!cpu_has_mips_4_5_r)
1361                         return SIGILL;
1362
1363                 if (MIPSInst_FUNC(ir) != movc_op)
1364                         return SIGILL;
1365                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1366                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1367                         xcp->regs[MIPSInst_RD(ir)] =
1368                                 xcp->regs[MIPSInst_RS(ir)];
1369                 break;
1370         default:
1371 sigill:
1372                 return SIGILL;
1373         }
1374
1375         /* we did it !! */
1376         xcp->cp0_epc = contpc;
1377         clear_delay_slot(xcp);
1378
1379         return 0;
1380 }
1381
1382 /*
1383  * Conversion table from MIPS compare ops 48-63
1384  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1385  */
1386 static const unsigned char cmptab[8] = {
1387         0,                      /* cmp_0 (sig) cmp_sf */
1388         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1389         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1390         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1391         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1392         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1393         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1394         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1395 };
1396
1397 static const unsigned char negative_cmptab[8] = {
1398         0, /* Reserved */
1399         IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
1400         IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
1401         IEEE754_CLT | IEEE754_CGT,
1402         /* Reserved */
1403 };
1404
1405
1406 /*
1407  * Additional MIPS4 instructions
1408  */
1409
1410 #define DEF3OP(name, p, f1, f2, f3)                                     \
1411 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1412         union ieee754##p s, union ieee754##p t)                         \
1413 {                                                                       \
1414         struct _ieee754_csr ieee754_csr_save;                           \
1415         s = f1(s, t);                                                   \
1416         ieee754_csr_save = ieee754_csr;                                 \
1417         s = f2(s, r);                                                   \
1418         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1419         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1420         s = f3(s);                                                      \
1421         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1422         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1423         return s;                                                       \
1424 }
1425
1426 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1427 {
1428         return ieee754dp_div(ieee754dp_one(0), d);
1429 }
1430
1431 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1432 {
1433         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1434 }
1435
1436 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1437 {
1438         return ieee754sp_div(ieee754sp_one(0), s);
1439 }
1440
1441 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1442 {
1443         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1444 }
1445
1446 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1447 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1448 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1449 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1450 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1451 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1452 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1453 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1454
1455 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1456         mips_instruction ir, void *__user *fault_addr)
1457 {
1458         unsigned rcsr = 0;      /* resulting csr */
1459
1460         MIPS_FPU_EMU_INC_STATS(cp1xops);
1461
1462         switch (MIPSInst_FMA_FFMT(ir)) {
1463         case s_fmt:{            /* 0 */
1464
1465                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1466                 union ieee754sp fd, fr, fs, ft;
1467                 u32 __user *va;
1468                 u32 val;
1469
1470                 switch (MIPSInst_FUNC(ir)) {
1471                 case lwxc1_op:
1472                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1473                                 xcp->regs[MIPSInst_FT(ir)]);
1474
1475                         MIPS_FPU_EMU_INC_STATS(loads);
1476                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1477                                 MIPS_FPU_EMU_INC_STATS(errors);
1478                                 *fault_addr = va;
1479                                 return SIGBUS;
1480                         }
1481                         if (__get_user(val, va)) {
1482                                 MIPS_FPU_EMU_INC_STATS(errors);
1483                                 *fault_addr = va;
1484                                 return SIGSEGV;
1485                         }
1486                         SITOREG(val, MIPSInst_FD(ir));
1487                         break;
1488
1489                 case swxc1_op:
1490                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1491                                 xcp->regs[MIPSInst_FT(ir)]);
1492
1493                         MIPS_FPU_EMU_INC_STATS(stores);
1494
1495                         SIFROMREG(val, MIPSInst_FS(ir));
1496                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1497                                 MIPS_FPU_EMU_INC_STATS(errors);
1498                                 *fault_addr = va;
1499                                 return SIGBUS;
1500                         }
1501                         if (put_user(val, va)) {
1502                                 MIPS_FPU_EMU_INC_STATS(errors);
1503                                 *fault_addr = va;
1504                                 return SIGSEGV;
1505                         }
1506                         break;
1507
1508                 case madd_s_op:
1509                         handler = fpemu_sp_madd;
1510                         goto scoptop;
1511                 case msub_s_op:
1512                         handler = fpemu_sp_msub;
1513                         goto scoptop;
1514                 case nmadd_s_op:
1515                         handler = fpemu_sp_nmadd;
1516                         goto scoptop;
1517                 case nmsub_s_op:
1518                         handler = fpemu_sp_nmsub;
1519                         goto scoptop;
1520
1521                       scoptop:
1522                         SPFROMREG(fr, MIPSInst_FR(ir));
1523                         SPFROMREG(fs, MIPSInst_FS(ir));
1524                         SPFROMREG(ft, MIPSInst_FT(ir));
1525                         fd = (*handler) (fr, fs, ft);
1526                         SPTOREG(fd, MIPSInst_FD(ir));
1527
1528                       copcsr:
1529                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1530                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1531                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1532                         }
1533                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1534                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1535                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1536                         }
1537                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1538                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1539                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1540                         }
1541                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1542                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1543                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1544                         }
1545
1546                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1547                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1548                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1549                                    ctx->fcr31); */
1550                                 return SIGFPE;
1551                         }
1552
1553                         break;
1554
1555                 default:
1556                         return SIGILL;
1557                 }
1558                 break;
1559         }
1560
1561         case d_fmt:{            /* 1 */
1562                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1563                 union ieee754dp fd, fr, fs, ft;
1564                 u64 __user *va;
1565                 u64 val;
1566
1567                 switch (MIPSInst_FUNC(ir)) {
1568                 case ldxc1_op:
1569                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1570                                 xcp->regs[MIPSInst_FT(ir)]);
1571
1572                         MIPS_FPU_EMU_INC_STATS(loads);
1573                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1574                                 MIPS_FPU_EMU_INC_STATS(errors);
1575                                 *fault_addr = va;
1576                                 return SIGBUS;
1577                         }
1578                         if (__get_user(val, va)) {
1579                                 MIPS_FPU_EMU_INC_STATS(errors);
1580                                 *fault_addr = va;
1581                                 return SIGSEGV;
1582                         }
1583                         DITOREG(val, MIPSInst_FD(ir));
1584                         break;
1585
1586                 case sdxc1_op:
1587                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1588                                 xcp->regs[MIPSInst_FT(ir)]);
1589
1590                         MIPS_FPU_EMU_INC_STATS(stores);
1591                         DIFROMREG(val, MIPSInst_FS(ir));
1592                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1593                                 MIPS_FPU_EMU_INC_STATS(errors);
1594                                 *fault_addr = va;
1595                                 return SIGBUS;
1596                         }
1597                         if (__put_user(val, va)) {
1598                                 MIPS_FPU_EMU_INC_STATS(errors);
1599                                 *fault_addr = va;
1600                                 return SIGSEGV;
1601                         }
1602                         break;
1603
1604                 case madd_d_op:
1605                         handler = fpemu_dp_madd;
1606                         goto dcoptop;
1607                 case msub_d_op:
1608                         handler = fpemu_dp_msub;
1609                         goto dcoptop;
1610                 case nmadd_d_op:
1611                         handler = fpemu_dp_nmadd;
1612                         goto dcoptop;
1613                 case nmsub_d_op:
1614                         handler = fpemu_dp_nmsub;
1615                         goto dcoptop;
1616
1617                       dcoptop:
1618                         DPFROMREG(fr, MIPSInst_FR(ir));
1619                         DPFROMREG(fs, MIPSInst_FS(ir));
1620                         DPFROMREG(ft, MIPSInst_FT(ir));
1621                         fd = (*handler) (fr, fs, ft);
1622                         DPTOREG(fd, MIPSInst_FD(ir));
1623                         goto copcsr;
1624
1625                 default:
1626                         return SIGILL;
1627                 }
1628                 break;
1629         }
1630
1631         case 0x3:
1632                 if (MIPSInst_FUNC(ir) != pfetch_op)
1633                         return SIGILL;
1634
1635                 /* ignore prefx operation */
1636                 break;
1637
1638         default:
1639                 return SIGILL;
1640         }
1641
1642         return 0;
1643 }
1644
1645
1646
1647 /*
1648  * Emulate a single COP1 arithmetic instruction.
1649  */
1650 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1651         mips_instruction ir)
1652 {
1653         int rfmt;               /* resulting format */
1654         unsigned rcsr = 0;      /* resulting csr */
1655         unsigned int oldrm;
1656         unsigned int cbit;
1657         unsigned cond;
1658         union {
1659                 union ieee754dp d;
1660                 union ieee754sp s;
1661                 int w;
1662                 s64 l;
1663         } rv;                   /* resulting value */
1664         u64 bits;
1665
1666         MIPS_FPU_EMU_INC_STATS(cp1ops);
1667         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1668         case s_fmt: {           /* 0 */
1669                 union {
1670                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1671                         union ieee754sp(*u) (union ieee754sp);
1672                 } handler;
1673                 union ieee754sp fs, ft;
1674
1675                 switch (MIPSInst_FUNC(ir)) {
1676                         /* binary ops */
1677                 case fadd_op:
1678                         handler.b = ieee754sp_add;
1679                         goto scopbop;
1680                 case fsub_op:
1681                         handler.b = ieee754sp_sub;
1682                         goto scopbop;
1683                 case fmul_op:
1684                         handler.b = ieee754sp_mul;
1685                         goto scopbop;
1686                 case fdiv_op:
1687                         handler.b = ieee754sp_div;
1688                         goto scopbop;
1689
1690                         /* unary  ops */
1691                 case fsqrt_op:
1692                         if (!cpu_has_mips_2_3_4_5_r)
1693                                 return SIGILL;
1694
1695                         handler.u = ieee754sp_sqrt;
1696                         goto scopuop;
1697
1698                 /*
1699                  * Note that on some MIPS IV implementations such as the
1700                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1701                  * achieve full IEEE-754 accuracy - however this emulator does.
1702                  */
1703                 case frsqrt_op:
1704                         if (!cpu_has_mips_4_5_64_r2_r6)
1705                                 return SIGILL;
1706
1707                         handler.u = fpemu_sp_rsqrt;
1708                         goto scopuop;
1709
1710                 case frecip_op:
1711                         if (!cpu_has_mips_4_5_64_r2_r6)
1712                                 return SIGILL;
1713
1714                         handler.u = fpemu_sp_recip;
1715                         goto scopuop;
1716
1717                 case fmovc_op:
1718                         if (!cpu_has_mips_4_5_r)
1719                                 return SIGILL;
1720
1721                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1722                         if (((ctx->fcr31 & cond) != 0) !=
1723                                 ((MIPSInst_FT(ir) & 1) != 0))
1724                                 return 0;
1725                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1726                         break;
1727
1728                 case fmovz_op:
1729                         if (!cpu_has_mips_4_5_r)
1730                                 return SIGILL;
1731
1732                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1733                                 return 0;
1734                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1735                         break;
1736
1737                 case fmovn_op:
1738                         if (!cpu_has_mips_4_5_r)
1739                                 return SIGILL;
1740
1741                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1742                                 return 0;
1743                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1744                         break;
1745
1746                 case fabs_op:
1747                         handler.u = ieee754sp_abs;
1748                         goto scopuop;
1749
1750                 case fneg_op:
1751                         handler.u = ieee754sp_neg;
1752                         goto scopuop;
1753
1754                 case fmov_op:
1755                         /* an easy one */
1756                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1757                         goto copcsr;
1758
1759                         /* binary op on handler */
1760 scopbop:
1761                         SPFROMREG(fs, MIPSInst_FS(ir));
1762                         SPFROMREG(ft, MIPSInst_FT(ir));
1763
1764                         rv.s = (*handler.b) (fs, ft);
1765                         goto copcsr;
1766 scopuop:
1767                         SPFROMREG(fs, MIPSInst_FS(ir));
1768                         rv.s = (*handler.u) (fs);
1769                         goto copcsr;
1770 copcsr:
1771                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1772                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1773                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1774                         }
1775                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1776                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1777                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1778                         }
1779                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1780                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1781                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1782                         }
1783                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1784                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1785                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1786                         }
1787                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1788                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1789                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1790                         }
1791                         break;
1792
1793                         /* unary conv ops */
1794                 case fcvts_op:
1795                         return SIGILL;  /* not defined */
1796
1797                 case fcvtd_op:
1798                         SPFROMREG(fs, MIPSInst_FS(ir));
1799                         rv.d = ieee754dp_fsp(fs);
1800                         rfmt = d_fmt;
1801                         goto copcsr;
1802
1803                 case fcvtw_op:
1804                         SPFROMREG(fs, MIPSInst_FS(ir));
1805                         rv.w = ieee754sp_tint(fs);
1806                         rfmt = w_fmt;
1807                         goto copcsr;
1808
1809                 case fround_op:
1810                 case ftrunc_op:
1811                 case fceil_op:
1812                 case ffloor_op:
1813                         if (!cpu_has_mips_2_3_4_5_r)
1814                                 return SIGILL;
1815
1816                         oldrm = ieee754_csr.rm;
1817                         SPFROMREG(fs, MIPSInst_FS(ir));
1818                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1819                         rv.w = ieee754sp_tint(fs);
1820                         ieee754_csr.rm = oldrm;
1821                         rfmt = w_fmt;
1822                         goto copcsr;
1823
1824                 case fcvtl_op:
1825                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1826                                 return SIGILL;
1827
1828                         SPFROMREG(fs, MIPSInst_FS(ir));
1829                         rv.l = ieee754sp_tlong(fs);
1830                         rfmt = l_fmt;
1831                         goto copcsr;
1832
1833                 case froundl_op:
1834                 case ftruncl_op:
1835                 case fceill_op:
1836                 case ffloorl_op:
1837                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1838                                 return SIGILL;
1839
1840                         oldrm = ieee754_csr.rm;
1841                         SPFROMREG(fs, MIPSInst_FS(ir));
1842                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1843                         rv.l = ieee754sp_tlong(fs);
1844                         ieee754_csr.rm = oldrm;
1845                         rfmt = l_fmt;
1846                         goto copcsr;
1847
1848                 default:
1849                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
1850                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1851                                 union ieee754sp fs, ft;
1852
1853                                 SPFROMREG(fs, MIPSInst_FS(ir));
1854                                 SPFROMREG(ft, MIPSInst_FT(ir));
1855                                 rv.w = ieee754sp_cmp(fs, ft,
1856                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1857                                 rfmt = -1;
1858                                 if ((cmpop & 0x8) && ieee754_cxtest
1859                                         (IEEE754_INVALID_OPERATION))
1860                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1861                                 else
1862                                         goto copcsr;
1863
1864                         } else
1865                                 return SIGILL;
1866                         break;
1867                 }
1868                 break;
1869         }
1870
1871         case d_fmt: {
1872                 union ieee754dp fs, ft;
1873                 union {
1874                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1875                         union ieee754dp(*u) (union ieee754dp);
1876                 } handler;
1877
1878                 switch (MIPSInst_FUNC(ir)) {
1879                         /* binary ops */
1880                 case fadd_op:
1881                         handler.b = ieee754dp_add;
1882                         goto dcopbop;
1883                 case fsub_op:
1884                         handler.b = ieee754dp_sub;
1885                         goto dcopbop;
1886                 case fmul_op:
1887                         handler.b = ieee754dp_mul;
1888                         goto dcopbop;
1889                 case fdiv_op:
1890                         handler.b = ieee754dp_div;
1891                         goto dcopbop;
1892
1893                         /* unary  ops */
1894                 case fsqrt_op:
1895                         if (!cpu_has_mips_2_3_4_5_r)
1896                                 return SIGILL;
1897
1898                         handler.u = ieee754dp_sqrt;
1899                         goto dcopuop;
1900                 /*
1901                  * Note that on some MIPS IV implementations such as the
1902                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1903                  * achieve full IEEE-754 accuracy - however this emulator does.
1904                  */
1905                 case frsqrt_op:
1906                         if (!cpu_has_mips_4_5_64_r2_r6)
1907                                 return SIGILL;
1908
1909                         handler.u = fpemu_dp_rsqrt;
1910                         goto dcopuop;
1911                 case frecip_op:
1912                         if (!cpu_has_mips_4_5_64_r2_r6)
1913                                 return SIGILL;
1914
1915                         handler.u = fpemu_dp_recip;
1916                         goto dcopuop;
1917                 case fmovc_op:
1918                         if (!cpu_has_mips_4_5_r)
1919                                 return SIGILL;
1920
1921                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1922                         if (((ctx->fcr31 & cond) != 0) !=
1923                                 ((MIPSInst_FT(ir) & 1) != 0))
1924                                 return 0;
1925                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1926                         break;
1927                 case fmovz_op:
1928                         if (!cpu_has_mips_4_5_r)
1929                                 return SIGILL;
1930
1931                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1932                                 return 0;
1933                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1934                         break;
1935                 case fmovn_op:
1936                         if (!cpu_has_mips_4_5_r)
1937                                 return SIGILL;
1938
1939                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1940                                 return 0;
1941                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1942                         break;
1943                 case fabs_op:
1944                         handler.u = ieee754dp_abs;
1945                         goto dcopuop;
1946
1947                 case fneg_op:
1948                         handler.u = ieee754dp_neg;
1949                         goto dcopuop;
1950
1951                 case fmov_op:
1952                         /* an easy one */
1953                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1954                         goto copcsr;
1955
1956                         /* binary op on handler */
1957 dcopbop:
1958                         DPFROMREG(fs, MIPSInst_FS(ir));
1959                         DPFROMREG(ft, MIPSInst_FT(ir));
1960
1961                         rv.d = (*handler.b) (fs, ft);
1962                         goto copcsr;
1963 dcopuop:
1964                         DPFROMREG(fs, MIPSInst_FS(ir));
1965                         rv.d = (*handler.u) (fs);
1966                         goto copcsr;
1967
1968                 /*
1969                  * unary conv ops
1970                  */
1971                 case fcvts_op:
1972                         DPFROMREG(fs, MIPSInst_FS(ir));
1973                         rv.s = ieee754sp_fdp(fs);
1974                         rfmt = s_fmt;
1975                         goto copcsr;
1976
1977                 case fcvtd_op:
1978                         return SIGILL;  /* not defined */
1979
1980                 case fcvtw_op:
1981                         DPFROMREG(fs, MIPSInst_FS(ir));
1982                         rv.w = ieee754dp_tint(fs);      /* wrong */
1983                         rfmt = w_fmt;
1984                         goto copcsr;
1985
1986                 case fround_op:
1987                 case ftrunc_op:
1988                 case fceil_op:
1989                 case ffloor_op:
1990                         if (!cpu_has_mips_2_3_4_5_r)
1991                                 return SIGILL;
1992
1993                         oldrm = ieee754_csr.rm;
1994                         DPFROMREG(fs, MIPSInst_FS(ir));
1995                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1996                         rv.w = ieee754dp_tint(fs);
1997                         ieee754_csr.rm = oldrm;
1998                         rfmt = w_fmt;
1999                         goto copcsr;
2000
2001                 case fcvtl_op:
2002                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2003                                 return SIGILL;
2004
2005                         DPFROMREG(fs, MIPSInst_FS(ir));
2006                         rv.l = ieee754dp_tlong(fs);
2007                         rfmt = l_fmt;
2008                         goto copcsr;
2009
2010                 case froundl_op:
2011                 case ftruncl_op:
2012                 case fceill_op:
2013                 case ffloorl_op:
2014                         if (!cpu_has_mips_3_4_5_64_r2_r6)
2015                                 return SIGILL;
2016
2017                         oldrm = ieee754_csr.rm;
2018                         DPFROMREG(fs, MIPSInst_FS(ir));
2019                         ieee754_csr.rm = MIPSInst_FUNC(ir);
2020                         rv.l = ieee754dp_tlong(fs);
2021                         ieee754_csr.rm = oldrm;
2022                         rfmt = l_fmt;
2023                         goto copcsr;
2024
2025                 default:
2026                         if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
2027                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2028                                 union ieee754dp fs, ft;
2029
2030                                 DPFROMREG(fs, MIPSInst_FS(ir));
2031                                 DPFROMREG(ft, MIPSInst_FT(ir));
2032                                 rv.w = ieee754dp_cmp(fs, ft,
2033                                         cmptab[cmpop & 0x7], cmpop & 0x8);
2034                                 rfmt = -1;
2035                                 if ((cmpop & 0x8)
2036                                         &&
2037                                         ieee754_cxtest
2038                                         (IEEE754_INVALID_OPERATION))
2039                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2040                                 else
2041                                         goto copcsr;
2042
2043                         }
2044                         else {
2045                                 return SIGILL;
2046                         }
2047                         break;
2048                 }
2049                 break;
2050         }
2051
2052         case w_fmt: {
2053                 union ieee754dp fs;
2054
2055                 switch (MIPSInst_FUNC(ir)) {
2056                 case fcvts_op:
2057                         /* convert word to single precision real */
2058                         SPFROMREG(fs, MIPSInst_FS(ir));
2059                         rv.s = ieee754sp_fint(fs.bits);
2060                         rfmt = s_fmt;
2061                         goto copcsr;
2062                 case fcvtd_op:
2063                         /* convert word to double precision real */
2064                         SPFROMREG(fs, MIPSInst_FS(ir));
2065                         rv.d = ieee754dp_fint(fs.bits);
2066                         rfmt = d_fmt;
2067                         goto copcsr;
2068                 default: {
2069                         /* Emulating the new CMP.condn.fmt R6 instruction */
2070 #define CMPOP_MASK      0x7
2071 #define SIGN_BIT        (0x1 << 3)
2072 #define PREDICATE_BIT   (0x1 << 4)
2073
2074                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2075                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2076                         union ieee754sp fs, ft;
2077
2078                         /* This is an R6 only instruction */
2079                         if (!cpu_has_mips_r6 ||
2080                             (MIPSInst_FUNC(ir) & 0x20))
2081                                 return SIGILL;
2082
2083                         /* fmt is w_fmt for single precision so fix it */
2084                         rfmt = s_fmt;
2085                         /* default to false */
2086                         rv.w = 0;
2087
2088                         /* CMP.condn.S */
2089                         SPFROMREG(fs, MIPSInst_FS(ir));
2090                         SPFROMREG(ft, MIPSInst_FT(ir));
2091
2092                         /* positive predicates */
2093                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2094                                 if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
2095                                                   sig))
2096                                     rv.w = -1; /* true, all 1s */
2097                                 if ((sig) &&
2098                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2099                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2100                                 else
2101                                         goto copcsr;
2102                         } else {
2103                                 /* negative predicates */
2104                                 switch (cmpop) {
2105                                 case 1:
2106                                 case 2:
2107                                 case 3:
2108                                         if (ieee754sp_cmp(fs, ft,
2109                                                           negative_cmptab[cmpop],
2110                                                           sig))
2111                                                 rv.w = -1; /* true, all 1s */
2112                                         if (sig &&
2113                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2114                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2115                                         else
2116                                                 goto copcsr;
2117                                         break;
2118                                 default:
2119                                         /* Reserved R6 ops */
2120                                         pr_err("Reserved MIPS R6 CMP.condn.S operation\n");
2121                                         return SIGILL;
2122                                 }
2123                         }
2124                         break;
2125                         }
2126                 }
2127         }
2128
2129         case l_fmt:
2130
2131                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2132                         return SIGILL;
2133
2134                 DIFROMREG(bits, MIPSInst_FS(ir));
2135
2136                 switch (MIPSInst_FUNC(ir)) {
2137                 case fcvts_op:
2138                         /* convert long to single precision real */
2139                         rv.s = ieee754sp_flong(bits);
2140                         rfmt = s_fmt;
2141                         goto copcsr;
2142                 case fcvtd_op:
2143                         /* convert long to double precision real */
2144                         rv.d = ieee754dp_flong(bits);
2145                         rfmt = d_fmt;
2146                         goto copcsr;
2147                 default: {
2148                         /* Emulating the new CMP.condn.fmt R6 instruction */
2149                         int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
2150                         int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
2151                         union ieee754dp fs, ft;
2152
2153                         if (!cpu_has_mips_r6 ||
2154                             (MIPSInst_FUNC(ir) & 0x20))
2155                                 return SIGILL;
2156
2157                         /* fmt is l_fmt for double precision so fix it */
2158                         rfmt = d_fmt;
2159                         /* default to false */
2160                         rv.l = 0;
2161
2162                         /* CMP.condn.D */
2163                         DPFROMREG(fs, MIPSInst_FS(ir));
2164                         DPFROMREG(ft, MIPSInst_FT(ir));
2165
2166                         /* positive predicates */
2167                         if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
2168                                 if (ieee754dp_cmp(fs, ft,
2169                                                   cmptab[cmpop], sig))
2170                                     rv.l = -1LL; /* true, all 1s */
2171                                 if (sig &&
2172                                     ieee754_cxtest(IEEE754_INVALID_OPERATION))
2173                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2174                                 else
2175                                         goto copcsr;
2176                         } else {
2177                                 /* negative predicates */
2178                                 switch (cmpop) {
2179                                 case 1:
2180                                 case 2:
2181                                 case 3:
2182                                         if (ieee754dp_cmp(fs, ft,
2183                                                           negative_cmptab[cmpop],
2184                                                           sig))
2185                                                 rv.l = -1LL; /* true, all 1s */
2186                                         if (sig &&
2187                                             ieee754_cxtest(IEEE754_INVALID_OPERATION))
2188                                                 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2189                                         else
2190                                                 goto copcsr;
2191                                         break;
2192                                 default:
2193                                         /* Reserved R6 ops */
2194                                         pr_err("Reserved MIPS R6 CMP.condn.D operation\n");
2195                                         return SIGILL;
2196                                 }
2197                         }
2198                         break;
2199                         }
2200                 }
2201         default:
2202                 return SIGILL;
2203         }
2204
2205         /*
2206          * Update the fpu CSR register for this operation.
2207          * If an exception is required, generate a tidy SIGFPE exception,
2208          * without updating the result register.
2209          * Note: cause exception bits do not accumulate, they are rewritten
2210          * for each op; only the flag/sticky bits accumulate.
2211          */
2212         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2213         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2214                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2215                 return SIGFPE;
2216         }
2217
2218         /*
2219          * Now we can safely write the result back to the register file.
2220          */
2221         switch (rfmt) {
2222         case -1:
2223
2224                 if (cpu_has_mips_4_5_r)
2225                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2226                 else
2227                         cbit = FPU_CSR_COND;
2228                 if (rv.w)
2229                         ctx->fcr31 |= cbit;
2230                 else
2231                         ctx->fcr31 &= ~cbit;
2232                 break;
2233
2234         case d_fmt:
2235                 DPTOREG(rv.d, MIPSInst_FD(ir));
2236                 break;
2237         case s_fmt:
2238                 SPTOREG(rv.s, MIPSInst_FD(ir));
2239                 break;
2240         case w_fmt:
2241                 SITOREG(rv.w, MIPSInst_FD(ir));
2242                 break;
2243         case l_fmt:
2244                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2245                         return SIGILL;
2246
2247                 DITOREG(rv.l, MIPSInst_FD(ir));
2248                 break;
2249         default:
2250                 return SIGILL;
2251         }
2252
2253         return 0;
2254 }
2255
2256 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2257         int has_fpu, void *__user *fault_addr)
2258 {
2259         unsigned long oldepc, prevepc;
2260         struct mm_decoded_insn dec_insn;
2261         u16 instr[4];
2262         u16 *instr_ptr;
2263         int sig = 0;
2264
2265         oldepc = xcp->cp0_epc;
2266         do {
2267                 prevepc = xcp->cp0_epc;
2268
2269                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2270                         /*
2271                          * Get next 2 microMIPS instructions and convert them
2272                          * into 32-bit instructions.
2273                          */
2274                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2275                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2276                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2277                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2278                                 MIPS_FPU_EMU_INC_STATS(errors);
2279                                 return SIGBUS;
2280                         }
2281                         instr_ptr = instr;
2282
2283                         /* Get first instruction. */
2284                         if (mm_insn_16bit(*instr_ptr)) {
2285                                 /* Duplicate the half-word. */
2286                                 dec_insn.insn = (*instr_ptr << 16) |
2287                                         (*instr_ptr);
2288                                 /* 16-bit instruction. */
2289                                 dec_insn.pc_inc = 2;
2290                                 instr_ptr += 1;
2291                         } else {
2292                                 dec_insn.insn = (*instr_ptr << 16) |
2293                                         *(instr_ptr+1);
2294                                 /* 32-bit instruction. */
2295                                 dec_insn.pc_inc = 4;
2296                                 instr_ptr += 2;
2297                         }
2298                         /* Get second instruction. */
2299                         if (mm_insn_16bit(*instr_ptr)) {
2300                                 /* Duplicate the half-word. */
2301                                 dec_insn.next_insn = (*instr_ptr << 16) |
2302                                         (*instr_ptr);
2303                                 /* 16-bit instruction. */
2304                                 dec_insn.next_pc_inc = 2;
2305                         } else {
2306                                 dec_insn.next_insn = (*instr_ptr << 16) |
2307                                         *(instr_ptr+1);
2308                                 /* 32-bit instruction. */
2309                                 dec_insn.next_pc_inc = 4;
2310                         }
2311                         dec_insn.micro_mips_mode = 1;
2312                 } else {
2313                         if ((get_user(dec_insn.insn,
2314                             (mips_instruction __user *) xcp->cp0_epc)) ||
2315                             (get_user(dec_insn.next_insn,
2316                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2317                                 MIPS_FPU_EMU_INC_STATS(errors);
2318                                 return SIGBUS;
2319                         }
2320                         dec_insn.pc_inc = 4;
2321                         dec_insn.next_pc_inc = 4;
2322                         dec_insn.micro_mips_mode = 0;
2323                 }
2324
2325                 if ((dec_insn.insn == 0) ||
2326                    ((dec_insn.pc_inc == 2) &&
2327                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2328                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2329                 else {
2330                         /*
2331                          * The 'ieee754_csr' is an alias of ctx->fcr31.
2332                          * No need to copy ctx->fcr31 to ieee754_csr.
2333                          */
2334                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2335                 }
2336
2337                 if (has_fpu)
2338                         break;
2339                 if (sig)
2340                         break;
2341
2342                 cond_resched();
2343         } while (xcp->cp0_epc > prevepc);
2344
2345         /* SIGILL indicates a non-fpu instruction */
2346         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2347                 /* but if EPC has advanced, then ignore it */
2348                 sig = 0;
2349
2350         return sig;
2351 }