arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/processor.h>
  49 #include <asm/fpu_emulator.h>
  50 #include <asm/fpu.h>
  51 #include <asm/mips-r2-to-r6-emul.h>
  52
  53 #include "ieee754.h"
  54
  55 /* Function which emulates a floating point instruction. */
  56
  57 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  58         mips_instruction);
  59
  60 static int fpux_emu(struct pt_regs *,
  61         struct mips_fpu_struct *, mips_instruction, void *__user *);
  62
  63 /* Control registers */
  64
  65 #define FPCREG_RID      0       /* $0  = revision id */
  66 #define FPCREG_CSR      31      /* $31 = csr */
  67
  68 /* convert condition code register number to csr bit */
  69 const unsigned int fpucondbit[8] = {
  70         FPU_CSR_COND0,
  71         FPU_CSR_COND1,
  72         FPU_CSR_COND2,
  73         FPU_CSR_COND3,
  74         FPU_CSR_COND4,
  75         FPU_CSR_COND5,
  76         FPU_CSR_COND6,
  77         FPU_CSR_COND7
  78 };
  79
  80 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  81 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  82 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  83 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  84 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  85
  86 /*
  87  * This functions translates a 32-bit microMIPS instruction
  88  * into a 32-bit MIPS32 instruction. Returns 0 on success
  89  * and SIGILL otherwise.
  90  */
  91 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  92 {
  93         union mips_instruction insn = *insn_ptr;
  94         union mips_instruction mips32_insn = insn;
  95         int func, fmt, op;
  96
  97         switch (insn.mm_i_format.opcode) {
  98         case mm_ldc132_op:
  99                 mips32_insn.mm_i_format.opcode = ldc1_op;
 100                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 101                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 102                 break;
 103         case mm_lwc132_op:
 104                 mips32_insn.mm_i_format.opcode = lwc1_op;
 105                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 106                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 107                 break;
 108         case mm_sdc132_op:
 109                 mips32_insn.mm_i_format.opcode = sdc1_op;
 110                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 111                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 112                 break;
 113         case mm_swc132_op:
 114                 mips32_insn.mm_i_format.opcode = swc1_op;
 115                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 116                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 117                 break;
 118         case mm_pool32i_op:
 119                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 120                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 121                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 122                         mips32_insn.fb_format.opcode = cop1_op;
 123                         mips32_insn.fb_format.bc = bc_op;
 124                         mips32_insn.fb_format.flag =
 125                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 126                 } else
 127                         return SIGILL;
 128                 break;
 129         case mm_pool32f_op:
 130                 switch (insn.mm_fp0_format.func) {
 131                 case mm_32f_01_op:
 132                 case mm_32f_11_op:
 133                 case mm_32f_02_op:
 134                 case mm_32f_12_op:
 135                 case mm_32f_41_op:
 136                 case mm_32f_51_op:
 137                 case mm_32f_42_op:
 138                 case mm_32f_52_op:
 139                         op = insn.mm_fp0_format.func;
 140                         if (op == mm_32f_01_op)
 141                                 func = madd_s_op;
 142                         else if (op == mm_32f_11_op)
 143                                 func = madd_d_op;
 144                         else if (op == mm_32f_02_op)
 145                                 func = nmadd_s_op;
 146                         else if (op == mm_32f_12_op)
 147                                 func = nmadd_d_op;
 148                         else if (op == mm_32f_41_op)
 149                                 func = msub_s_op;
 150                         else if (op == mm_32f_51_op)
 151                                 func = msub_d_op;
 152                         else if (op == mm_32f_42_op)
 153                                 func = nmsub_s_op;
 154                         else
 155                                 func = nmsub_d_op;
 156                         mips32_insn.fp6_format.opcode = cop1x_op;
 157                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 158                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 159                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 160                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 161                         mips32_insn.fp6_format.func = func;
 162                         break;
 163                 case mm_32f_10_op:
 164                         func = -1;      /* Invalid */
 165                         op = insn.mm_fp5_format.op & 0x7;
 166                         if (op == mm_ldxc1_op)
 167                                 func = ldxc1_op;
 168                         else if (op == mm_sdxc1_op)
 169                                 func = sdxc1_op;
 170                         else if (op == mm_lwxc1_op)
 171                                 func = lwxc1_op;
 172                         else if (op == mm_swxc1_op)
 173                                 func = swxc1_op;
 174
 175                         if (func != -1) {
 176                                 mips32_insn.r_format.opcode = cop1x_op;
 177                                 mips32_insn.r_format.rs =
 178                                         insn.mm_fp5_format.base;
 179                                 mips32_insn.r_format.rt =
 180                                         insn.mm_fp5_format.index;
 181                                 mips32_insn.r_format.rd = 0;
 182                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 183                                 mips32_insn.r_format.func = func;
 184                         } else
 185                                 return SIGILL;
 186                         break;
 187                 case mm_32f_40_op:
 188                         op = -1;        /* Invalid */
 189                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 190                                 op = 1;
 191                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 192                                 op = 0;
 193                         if (op != -1) {
 194                                 mips32_insn.fp0_format.opcode = cop1_op;
 195                                 mips32_insn.fp0_format.fmt =
 196                                         sdps_format[insn.mm_fp2_format.fmt];
 197                                 mips32_insn.fp0_format.ft =
 198                                         (insn.mm_fp2_format.cc<<2) + op;
 199                                 mips32_insn.fp0_format.fs =
 200                                         insn.mm_fp2_format.fs;
 201                                 mips32_insn.fp0_format.fd =
 202                                         insn.mm_fp2_format.fd;
 203                                 mips32_insn.fp0_format.func = fmovc_op;
 204                         } else
 205                                 return SIGILL;
 206                         break;
 207                 case mm_32f_60_op:
 208                         func = -1;      /* Invalid */
 209                         if (insn.mm_fp0_format.op == mm_fadd_op)
 210                                 func = fadd_op;
 211                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 212                                 func = fsub_op;
 213                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 214                                 func = fmul_op;
 215                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 216                                 func = fdiv_op;
 217                         if (func != -1) {
 218                                 mips32_insn.fp0_format.opcode = cop1_op;
 219                                 mips32_insn.fp0_format.fmt =
 220                                         sdps_format[insn.mm_fp0_format.fmt];
 221                                 mips32_insn.fp0_format.ft =
 222                                         insn.mm_fp0_format.ft;
 223                                 mips32_insn.fp0_format.fs =
 224                                         insn.mm_fp0_format.fs;
 225                                 mips32_insn.fp0_format.fd =
 226                                         insn.mm_fp0_format.fd;
 227                                 mips32_insn.fp0_format.func = func;
 228                         } else
 229                                 return SIGILL;
 230                         break;
 231                 case mm_32f_70_op:
 232                         func = -1;      /* Invalid */
 233                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 234                                 func = fmovn_op;
 235                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 236                                 func = fmovz_op;
 237                         if (func != -1) {
 238                                 mips32_insn.fp0_format.opcode = cop1_op;
 239                                 mips32_insn.fp0_format.fmt =
 240                                         sdps_format[insn.mm_fp0_format.fmt];
 241                                 mips32_insn.fp0_format.ft =
 242                                         insn.mm_fp0_format.ft;
 243                                 mips32_insn.fp0_format.fs =
 244                                         insn.mm_fp0_format.fs;
 245                                 mips32_insn.fp0_format.fd =
 246                                         insn.mm_fp0_format.fd;
 247                                 mips32_insn.fp0_format.func = func;
 248                         } else
 249                                 return SIGILL;
 250                         break;
 251                 case mm_32f_73_op:    /* POOL32FXF */
 252                         switch (insn.mm_fp1_format.op) {
 253                         case mm_movf0_op:
 254                         case mm_movf1_op:
 255                         case mm_movt0_op:
 256                         case mm_movt1_op:
 257                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 258                                     mm_movf0_op)
 259                                         op = 0;
 260                                 else
 261                                         op = 1;
 262                                 mips32_insn.r_format.opcode = spec_op;
 263                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 264                                 mips32_insn.r_format.rt =
 265                                         (insn.mm_fp4_format.cc << 2) + op;
 266                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 267                                 mips32_insn.r_format.re = 0;
 268                                 mips32_insn.r_format.func = movc_op;
 269                                 break;
 270                         case mm_fcvtd0_op:
 271                         case mm_fcvtd1_op:
 272                         case mm_fcvts0_op:
 273                         case mm_fcvts1_op:
 274                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 275                                     mm_fcvtd0_op) {
 276                                         func = fcvtd_op;
 277                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 278                                 } else {
 279                                         func = fcvts_op;
 280                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 281                                 }
 282                                 mips32_insn.fp0_format.opcode = cop1_op;
 283                                 mips32_insn.fp0_format.fmt = fmt;
 284                                 mips32_insn.fp0_format.ft = 0;
 285                                 mips32_insn.fp0_format.fs =
 286                                         insn.mm_fp3_format.fs;
 287                                 mips32_insn.fp0_format.fd =
 288                                         insn.mm_fp3_format.rt;
 289                                 mips32_insn.fp0_format.func = func;
 290                                 break;
 291                         case mm_fmov0_op:
 292                         case mm_fmov1_op:
 293                         case mm_fabs0_op:
 294                         case mm_fabs1_op:
 295                         case mm_fneg0_op:
 296                         case mm_fneg1_op:
 297                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 298                                     mm_fmov0_op)
 299                                         func = fmov_op;
 300                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 301                                          mm_fabs0_op)
 302                                         func = fabs_op;
 303                                 else
 304                                         func = fneg_op;
 305                                 mips32_insn.fp0_format.opcode = cop1_op;
 306                                 mips32_insn.fp0_format.fmt =
 307                                         sdps_format[insn.mm_fp3_format.fmt];
 308                                 mips32_insn.fp0_format.ft = 0;
 309                                 mips32_insn.fp0_format.fs =
 310                                         insn.mm_fp3_format.fs;
 311                                 mips32_insn.fp0_format.fd =
 312                                         insn.mm_fp3_format.rt;
 313                                 mips32_insn.fp0_format.func = func;
 314                                 break;
 315                         case mm_ffloorl_op:
 316                         case mm_ffloorw_op:
 317                         case mm_fceill_op:
 318                         case mm_fceilw_op:
 319                         case mm_ftruncl_op:
 320                         case mm_ftruncw_op:
 321                         case mm_froundl_op:
 322                         case mm_froundw_op:
 323                         case mm_fcvtl_op:
 324                         case mm_fcvtw_op:
 325                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 326                                         func = ffloorl_op;
 327                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 328                                         func = ffloor_op;
 329                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 330                                         func = fceill_op;
 331                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 332                                         func = fceil_op;
 333                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 334                                         func = ftruncl_op;
 335                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 336                                         func = ftrunc_op;
 337                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 338                                         func = froundl_op;
 339                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 340                                         func = fround_op;
 341                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 342                                         func = fcvtl_op;
 343                                 else
 344                                         func = fcvtw_op;
 345                                 mips32_insn.fp0_format.opcode = cop1_op;
 346                                 mips32_insn.fp0_format.fmt =
 347                                         sd_format[insn.mm_fp1_format.fmt];
 348                                 mips32_insn.fp0_format.ft = 0;
 349                                 mips32_insn.fp0_format.fs =
 350                                         insn.mm_fp1_format.fs;
 351                                 mips32_insn.fp0_format.fd =
 352                                         insn.mm_fp1_format.rt;
 353                                 mips32_insn.fp0_format.func = func;
 354                                 break;
 355                         case mm_frsqrt_op:
 356                         case mm_fsqrt_op:
 357                         case mm_frecip_op:
 358                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 359                                         func = frsqrt_op;
 360                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 361                                         func = fsqrt_op;
 362                                 else
 363                                         func = frecip_op;
 364                                 mips32_insn.fp0_format.opcode = cop1_op;
 365                                 mips32_insn.fp0_format.fmt =
 366                                         sdps_format[insn.mm_fp1_format.fmt];
 367                                 mips32_insn.fp0_format.ft = 0;
 368                                 mips32_insn.fp0_format.fs =
 369                                         insn.mm_fp1_format.fs;
 370                                 mips32_insn.fp0_format.fd =
 371                                         insn.mm_fp1_format.rt;
 372                                 mips32_insn.fp0_format.func = func;
 373                                 break;
 374                         case mm_mfc1_op:
 375                         case mm_mtc1_op:
 376                         case mm_cfc1_op:
 377                         case mm_ctc1_op:
 378                         case mm_mfhc1_op:
 379                         case mm_mthc1_op:
 380                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 381                                         op = mfc_op;
 382                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 383                                         op = mtc_op;
 384                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 385                                         op = cfc_op;
 386                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 387                                         op = ctc_op;
 388                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 389                                         op = mfhc_op;
 390                                 else
 391                                         op = mthc_op;
 392                                 mips32_insn.fp1_format.opcode = cop1_op;
 393                                 mips32_insn.fp1_format.op = op;
 394                                 mips32_insn.fp1_format.rt =
 395                                         insn.mm_fp1_format.rt;
 396                                 mips32_insn.fp1_format.fs =
 397                                         insn.mm_fp1_format.fs;
 398                                 mips32_insn.fp1_format.fd = 0;
 399                                 mips32_insn.fp1_format.func = 0;
 400                                 break;
 401                         default:
 402                                 return SIGILL;
 403                         }
 404                         break;
 405                 case mm_32f_74_op:      /* c.cond.fmt */
 406                         mips32_insn.fp0_format.opcode = cop1_op;
 407                         mips32_insn.fp0_format.fmt =
 408                                 sdps_format[insn.mm_fp4_format.fmt];
 409                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 410                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 411                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 412                         mips32_insn.fp0_format.func =
 413                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 414                         break;
 415                 default:
 416                         return SIGILL;
 417                 }
 418                 break;
 419         default:
 420                 return SIGILL;
 421         }
 422
 423         *insn_ptr = mips32_insn;
 424         return 0;
 425 }
 426
 427 /*
 428  * Redundant with logic already in kernel/branch.c,
 429  * embedded in compute_return_epc.  At some point,
 430  * a single subroutine should be used across both
 431  * modules.
 432  */
 433 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 434                          unsigned long *contpc)
 435 {
 436         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 437         unsigned int fcr31;
 438         unsigned int bit = 0;
 439
 440         switch (insn.i_format.opcode) {
 441         case spec_op:
 442                 switch (insn.r_format.func) {
 443                 case jalr_op:
 444                         regs->regs[insn.r_format.rd] =
 445                                 regs->cp0_epc + dec_insn.pc_inc +
 446                                 dec_insn.next_pc_inc;
 447                         /* Fall through */
 448                 case jr_op:
 449                         /* For R6, JR already emulated in jalr_op */
 450                         if (NO_R6EMU && insn.r_format.opcode == jr_op)
 451                                 break;
 452                         *contpc = regs->regs[insn.r_format.rs];
 453                         return 1;
 454                 }
 455                 break;
 456         case bcond_op:
 457                 switch (insn.i_format.rt) {
 458                 case bltzal_op:
 459                 case bltzall_op:
 460                         if (NO_R6EMU && (insn.i_format.rs ||
 461                             insn.i_format.rt == bltzall_op))
 462                                 break;
 463
 464                         regs->regs[31] = regs->cp0_epc +
 465                                 dec_insn.pc_inc +
 466                                 dec_insn.next_pc_inc;
 467                         /* Fall through */
 468                 case bltzl_op:
 469                         if (NO_R6EMU)
 470                                 break;
 471                 case bltz_op:
 472                         if ((long)regs->regs[insn.i_format.rs] < 0)
 473                                 *contpc = regs->cp0_epc +
 474                                         dec_insn.pc_inc +
 475                                         (insn.i_format.simmediate << 2);
 476                         else
 477                                 *contpc = regs->cp0_epc +
 478                                         dec_insn.pc_inc +
 479                                         dec_insn.next_pc_inc;
 480                         return 1;
 481                 case bgezal_op:
 482                 case bgezall_op:
 483                         if (NO_R6EMU && (insn.i_format.rs ||
 484                             insn.i_format.rt == bgezall_op))
 485                                 break;
 486
 487                         regs->regs[31] = regs->cp0_epc +
 488                                 dec_insn.pc_inc +
 489                                 dec_insn.next_pc_inc;
 490                         /* Fall through */
 491                 case bgezl_op:
 492                         if (NO_R6EMU)
 493                                 break;
 494                 case bgez_op:
 495                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 496                                 *contpc = regs->cp0_epc +
 497                                         dec_insn.pc_inc +
 498                                         (insn.i_format.simmediate << 2);
 499                         else
 500                                 *contpc = regs->cp0_epc +
 501                                         dec_insn.pc_inc +
 502                                         dec_insn.next_pc_inc;
 503                         return 1;
 504                 }
 505                 break;
 506         case jalx_op:
 507                 set_isa16_mode(bit);
 508         case jal_op:
 509                 regs->regs[31] = regs->cp0_epc +
 510                         dec_insn.pc_inc +
 511                         dec_insn.next_pc_inc;
 512                 /* Fall through */
 513         case j_op:
 514                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 515                 *contpc >>= 28;
 516                 *contpc <<= 28;
 517                 *contpc |= (insn.j_format.target << 2);
 518                 /* Set microMIPS mode bit: XOR for jalx. */
 519                 *contpc ^= bit;
 520                 return 1;
 521         case beql_op:
 522                 if (NO_R6EMU)
 523                         break;
 524         case beq_op:
 525                 if (regs->regs[insn.i_format.rs] ==
 526                     regs->regs[insn.i_format.rt])
 527                         *contpc = regs->cp0_epc +
 528                                 dec_insn.pc_inc +
 529                                 (insn.i_format.simmediate << 2);
 530                 else
 531                         *contpc = regs->cp0_epc +
 532                                 dec_insn.pc_inc +
 533                                 dec_insn.next_pc_inc;
 534                 return 1;
 535         case bnel_op:
 536                 if (NO_R6EMU)
 537                         break;
 538         case bne_op:
 539                 if (regs->regs[insn.i_format.rs] !=
 540                     regs->regs[insn.i_format.rt])
 541                         *contpc = regs->cp0_epc +
 542                                 dec_insn.pc_inc +
 543                                 (insn.i_format.simmediate << 2);
 544                 else
 545                         *contpc = regs->cp0_epc +
 546                                 dec_insn.pc_inc +
 547                                 dec_insn.next_pc_inc;
 548                 return 1;
 549         case blezl_op:
 550                 if (NO_R6EMU)
 551                         break;
 552         case blez_op:
 553
 554                 /*
 555                  * Compact branches for R6 for the
 556                  * blez and blezl opcodes.
 557                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
 558                  * BLEZ  | rs = rt != 0      == BGEZALC
 559                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
 560                  * BLEZL | rs = 0 | rt != 0  == BLEZC
 561                  * BLEZL | rs = rt != 0      == BGEZC
 562                  * BLEZL | rs != 0 | rt != 0 == BGEC
 563                  *
 564                  * For real BLEZ{,L}, rt is always 0.
 565                  */
 566                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 567                         if ((insn.i_format.opcode == blez_op) &&
 568                             ((!insn.i_format.rs && insn.i_format.rt) ||
 569                              (insn.i_format.rs == insn.i_format.rt)))
 570                                 regs->regs[31] = regs->cp0_epc +
 571                                         dec_insn.pc_inc;
 572                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 573                                 dec_insn.next_pc_inc;
 574
 575                         return 1;
 576                 }
 577                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 578                         *contpc = regs->cp0_epc +
 579                                 dec_insn.pc_inc +
 580                                 (insn.i_format.simmediate << 2);
 581                 else
 582                         *contpc = regs->cp0_epc +
 583                                 dec_insn.pc_inc +
 584                                 dec_insn.next_pc_inc;
 585                 return 1;
 586         case bgtzl_op:
 587                 if (NO_R6EMU)
 588                         break;
 589         case bgtz_op:
 590                 /*
 591                  * Compact branches for R6 for the
 592                  * bgtz and bgtzl opcodes.
 593                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
 594                  * BGTZ  | rs = rt != 0      == BLTZALC
 595                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
 596                  * BGTZL | rs = 0 | rt != 0  == BGTZC
 597                  * BGTZL | rs = rt != 0      == BLTZC
 598                  * BGTZL | rs != 0 | rt != 0 == BLTC
 599                  *
 600                  * *ZALC varint for BGTZ &&& rt != 0
 601                  * For real GTZ{,L}, rt is always 0.
 602                  */
 603                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 604                         if ((insn.i_format.opcode == blez_op) &&
 605                             ((!insn.i_format.rs && insn.i_format.rt) ||
 606                              (insn.i_format.rs == insn.i_format.rt)))
 607                                 regs->regs[31] = regs->cp0_epc +
 608                                         dec_insn.pc_inc;
 609                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 610                                 dec_insn.next_pc_inc;
 611
 612                         return 1;
 613                 }
 614
 615                 if ((long)regs->regs[insn.i_format.rs] > 0)
 616                         *contpc = regs->cp0_epc +
 617                                 dec_insn.pc_inc +
 618                                 (insn.i_format.simmediate << 2);
 619                 else
 620                         *contpc = regs->cp0_epc +
 621                                 dec_insn.pc_inc +
 622                                 dec_insn.next_pc_inc;
 623                 return 1;
 624         case cbcond0_op:
 625         case cbcond1_op:
 626                 if (!cpu_has_mips_r6)
 627                         break;
 628                 if (insn.i_format.rt && !insn.i_format.rs)
 629                         regs->regs[31] = regs->cp0_epc + 4;
 630                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 631                         dec_insn.next_pc_inc;
 632
 633                 return 1;
 634 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 635         case lwc2_op: /* This is bbit0 on Octeon */
 636                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 637                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 638                 else
 639                         *contpc = regs->cp0_epc + 8;
 640                 return 1;
 641         case ldc2_op: /* This is bbit032 on Octeon */
 642                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 643                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 644                 else
 645                         *contpc = regs->cp0_epc + 8;
 646                 return 1;
 647         case swc2_op: /* This is bbit1 on Octeon */
 648                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 649                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 650                 else
 651                         *contpc = regs->cp0_epc + 8;
 652                 return 1;
 653         case sdc2_op: /* This is bbit132 on Octeon */
 654                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 655                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 656                 else
 657                         *contpc = regs->cp0_epc + 8;
 658                 return 1;
 659 #else
 660         case bc6_op:
 661                 /*
 662                  * Only valid for MIPS R6 but we can still end up
 663                  * here from a broken userland so just tell emulator
 664                  * this is not a branch and let it break later on.
 665                  */
 666                 if  (!cpu_has_mips_r6)
 667                         break;
 668                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 669                         dec_insn.next_pc_inc;
 670
 671                 return 1;
 672         case balc6_op:
 673                 if (!cpu_has_mips_r6)
 674                         break;
 675                 regs->regs[31] = regs->cp0_epc + 4;
 676                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 677                         dec_insn.next_pc_inc;
 678
 679                 return 1;
 680         case beqzcjic_op:
 681                 if (!cpu_has_mips_r6)
 682                         break;
 683                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 684                         dec_insn.next_pc_inc;
 685
 686                 return 1;
 687         case bnezcjialc_op:
 688                 if (!cpu_has_mips_r6)
 689                         break;
 690                 if (!insn.i_format.rs)
 691                         regs->regs[31] = regs->cp0_epc + 4;
 692                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 693                         dec_insn.next_pc_inc;
 694
 695                 return 1;
 696 #endif
 697         case cop0_op:
 698         case cop1_op:
 699                 /* Need to check for R6 bc1nez and bc1eqz branches */
 700                 if (cpu_has_mips_r6 &&
 701                     ((insn.i_format.rs == bc1eqz_op) ||
 702                      (insn.i_format.rs == bc1nez_op))) {
 703                         bit = 0;
 704                         switch (insn.i_format.rs) {
 705                         case bc1eqz_op:
 706                                 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
 707                                     bit = 1;
 708                                 break;
 709                         case bc1nez_op:
 710                                 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
 711                                     bit = 1;
 712                                 break;
 713                         }
 714                         if (bit)
 715                                 *contpc = regs->cp0_epc +
 716                                         dec_insn.pc_inc +
 717                                         (insn.i_format.simmediate << 2);
 718                         else
 719                                 *contpc = regs->cp0_epc +
 720                                         dec_insn.pc_inc +
 721                                         dec_insn.next_pc_inc;
 722
 723                         return 1;
 724                 }
 725                 /* R2/R6 compatible cop1 instruction. Fall through */
 726         case cop2_op:
 727         case cop1x_op:
 728                 if (insn.i_format.rs == bc_op) {
 729                         preempt_disable();
 730                         if (is_fpu_owner())
 731                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 732                         else
 733                                 fcr31 = current->thread.fpu.fcr31;
 734                         preempt_enable();
 735
 736                         bit = (insn.i_format.rt >> 2);
 737                         bit += (bit != 0);
 738                         bit += 23;
 739                         switch (insn.i_format.rt & 3) {
 740                         case 0: /* bc1f */
 741                         case 2: /* bc1fl */
 742                                 if (~fcr31 & (1 << bit))
 743                                         *contpc = regs->cp0_epc +
 744                                                 dec_insn.pc_inc +
 745                                                 (insn.i_format.simmediate << 2);
 746                                 else
 747                                         *contpc = regs->cp0_epc +
 748                                                 dec_insn.pc_inc +
 749                                                 dec_insn.next_pc_inc;
 750                                 return 1;
 751                         case 1: /* bc1t */
 752                         case 3: /* bc1tl */
 753                                 if (fcr31 & (1 << bit))
 754                                         *contpc = regs->cp0_epc +
 755                                                 dec_insn.pc_inc +
 756                                                 (insn.i_format.simmediate << 2);
 757                                 else
 758                                         *contpc = regs->cp0_epc +
 759                                                 dec_insn.pc_inc +
 760                                                 dec_insn.next_pc_inc;
 761                                 return 1;
 762                         }
 763                 }
 764                 break;
 765         }
 766         return 0;
 767 }
 768
 769 /*
 770  * In the Linux kernel, we support selection of FPR format on the
 771  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 772  * is hardwired to zero, which would imply a 32-bit FPU even for
 773  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 774  * FPU emu is slow and bulky and optimizing this function offers fairly
 775  * sizeable benefits so we try to be clever and make this function return
 776  * a constant whenever possible, that is on 64-bit kernels without O32
 777  * compatibility enabled and on 32-bit without 64-bit FPU support.
 778  */
 779 static inline int cop1_64bit(struct pt_regs *xcp)
 780 {
 781         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 782                 return 1;
 783         else if (config_enabled(CONFIG_32BIT) &&
 784                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 785                 return 0;
 786
 787         return !test_thread_flag(TIF_32BIT_FPREGS);
 788 }
 789
 790 static inline bool hybrid_fprs(void)
 791 {
 792         return test_thread_flag(TIF_HYBRID_FPREGS);
 793 }
 794
 795 #define SIFROMREG(si, x)                                                \
 796 do {                                                                    \
 797         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 798                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 799         else                                                            \
 800                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 801 } while (0)
 802
 803 #define SITOREG(si, x)                                                  \
 804 do {                                                                    \
 805         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 806                 unsigned i;                                             \
 807                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 808                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 809                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 810         } else {                                                        \
 811                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 812         }                                                               \
 813 } while (0)
 814
 815 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 816
 817 #define SITOHREG(si, x)                                                 \
 818 do {                                                                    \
 819         unsigned i;                                                     \
 820         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 821         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 822                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 823 } while (0)
 824
 825 #define DIFROMREG(di, x)                                                \
 826         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 827
 828 #define DITOREG(di, x)                                                  \
 829 do {                                                                    \
 830         unsigned fpr, i;                                                \
 831         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 832         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 833         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 834                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 835 } while (0)
 836
 837 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 838 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 839 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 840 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 841
 842 /*
 843  * Emulate a CFC1 instruction.
 844  */
 845 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 846                             mips_instruction ir)
 847 {
 848         u32 value;
 849
 850         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 851                 value = ctx->fcr31;
 852                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 853                          (void *)xcp->cp0_epc,
 854                          MIPSInst_RT(ir), value);
 855         } else if (MIPSInst_RD(ir) == FPCREG_RID)
 856                 value = 0;
 857         else
 858                 value = 0;
 859         if (MIPSInst_RT(ir))
 860                 xcp->regs[MIPSInst_RT(ir)] = value;
 861 }
 862
 863 /*
 864  * Emulate a CTC1 instruction.
 865  */
 866 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 867                             mips_instruction ir)
 868 {
 869         u32 value;
 870
 871         if (MIPSInst_RT(ir) == 0)
 872                 value = 0;
 873         else
 874                 value = xcp->regs[MIPSInst_RT(ir)];
 875
 876         /* we only have one writable control reg
 877          */
 878         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 879                 pr_debug("%p gpr[%d]->csr=%08x\n",
 880                          (void *)xcp->cp0_epc,
 881                          MIPSInst_RT(ir), value);
 882
 883                 /* Don't write reserved bits.  */
 884                 ctx->fcr31 = value & ~FPU_CSR_RSVD;
 885         }
 886 }
 887
 888 /*
 889  * Emulate the single floating point instruction pointed at by EPC.
 890  * Two instructions if the instruction is in a branch delay slot.
 891  */
 892
 893 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 894                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 895 {
 896         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 897         unsigned int cond, cbit;
 898         mips_instruction ir;
 899         int likely, pc_inc;
 900         u32 __user *wva;
 901         u64 __user *dva;
 902         u32 wval;
 903         u64 dval;
 904         int sig;
 905
 906         /*
 907          * These are giving gcc a gentle hint about what to expect in
 908          * dec_inst in order to do better optimization.
 909          */
 910         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 911                 unreachable();
 912
 913         /* XXX NEC Vr54xx bug workaround */
 914         if (delay_slot(xcp)) {
 915                 if (dec_insn.micro_mips_mode) {
 916                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 917                                 clear_delay_slot(xcp);
 918                 } else {
 919                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 920                                 clear_delay_slot(xcp);
 921                 }
 922         }
 923
 924         if (delay_slot(xcp)) {
 925                 /*
 926                  * The instruction to be emulated is in a branch delay slot
 927                  * which means that we have to  emulate the branch instruction
 928                  * BEFORE we do the cop1 instruction.
 929                  *
 930                  * This branch could be a COP1 branch, but in that case we
 931                  * would have had a trap for that instruction, and would not
 932                  * come through this route.
 933                  *
 934                  * Linux MIPS branch emulator operates on context, updating the
 935                  * cp0_epc.
 936                  */
 937                 ir = dec_insn.next_insn;  /* process delay slot instr */
 938                 pc_inc = dec_insn.next_pc_inc;
 939         } else {
 940                 ir = dec_insn.insn;       /* process current instr */
 941                 pc_inc = dec_insn.pc_inc;
 942         }
 943
 944         /*
 945          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 946          * instructions, we want to convert microMIPS FPU instructions
 947          * into MIPS32 instructions so that we could reuse all of the
 948          * FPU emulation code.
 949          *
 950          * NOTE: We cannot do this for branch instructions since they
 951          *       are not a subset. Example: Cannot emulate a 16-bit
 952          *       aligned target address with a MIPS32 instruction.
 953          */
 954         if (dec_insn.micro_mips_mode) {
 955                 /*
 956                  * If next instruction is a 16-bit instruction, then it
 957                  * it cannot be a FPU instruction. This could happen
 958                  * since we can be called for non-FPU instructions.
 959                  */
 960                 if ((pc_inc == 2) ||
 961                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 962                          == SIGILL))
 963                         return SIGILL;
 964         }
 965
 966 emul:
 967         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 968         MIPS_FPU_EMU_INC_STATS(emulated);
 969         switch (MIPSInst_OPCODE(ir)) {
 970         case ldc1_op:
 971                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 972                                      MIPSInst_SIMM(ir));
 973                 MIPS_FPU_EMU_INC_STATS(loads);
 974
 975                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
 976                         MIPS_FPU_EMU_INC_STATS(errors);
 977                         *fault_addr = dva;
 978                         return SIGBUS;
 979                 }
 980                 if (__get_user(dval, dva)) {
 981                         MIPS_FPU_EMU_INC_STATS(errors);
 982                         *fault_addr = dva;
 983                         return SIGSEGV;
 984                 }
 985                 DITOREG(dval, MIPSInst_RT(ir));
 986                 break;
 987
 988         case sdc1_op:
 989                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 990                                       MIPSInst_SIMM(ir));
 991                 MIPS_FPU_EMU_INC_STATS(stores);
 992                 DIFROMREG(dval, MIPSInst_RT(ir));
 993                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
 994                         MIPS_FPU_EMU_INC_STATS(errors);
 995                         *fault_addr = dva;
 996                         return SIGBUS;
 997                 }
 998                 if (__put_user(dval, dva)) {
 999                         MIPS_FPU_EMU_INC_STATS(errors);
1000                         *fault_addr = dva;
1001                         return SIGSEGV;
1002                 }
1003                 break;
1004
1005         case lwc1_op:
1006                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1007                                       MIPSInst_SIMM(ir));
1008                 MIPS_FPU_EMU_INC_STATS(loads);
1009                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1010                         MIPS_FPU_EMU_INC_STATS(errors);
1011                         *fault_addr = wva;
1012                         return SIGBUS;
1013                 }
1014                 if (__get_user(wval, wva)) {
1015                         MIPS_FPU_EMU_INC_STATS(errors);
1016                         *fault_addr = wva;
1017                         return SIGSEGV;
1018                 }
1019                 SITOREG(wval, MIPSInst_RT(ir));
1020                 break;
1021
1022         case swc1_op:
1023                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1024                                       MIPSInst_SIMM(ir));
1025                 MIPS_FPU_EMU_INC_STATS(stores);
1026                 SIFROMREG(wval, MIPSInst_RT(ir));
1027                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1028                         MIPS_FPU_EMU_INC_STATS(errors);
1029                         *fault_addr = wva;
1030                         return SIGBUS;
1031                 }
1032                 if (__put_user(wval, wva)) {
1033                         MIPS_FPU_EMU_INC_STATS(errors);
1034                         *fault_addr = wva;
1035                         return SIGSEGV;
1036                 }
1037                 break;
1038
1039         case cop1_op:
1040                 switch (MIPSInst_RS(ir)) {
1041                 case dmfc_op:
1042                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1043                                 return SIGILL;
1044
1045                         /* copregister fs -> gpr[rt] */
1046                         if (MIPSInst_RT(ir) != 0) {
1047                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1048                                         MIPSInst_RD(ir));
1049                         }
1050                         break;
1051
1052                 case dmtc_op:
1053                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1054                                 return SIGILL;
1055
1056                         /* copregister fs <- rt */
1057                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1058                         break;
1059
1060                 case mfhc_op:
1061                         if (!cpu_has_mips_r2)
1062                                 goto sigill;
1063
1064                         /* copregister rd -> gpr[rt] */
1065                         if (MIPSInst_RT(ir) != 0) {
1066                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1067                                         MIPSInst_RD(ir));
1068                         }
1069                         break;
1070
1071                 case mthc_op:
1072                         if (!cpu_has_mips_r2)
1073                                 goto sigill;
1074
1075                         /* copregister rd <- gpr[rt] */
1076                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1077                         break;
1078
1079                 case mfc_op:
1080                         /* copregister rd -> gpr[rt] */
1081                         if (MIPSInst_RT(ir) != 0) {
1082                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1083                                         MIPSInst_RD(ir));
1084                         }
1085                         break;
1086
1087                 case mtc_op:
1088                         /* copregister rd <- rt */
1089                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1090                         break;
1091
1092                 case cfc_op:
1093                         /* cop control register rd -> gpr[rt] */
1094                         cop1_cfc(xcp, ctx, ir);
1095                         break;
1096
1097                 case ctc_op:
1098                         /* copregister rd <- rt */
1099                         cop1_ctc(xcp, ctx, ir);
1100                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1101                                 return SIGFPE;
1102                         }
1103                         break;
1104
1105                 case bc_op:
1106                         if (delay_slot(xcp))
1107                                 return SIGILL;
1108
1109                         if (cpu_has_mips_4_5_r)
1110                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1111                         else
1112                                 cbit = FPU_CSR_COND;
1113                         cond = ctx->fcr31 & cbit;
1114
1115                         likely = 0;
1116                         switch (MIPSInst_RT(ir) & 3) {
1117                         case bcfl_op:
1118                                 if (cpu_has_mips_2_3_4_5_r)
1119                                         likely = 1;
1120                                 /* Fall through */
1121                         case bcf_op:
1122                                 cond = !cond;
1123                                 break;
1124                         case bctl_op:
1125                                 if (cpu_has_mips_2_3_4_5_r)
1126                                         likely = 1;
1127                                 /* Fall through */
1128                         case bct_op:
1129                                 break;
1130                         }
1131
1132                         set_delay_slot(xcp);
1133                         if (cond) {
1134                                 /*
1135                                  * Branch taken: emulate dslot instruction
1136                                  */
1137                                 unsigned long bcpc;
1138
1139                                 /*
1140                                  * Remember EPC at the branch to point back
1141                                  * at so that any delay-slot instruction
1142                                  * signal is not silently ignored.
1143                                  */
1144                                 bcpc = xcp->cp0_epc;
1145                                 xcp->cp0_epc += dec_insn.pc_inc;
1146
1147                                 contpc = MIPSInst_SIMM(ir);
1148                                 ir = dec_insn.next_insn;
1149                                 if (dec_insn.micro_mips_mode) {
1150                                         contpc = (xcp->cp0_epc + (contpc << 1));
1151
1152                                         /* If 16-bit instruction, not FPU. */
1153                                         if ((dec_insn.next_pc_inc == 2) ||
1154                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1155
1156                                                 /*
1157                                                  * Since this instruction will
1158                                                  * be put on the stack with
1159                                                  * 32-bit words, get around
1160                                                  * this problem by putting a
1161                                                  * NOP16 as the second one.
1162                                                  */
1163                                                 if (dec_insn.next_pc_inc == 2)
1164                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1165
1166                                                 /*
1167                                                  * Single step the non-CP1
1168                                                  * instruction in the dslot.
1169                                                  */
1170                                                 sig = mips_dsemul(xcp, ir,
1171                                                                   contpc);
1172                                                 if (sig)
1173                                                         xcp->cp0_epc = bcpc;
1174                                                 /*
1175                                                  * SIGILL forces out of
1176                                                  * the emulation loop.
1177                                                  */
1178                                                 return sig ? sig : SIGILL;
1179                                         }
1180                                 } else
1181                                         contpc = (xcp->cp0_epc + (contpc << 2));
1182
1183                                 switch (MIPSInst_OPCODE(ir)) {
1184                                 case lwc1_op:
1185                                 case swc1_op:
1186                                         goto emul;
1187
1188                                 case ldc1_op:
1189                                 case sdc1_op:
1190                                         if (cpu_has_mips_2_3_4_5_r)
1191                                                 goto emul;
1192
1193                                         goto bc_sigill;
1194
1195                                 case cop1_op:
1196                                         goto emul;
1197
1198                                 case cop1x_op:
1199                                         if (cpu_has_mips_4_5_64_r2_r6)
1200                                                 /* its one of ours */
1201                                                 goto emul;
1202
1203                                         goto bc_sigill;
1204
1205                                 case spec_op:
1206                                         switch (MIPSInst_FUNC(ir)) {
1207                                         case movc_op:
1208                                                 if (cpu_has_mips_4_5_r)
1209                                                         goto emul;
1210
1211                                                 goto bc_sigill;
1212                                         }
1213                                         break;
1214
1215                                 bc_sigill:
1216                                         xcp->cp0_epc = bcpc;
1217                                         return SIGILL;
1218                                 }
1219
1220                                 /*
1221                                  * Single step the non-cp1
1222                                  * instruction in the dslot
1223                                  */
1224                                 sig = mips_dsemul(xcp, ir, contpc);
1225                                 if (sig)
1226                                         xcp->cp0_epc = bcpc;
1227                                 /* SIGILL forces out of the emulation loop.  */
1228                                 return sig ? sig : SIGILL;
1229                         } else if (likely) {    /* branch not taken */
1230                                 /*
1231                                  * branch likely nullifies
1232                                  * dslot if not taken
1233                                  */
1234                                 xcp->cp0_epc += dec_insn.pc_inc;
1235                                 contpc += dec_insn.pc_inc;
1236                                 /*
1237                                  * else continue & execute
1238                                  * dslot as normal insn
1239                                  */
1240                         }
1241                         break;
1242
1243                 default:
1244                         if (!(MIPSInst_RS(ir) & 0x10))
1245                                 return SIGILL;
1246
1247                         /* a real fpu computation instruction */
1248                         if ((sig = fpu_emu(xcp, ctx, ir)))
1249                                 return sig;
1250                 }
1251                 break;
1252
1253         case cop1x_op:
1254                 if (!cpu_has_mips_4_5_64_r2_r6)
1255                         return SIGILL;
1256
1257                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1258                 if (sig)
1259                         return sig;
1260                 break;
1261
1262         case spec_op:
1263                 if (!cpu_has_mips_4_5_r)
1264                         return SIGILL;
1265
1266                 if (MIPSInst_FUNC(ir) != movc_op)
1267                         return SIGILL;
1268                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1269                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1270                         xcp->regs[MIPSInst_RD(ir)] =
1271                                 xcp->regs[MIPSInst_RS(ir)];
1272                 break;
1273         default:
1274 sigill:
1275                 return SIGILL;
1276         }
1277
1278         /* we did it !! */
1279         xcp->cp0_epc = contpc;
1280         clear_delay_slot(xcp);
1281
1282         return 0;
1283 }
1284
1285 /*
1286  * Conversion table from MIPS compare ops 48-63
1287  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1288  */
1289 static const unsigned char cmptab[8] = {
1290         0,                      /* cmp_0 (sig) cmp_sf */
1291         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1292         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1293         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1294         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1295         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1296         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1297         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1298 };
1299
1300
1301 /*
1302  * Additional MIPS4 instructions
1303  */
1304
1305 #define DEF3OP(name, p, f1, f2, f3)                                     \
1306 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1307         union ieee754##p s, union ieee754##p t)                         \
1308 {                                                                       \
1309         struct _ieee754_csr ieee754_csr_save;                           \
1310         s = f1(s, t);                                                   \
1311         ieee754_csr_save = ieee754_csr;                                 \
1312         s = f2(s, r);                                                   \
1313         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1314         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1315         s = f3(s);                                                      \
1316         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1317         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1318         return s;                                                       \
1319 }
1320
1321 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1322 {
1323         return ieee754dp_div(ieee754dp_one(0), d);
1324 }
1325
1326 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1327 {
1328         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1329 }
1330
1331 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1332 {
1333         return ieee754sp_div(ieee754sp_one(0), s);
1334 }
1335
1336 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1337 {
1338         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1339 }
1340
1341 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1342 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1343 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1344 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1345 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1346 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1347 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1348 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1349
1350 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1351         mips_instruction ir, void *__user *fault_addr)
1352 {
1353         unsigned rcsr = 0;      /* resulting csr */
1354
1355         MIPS_FPU_EMU_INC_STATS(cp1xops);
1356
1357         switch (MIPSInst_FMA_FFMT(ir)) {
1358         case s_fmt:{            /* 0 */
1359
1360                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1361                 union ieee754sp fd, fr, fs, ft;
1362                 u32 __user *va;
1363                 u32 val;
1364
1365                 switch (MIPSInst_FUNC(ir)) {
1366                 case lwxc1_op:
1367                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1368                                 xcp->regs[MIPSInst_FT(ir)]);
1369
1370                         MIPS_FPU_EMU_INC_STATS(loads);
1371                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1372                                 MIPS_FPU_EMU_INC_STATS(errors);
1373                                 *fault_addr = va;
1374                                 return SIGBUS;
1375                         }
1376                         if (__get_user(val, va)) {
1377                                 MIPS_FPU_EMU_INC_STATS(errors);
1378                                 *fault_addr = va;
1379                                 return SIGSEGV;
1380                         }
1381                         SITOREG(val, MIPSInst_FD(ir));
1382                         break;
1383
1384                 case swxc1_op:
1385                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1386                                 xcp->regs[MIPSInst_FT(ir)]);
1387
1388                         MIPS_FPU_EMU_INC_STATS(stores);
1389
1390                         SIFROMREG(val, MIPSInst_FS(ir));
1391                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1392                                 MIPS_FPU_EMU_INC_STATS(errors);
1393                                 *fault_addr = va;
1394                                 return SIGBUS;
1395                         }
1396                         if (put_user(val, va)) {
1397                                 MIPS_FPU_EMU_INC_STATS(errors);
1398                                 *fault_addr = va;
1399                                 return SIGSEGV;
1400                         }
1401                         break;
1402
1403                 case madd_s_op:
1404                         handler = fpemu_sp_madd;
1405                         goto scoptop;
1406                 case msub_s_op:
1407                         handler = fpemu_sp_msub;
1408                         goto scoptop;
1409                 case nmadd_s_op:
1410                         handler = fpemu_sp_nmadd;
1411                         goto scoptop;
1412                 case nmsub_s_op:
1413                         handler = fpemu_sp_nmsub;
1414                         goto scoptop;
1415
1416                       scoptop:
1417                         SPFROMREG(fr, MIPSInst_FR(ir));
1418                         SPFROMREG(fs, MIPSInst_FS(ir));
1419                         SPFROMREG(ft, MIPSInst_FT(ir));
1420                         fd = (*handler) (fr, fs, ft);
1421                         SPTOREG(fd, MIPSInst_FD(ir));
1422
1423                       copcsr:
1424                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1425                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1426                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1427                         }
1428                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1429                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1430                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1431                         }
1432                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1433                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1434                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1435                         }
1436                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1437                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1438                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1439                         }
1440
1441                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1442                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1443                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1444                                    ctx->fcr31); */
1445                                 return SIGFPE;
1446                         }
1447
1448                         break;
1449
1450                 default:
1451                         return SIGILL;
1452                 }
1453                 break;
1454         }
1455
1456         case d_fmt:{            /* 1 */
1457                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1458                 union ieee754dp fd, fr, fs, ft;
1459                 u64 __user *va;
1460                 u64 val;
1461
1462                 switch (MIPSInst_FUNC(ir)) {
1463                 case ldxc1_op:
1464                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1465                                 xcp->regs[MIPSInst_FT(ir)]);
1466
1467                         MIPS_FPU_EMU_INC_STATS(loads);
1468                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1469                                 MIPS_FPU_EMU_INC_STATS(errors);
1470                                 *fault_addr = va;
1471                                 return SIGBUS;
1472                         }
1473                         if (__get_user(val, va)) {
1474                                 MIPS_FPU_EMU_INC_STATS(errors);
1475                                 *fault_addr = va;
1476                                 return SIGSEGV;
1477                         }
1478                         DITOREG(val, MIPSInst_FD(ir));
1479                         break;
1480
1481                 case sdxc1_op:
1482                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1483                                 xcp->regs[MIPSInst_FT(ir)]);
1484
1485                         MIPS_FPU_EMU_INC_STATS(stores);
1486                         DIFROMREG(val, MIPSInst_FS(ir));
1487                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1488                                 MIPS_FPU_EMU_INC_STATS(errors);
1489                                 *fault_addr = va;
1490                                 return SIGBUS;
1491                         }
1492                         if (__put_user(val, va)) {
1493                                 MIPS_FPU_EMU_INC_STATS(errors);
1494                                 *fault_addr = va;
1495                                 return SIGSEGV;
1496                         }
1497                         break;
1498
1499                 case madd_d_op:
1500                         handler = fpemu_dp_madd;
1501                         goto dcoptop;
1502                 case msub_d_op:
1503                         handler = fpemu_dp_msub;
1504                         goto dcoptop;
1505                 case nmadd_d_op:
1506                         handler = fpemu_dp_nmadd;
1507                         goto dcoptop;
1508                 case nmsub_d_op:
1509                         handler = fpemu_dp_nmsub;
1510                         goto dcoptop;
1511
1512                       dcoptop:
1513                         DPFROMREG(fr, MIPSInst_FR(ir));
1514                         DPFROMREG(fs, MIPSInst_FS(ir));
1515                         DPFROMREG(ft, MIPSInst_FT(ir));
1516                         fd = (*handler) (fr, fs, ft);
1517                         DPTOREG(fd, MIPSInst_FD(ir));
1518                         goto copcsr;
1519
1520                 default:
1521                         return SIGILL;
1522                 }
1523                 break;
1524         }
1525
1526         case 0x3:
1527                 if (MIPSInst_FUNC(ir) != pfetch_op)
1528                         return SIGILL;
1529
1530                 /* ignore prefx operation */
1531                 break;
1532
1533         default:
1534                 return SIGILL;
1535         }
1536
1537         return 0;
1538 }
1539
1540
1541
1542 /*
1543  * Emulate a single COP1 arithmetic instruction.
1544  */
1545 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1546         mips_instruction ir)
1547 {
1548         int rfmt;               /* resulting format */
1549         unsigned rcsr = 0;      /* resulting csr */
1550         unsigned int oldrm;
1551         unsigned int cbit;
1552         unsigned cond;
1553         union {
1554                 union ieee754dp d;
1555                 union ieee754sp s;
1556                 int w;
1557                 s64 l;
1558         } rv;                   /* resulting value */
1559         u64 bits;
1560
1561         MIPS_FPU_EMU_INC_STATS(cp1ops);
1562         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1563         case s_fmt: {           /* 0 */
1564                 union {
1565                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1566                         union ieee754sp(*u) (union ieee754sp);
1567                 } handler;
1568                 union ieee754sp fs, ft;
1569
1570                 switch (MIPSInst_FUNC(ir)) {
1571                         /* binary ops */
1572                 case fadd_op:
1573                         handler.b = ieee754sp_add;
1574                         goto scopbop;
1575                 case fsub_op:
1576                         handler.b = ieee754sp_sub;
1577                         goto scopbop;
1578                 case fmul_op:
1579                         handler.b = ieee754sp_mul;
1580                         goto scopbop;
1581                 case fdiv_op:
1582                         handler.b = ieee754sp_div;
1583                         goto scopbop;
1584
1585                         /* unary  ops */
1586                 case fsqrt_op:
1587                         if (!cpu_has_mips_2_3_4_5_r)
1588                                 return SIGILL;
1589
1590                         handler.u = ieee754sp_sqrt;
1591                         goto scopuop;
1592
1593                 /*
1594                  * Note that on some MIPS IV implementations such as the
1595                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1596                  * achieve full IEEE-754 accuracy - however this emulator does.
1597                  */
1598                 case frsqrt_op:
1599                         if (!cpu_has_mips_4_5_64_r2_r6)
1600                                 return SIGILL;
1601
1602                         handler.u = fpemu_sp_rsqrt;
1603                         goto scopuop;
1604
1605                 case frecip_op:
1606                         if (!cpu_has_mips_4_5_64_r2_r6)
1607                                 return SIGILL;
1608
1609                         handler.u = fpemu_sp_recip;
1610                         goto scopuop;
1611
1612                 case fmovc_op:
1613                         if (!cpu_has_mips_4_5_r)
1614                                 return SIGILL;
1615
1616                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1617                         if (((ctx->fcr31 & cond) != 0) !=
1618                                 ((MIPSInst_FT(ir) & 1) != 0))
1619                                 return 0;
1620                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1621                         break;
1622
1623                 case fmovz_op:
1624                         if (!cpu_has_mips_4_5_r)
1625                                 return SIGILL;
1626
1627                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1628                                 return 0;
1629                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1630                         break;
1631
1632                 case fmovn_op:
1633                         if (!cpu_has_mips_4_5_r)
1634                                 return SIGILL;
1635
1636                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1637                                 return 0;
1638                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1639                         break;
1640
1641                 case fabs_op:
1642                         handler.u = ieee754sp_abs;
1643                         goto scopuop;
1644
1645                 case fneg_op:
1646                         handler.u = ieee754sp_neg;
1647                         goto scopuop;
1648
1649                 case fmov_op:
1650                         /* an easy one */
1651                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1652                         goto copcsr;
1653
1654                         /* binary op on handler */
1655 scopbop:
1656                         SPFROMREG(fs, MIPSInst_FS(ir));
1657                         SPFROMREG(ft, MIPSInst_FT(ir));
1658
1659                         rv.s = (*handler.b) (fs, ft);
1660                         goto copcsr;
1661 scopuop:
1662                         SPFROMREG(fs, MIPSInst_FS(ir));
1663                         rv.s = (*handler.u) (fs);
1664                         goto copcsr;
1665 copcsr:
1666                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1667                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1668                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1669                         }
1670                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1671                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1672                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1673                         }
1674                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1675                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1676                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1677                         }
1678                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1679                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1680                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1681                         }
1682                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1683                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1684                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1685                         }
1686                         break;
1687
1688                         /* unary conv ops */
1689                 case fcvts_op:
1690                         return SIGILL;  /* not defined */
1691
1692                 case fcvtd_op:
1693                         SPFROMREG(fs, MIPSInst_FS(ir));
1694                         rv.d = ieee754dp_fsp(fs);
1695                         rfmt = d_fmt;
1696                         goto copcsr;
1697
1698                 case fcvtw_op:
1699                         SPFROMREG(fs, MIPSInst_FS(ir));
1700                         rv.w = ieee754sp_tint(fs);
1701                         rfmt = w_fmt;
1702                         goto copcsr;
1703
1704                 case fround_op:
1705                 case ftrunc_op:
1706                 case fceil_op:
1707                 case ffloor_op:
1708                         if (!cpu_has_mips_2_3_4_5_r)
1709                                 return SIGILL;
1710
1711                         oldrm = ieee754_csr.rm;
1712                         SPFROMREG(fs, MIPSInst_FS(ir));
1713                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1714                         rv.w = ieee754sp_tint(fs);
1715                         ieee754_csr.rm = oldrm;
1716                         rfmt = w_fmt;
1717                         goto copcsr;
1718
1719                 case fcvtl_op:
1720                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1721                                 return SIGILL;
1722
1723                         SPFROMREG(fs, MIPSInst_FS(ir));
1724                         rv.l = ieee754sp_tlong(fs);
1725                         rfmt = l_fmt;
1726                         goto copcsr;
1727
1728                 case froundl_op:
1729                 case ftruncl_op:
1730                 case fceill_op:
1731                 case ffloorl_op:
1732                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1733                                 return SIGILL;
1734
1735                         oldrm = ieee754_csr.rm;
1736                         SPFROMREG(fs, MIPSInst_FS(ir));
1737                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1738                         rv.l = ieee754sp_tlong(fs);
1739                         ieee754_csr.rm = oldrm;
1740                         rfmt = l_fmt;
1741                         goto copcsr;
1742
1743                 default:
1744                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1745                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1746                                 union ieee754sp fs, ft;
1747
1748                                 SPFROMREG(fs, MIPSInst_FS(ir));
1749                                 SPFROMREG(ft, MIPSInst_FT(ir));
1750                                 rv.w = ieee754sp_cmp(fs, ft,
1751                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1752                                 rfmt = -1;
1753                                 if ((cmpop & 0x8) && ieee754_cxtest
1754                                         (IEEE754_INVALID_OPERATION))
1755                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1756                                 else
1757                                         goto copcsr;
1758
1759                         } else
1760                                 return SIGILL;
1761                         break;
1762                 }
1763                 break;
1764         }
1765
1766         case d_fmt: {
1767                 union ieee754dp fs, ft;
1768                 union {
1769                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1770                         union ieee754dp(*u) (union ieee754dp);
1771                 } handler;
1772
1773                 switch (MIPSInst_FUNC(ir)) {
1774                         /* binary ops */
1775                 case fadd_op:
1776                         handler.b = ieee754dp_add;
1777                         goto dcopbop;
1778                 case fsub_op:
1779                         handler.b = ieee754dp_sub;
1780                         goto dcopbop;
1781                 case fmul_op:
1782                         handler.b = ieee754dp_mul;
1783                         goto dcopbop;
1784                 case fdiv_op:
1785                         handler.b = ieee754dp_div;
1786                         goto dcopbop;
1787
1788                         /* unary  ops */
1789                 case fsqrt_op:
1790                         if (!cpu_has_mips_2_3_4_5_r)
1791                                 return SIGILL;
1792
1793                         handler.u = ieee754dp_sqrt;
1794                         goto dcopuop;
1795                 /*
1796                  * Note that on some MIPS IV implementations such as the
1797                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1798                  * achieve full IEEE-754 accuracy - however this emulator does.
1799                  */
1800                 case frsqrt_op:
1801                         if (!cpu_has_mips_4_5_64_r2_r6)
1802                                 return SIGILL;
1803
1804                         handler.u = fpemu_dp_rsqrt;
1805                         goto dcopuop;
1806                 case frecip_op:
1807                         if (!cpu_has_mips_4_5_64_r2_r6)
1808                                 return SIGILL;
1809
1810                         handler.u = fpemu_dp_recip;
1811                         goto dcopuop;
1812                 case fmovc_op:
1813                         if (!cpu_has_mips_4_5_r)
1814                                 return SIGILL;
1815
1816                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1817                         if (((ctx->fcr31 & cond) != 0) !=
1818                                 ((MIPSInst_FT(ir) & 1) != 0))
1819                                 return 0;
1820                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1821                         break;
1822                 case fmovz_op:
1823                         if (!cpu_has_mips_4_5_r)
1824                                 return SIGILL;
1825
1826                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1827                                 return 0;
1828                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1829                         break;
1830                 case fmovn_op:
1831                         if (!cpu_has_mips_4_5_r)
1832                                 return SIGILL;
1833
1834                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1835                                 return 0;
1836                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1837                         break;
1838                 case fabs_op:
1839                         handler.u = ieee754dp_abs;
1840                         goto dcopuop;
1841
1842                 case fneg_op:
1843                         handler.u = ieee754dp_neg;
1844                         goto dcopuop;
1845
1846                 case fmov_op:
1847                         /* an easy one */
1848                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1849                         goto copcsr;
1850
1851                         /* binary op on handler */
1852 dcopbop:
1853                         DPFROMREG(fs, MIPSInst_FS(ir));
1854                         DPFROMREG(ft, MIPSInst_FT(ir));
1855
1856                         rv.d = (*handler.b) (fs, ft);
1857                         goto copcsr;
1858 dcopuop:
1859                         DPFROMREG(fs, MIPSInst_FS(ir));
1860                         rv.d = (*handler.u) (fs);
1861                         goto copcsr;
1862
1863                 /*
1864                  * unary conv ops
1865                  */
1866                 case fcvts_op:
1867                         DPFROMREG(fs, MIPSInst_FS(ir));
1868                         rv.s = ieee754sp_fdp(fs);
1869                         rfmt = s_fmt;
1870                         goto copcsr;
1871
1872                 case fcvtd_op:
1873                         return SIGILL;  /* not defined */
1874
1875                 case fcvtw_op:
1876                         DPFROMREG(fs, MIPSInst_FS(ir));
1877                         rv.w = ieee754dp_tint(fs);      /* wrong */
1878                         rfmt = w_fmt;
1879                         goto copcsr;
1880
1881                 case fround_op:
1882                 case ftrunc_op:
1883                 case fceil_op:
1884                 case ffloor_op:
1885                         if (!cpu_has_mips_2_3_4_5_r)
1886                                 return SIGILL;
1887
1888                         oldrm = ieee754_csr.rm;
1889                         DPFROMREG(fs, MIPSInst_FS(ir));
1890                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1891                         rv.w = ieee754dp_tint(fs);
1892                         ieee754_csr.rm = oldrm;
1893                         rfmt = w_fmt;
1894                         goto copcsr;
1895
1896                 case fcvtl_op:
1897                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1898                                 return SIGILL;
1899
1900                         DPFROMREG(fs, MIPSInst_FS(ir));
1901                         rv.l = ieee754dp_tlong(fs);
1902                         rfmt = l_fmt;
1903                         goto copcsr;
1904
1905                 case froundl_op:
1906                 case ftruncl_op:
1907                 case fceill_op:
1908                 case ffloorl_op:
1909                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1910                                 return SIGILL;
1911
1912                         oldrm = ieee754_csr.rm;
1913                         DPFROMREG(fs, MIPSInst_FS(ir));
1914                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1915                         rv.l = ieee754dp_tlong(fs);
1916                         ieee754_csr.rm = oldrm;
1917                         rfmt = l_fmt;
1918                         goto copcsr;
1919
1920                 default:
1921                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1922                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1923                                 union ieee754dp fs, ft;
1924
1925                                 DPFROMREG(fs, MIPSInst_FS(ir));
1926                                 DPFROMREG(ft, MIPSInst_FT(ir));
1927                                 rv.w = ieee754dp_cmp(fs, ft,
1928                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1929                                 rfmt = -1;
1930                                 if ((cmpop & 0x8)
1931                                         &&
1932                                         ieee754_cxtest
1933                                         (IEEE754_INVALID_OPERATION))
1934                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1935                                 else
1936                                         goto copcsr;
1937
1938                         }
1939                         else {
1940                                 return SIGILL;
1941                         }
1942                         break;
1943                 }
1944                 break;
1945
1946         case w_fmt:
1947                 switch (MIPSInst_FUNC(ir)) {
1948                 case fcvts_op:
1949                         /* convert word to single precision real */
1950                         SPFROMREG(fs, MIPSInst_FS(ir));
1951                         rv.s = ieee754sp_fint(fs.bits);
1952                         rfmt = s_fmt;
1953                         goto copcsr;
1954                 case fcvtd_op:
1955                         /* convert word to double precision real */
1956                         SPFROMREG(fs, MIPSInst_FS(ir));
1957                         rv.d = ieee754dp_fint(fs.bits);
1958                         rfmt = d_fmt;
1959                         goto copcsr;
1960                 default:
1961                         return SIGILL;
1962                 }
1963                 break;
1964         }
1965
1966         case l_fmt:
1967
1968                 if (!cpu_has_mips_3_4_5_64_r2_r6)
1969                         return SIGILL;
1970
1971                 DIFROMREG(bits, MIPSInst_FS(ir));
1972
1973                 switch (MIPSInst_FUNC(ir)) {
1974                 case fcvts_op:
1975                         /* convert long to single precision real */
1976                         rv.s = ieee754sp_flong(bits);
1977                         rfmt = s_fmt;
1978                         goto copcsr;
1979                 case fcvtd_op:
1980                         /* convert long to double precision real */
1981                         rv.d = ieee754dp_flong(bits);
1982                         rfmt = d_fmt;
1983                         goto copcsr;
1984                 default:
1985                         return SIGILL;
1986                 }
1987                 break;
1988
1989         default:
1990                 return SIGILL;
1991         }
1992
1993         /*
1994          * Update the fpu CSR register for this operation.
1995          * If an exception is required, generate a tidy SIGFPE exception,
1996          * without updating the result register.
1997          * Note: cause exception bits do not accumulate, they are rewritten
1998          * for each op; only the flag/sticky bits accumulate.
1999          */
2000         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2001         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2002                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2003                 return SIGFPE;
2004         }
2005
2006         /*
2007          * Now we can safely write the result back to the register file.
2008          */
2009         switch (rfmt) {
2010         case -1:
2011
2012                 if (cpu_has_mips_4_5_r)
2013                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2014                 else
2015                         cbit = FPU_CSR_COND;
2016                 if (rv.w)
2017                         ctx->fcr31 |= cbit;
2018                 else
2019                         ctx->fcr31 &= ~cbit;
2020                 break;
2021
2022         case d_fmt:
2023                 DPTOREG(rv.d, MIPSInst_FD(ir));
2024                 break;
2025         case s_fmt:
2026                 SPTOREG(rv.s, MIPSInst_FD(ir));
2027                 break;
2028         case w_fmt:
2029                 SITOREG(rv.w, MIPSInst_FD(ir));
2030                 break;
2031         case l_fmt:
2032                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2033                         return SIGILL;
2034
2035                 DITOREG(rv.l, MIPSInst_FD(ir));
2036                 break;
2037         default:
2038                 return SIGILL;
2039         }
2040
2041         return 0;
2042 }
2043
2044 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2045         int has_fpu, void *__user *fault_addr)
2046 {
2047         unsigned long oldepc, prevepc;
2048         struct mm_decoded_insn dec_insn;
2049         u16 instr[4];
2050         u16 *instr_ptr;
2051         int sig = 0;
2052
2053         oldepc = xcp->cp0_epc;
2054         do {
2055                 prevepc = xcp->cp0_epc;
2056
2057                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2058                         /*
2059                          * Get next 2 microMIPS instructions and convert them
2060                          * into 32-bit instructions.
2061                          */
2062                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2063                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2064                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2065                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2066                                 MIPS_FPU_EMU_INC_STATS(errors);
2067                                 return SIGBUS;
2068                         }
2069                         instr_ptr = instr;
2070
2071                         /* Get first instruction. */
2072                         if (mm_insn_16bit(*instr_ptr)) {
2073                                 /* Duplicate the half-word. */
2074                                 dec_insn.insn = (*instr_ptr << 16) |
2075                                         (*instr_ptr);
2076                                 /* 16-bit instruction. */
2077                                 dec_insn.pc_inc = 2;
2078                                 instr_ptr += 1;
2079                         } else {
2080                                 dec_insn.insn = (*instr_ptr << 16) |
2081                                         *(instr_ptr+1);
2082                                 /* 32-bit instruction. */
2083                                 dec_insn.pc_inc = 4;
2084                                 instr_ptr += 2;
2085                         }
2086                         /* Get second instruction. */
2087                         if (mm_insn_16bit(*instr_ptr)) {
2088                                 /* Duplicate the half-word. */
2089                                 dec_insn.next_insn = (*instr_ptr << 16) |
2090                                         (*instr_ptr);
2091                                 /* 16-bit instruction. */
2092                                 dec_insn.next_pc_inc = 2;
2093                         } else {
2094                                 dec_insn.next_insn = (*instr_ptr << 16) |
2095                                         *(instr_ptr+1);
2096                                 /* 32-bit instruction. */
2097                                 dec_insn.next_pc_inc = 4;
2098                         }
2099                         dec_insn.micro_mips_mode = 1;
2100                 } else {
2101                         if ((get_user(dec_insn.insn,
2102                             (mips_instruction __user *) xcp->cp0_epc)) ||
2103                             (get_user(dec_insn.next_insn,
2104                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2105                                 MIPS_FPU_EMU_INC_STATS(errors);
2106                                 return SIGBUS;
2107                         }
2108                         dec_insn.pc_inc = 4;
2109                         dec_insn.next_pc_inc = 4;
2110                         dec_insn.micro_mips_mode = 0;
2111                 }
2112
2113                 if ((dec_insn.insn == 0) ||
2114                    ((dec_insn.pc_inc == 2) &&
2115                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2116                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2117                 else {
2118                         /*
2119                          * The 'ieee754_csr' is an alias of ctx->fcr31.
2120                          * No need to copy ctx->fcr31 to ieee754_csr.
2121                          */
2122                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2123                 }
2124
2125                 if (has_fpu)
2126                         break;
2127                 if (sig)
2128                         break;
2129
2130                 cond_resched();
2131         } while (xcp->cp0_epc > prevepc);
2132
2133         /* SIGILL indicates a non-fpu instruction */
2134         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2135                 /* but if EPC has advanced, then ignore it */
2136                 sig = 0;
2137
2138         return sig;
2139 }