arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/cpu-info.h>
  49 #include <asm/processor.h>
  50 #include <asm/fpu_emulator.h>
  51 #include <asm/fpu.h>
  52 #include <asm/mips-r2-to-r6-emul.h>
  53
  54 #include "ieee754.h"
  55
  56 /* Function which emulates a floating point instruction. */
  57
  58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  59         mips_instruction);
  60
  61 static int fpux_emu(struct pt_regs *,
  62         struct mips_fpu_struct *, mips_instruction, void *__user *);
  63
  64 /* Control registers */
  65
  66 #define FPCREG_RID      0       /* $0  = revision id */
  67 #define FPCREG_FCCR     25      /* $25 = fccr */
  68 #define FPCREG_FEXR     26      /* $26 = fexr */
  69 #define FPCREG_FENR     28      /* $28 = fenr */
  70 #define FPCREG_CSR      31      /* $31 = csr */
  71
  72 /* convert condition code register number to csr bit */
  73 const unsigned int fpucondbit[8] = {
  74         FPU_CSR_COND,
  75         FPU_CSR_COND1,
  76         FPU_CSR_COND2,
  77         FPU_CSR_COND3,
  78         FPU_CSR_COND4,
  79         FPU_CSR_COND5,
  80         FPU_CSR_COND6,
  81         FPU_CSR_COND7
  82 };
  83
  84 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  85 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  86 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  87 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  88 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  89
  90 /*
  91  * This functions translates a 32-bit microMIPS instruction
  92  * into a 32-bit MIPS32 instruction. Returns 0 on success
  93  * and SIGILL otherwise.
  94  */
  95 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  96 {
  97         union mips_instruction insn = *insn_ptr;
  98         union mips_instruction mips32_insn = insn;
  99         int func, fmt, op;
 100
 101         switch (insn.mm_i_format.opcode) {
 102         case mm_ldc132_op:
 103                 mips32_insn.mm_i_format.opcode = ldc1_op;
 104                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 105                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 106                 break;
 107         case mm_lwc132_op:
 108                 mips32_insn.mm_i_format.opcode = lwc1_op;
 109                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 110                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 111                 break;
 112         case mm_sdc132_op:
 113                 mips32_insn.mm_i_format.opcode = sdc1_op;
 114                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 115                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 116                 break;
 117         case mm_swc132_op:
 118                 mips32_insn.mm_i_format.opcode = swc1_op;
 119                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 120                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 121                 break;
 122         case mm_pool32i_op:
 123                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 124                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 125                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 126                         mips32_insn.fb_format.opcode = cop1_op;
 127                         mips32_insn.fb_format.bc = bc_op;
 128                         mips32_insn.fb_format.flag =
 129                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 130                 } else
 131                         return SIGILL;
 132                 break;
 133         case mm_pool32f_op:
 134                 switch (insn.mm_fp0_format.func) {
 135                 case mm_32f_01_op:
 136                 case mm_32f_11_op:
 137                 case mm_32f_02_op:
 138                 case mm_32f_12_op:
 139                 case mm_32f_41_op:
 140                 case mm_32f_51_op:
 141                 case mm_32f_42_op:
 142                 case mm_32f_52_op:
 143                         op = insn.mm_fp0_format.func;
 144                         if (op == mm_32f_01_op)
 145                                 func = madd_s_op;
 146                         else if (op == mm_32f_11_op)
 147                                 func = madd_d_op;
 148                         else if (op == mm_32f_02_op)
 149                                 func = nmadd_s_op;
 150                         else if (op == mm_32f_12_op)
 151                                 func = nmadd_d_op;
 152                         else if (op == mm_32f_41_op)
 153                                 func = msub_s_op;
 154                         else if (op == mm_32f_51_op)
 155                                 func = msub_d_op;
 156                         else if (op == mm_32f_42_op)
 157                                 func = nmsub_s_op;
 158                         else
 159                                 func = nmsub_d_op;
 160                         mips32_insn.fp6_format.opcode = cop1x_op;
 161                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 162                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 163                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 164                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 165                         mips32_insn.fp6_format.func = func;
 166                         break;
 167                 case mm_32f_10_op:
 168                         func = -1;      /* Invalid */
 169                         op = insn.mm_fp5_format.op & 0x7;
 170                         if (op == mm_ldxc1_op)
 171                                 func = ldxc1_op;
 172                         else if (op == mm_sdxc1_op)
 173                                 func = sdxc1_op;
 174                         else if (op == mm_lwxc1_op)
 175                                 func = lwxc1_op;
 176                         else if (op == mm_swxc1_op)
 177                                 func = swxc1_op;
 178
 179                         if (func != -1) {
 180                                 mips32_insn.r_format.opcode = cop1x_op;
 181                                 mips32_insn.r_format.rs =
 182                                         insn.mm_fp5_format.base;
 183                                 mips32_insn.r_format.rt =
 184                                         insn.mm_fp5_format.index;
 185                                 mips32_insn.r_format.rd = 0;
 186                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 187                                 mips32_insn.r_format.func = func;
 188                         } else
 189                                 return SIGILL;
 190                         break;
 191                 case mm_32f_40_op:
 192                         op = -1;        /* Invalid */
 193                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 194                                 op = 1;
 195                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 196                                 op = 0;
 197                         if (op != -1) {
 198                                 mips32_insn.fp0_format.opcode = cop1_op;
 199                                 mips32_insn.fp0_format.fmt =
 200                                         sdps_format[insn.mm_fp2_format.fmt];
 201                                 mips32_insn.fp0_format.ft =
 202                                         (insn.mm_fp2_format.cc<<2) + op;
 203                                 mips32_insn.fp0_format.fs =
 204                                         insn.mm_fp2_format.fs;
 205                                 mips32_insn.fp0_format.fd =
 206                                         insn.mm_fp2_format.fd;
 207                                 mips32_insn.fp0_format.func = fmovc_op;
 208                         } else
 209                                 return SIGILL;
 210                         break;
 211                 case mm_32f_60_op:
 212                         func = -1;      /* Invalid */
 213                         if (insn.mm_fp0_format.op == mm_fadd_op)
 214                                 func = fadd_op;
 215                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 216                                 func = fsub_op;
 217                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 218                                 func = fmul_op;
 219                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 220                                 func = fdiv_op;
 221                         if (func != -1) {
 222                                 mips32_insn.fp0_format.opcode = cop1_op;
 223                                 mips32_insn.fp0_format.fmt =
 224                                         sdps_format[insn.mm_fp0_format.fmt];
 225                                 mips32_insn.fp0_format.ft =
 226                                         insn.mm_fp0_format.ft;
 227                                 mips32_insn.fp0_format.fs =
 228                                         insn.mm_fp0_format.fs;
 229                                 mips32_insn.fp0_format.fd =
 230                                         insn.mm_fp0_format.fd;
 231                                 mips32_insn.fp0_format.func = func;
 232                         } else
 233                                 return SIGILL;
 234                         break;
 235                 case mm_32f_70_op:
 236                         func = -1;      /* Invalid */
 237                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 238                                 func = fmovn_op;
 239                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 240                                 func = fmovz_op;
 241                         if (func != -1) {
 242                                 mips32_insn.fp0_format.opcode = cop1_op;
 243                                 mips32_insn.fp0_format.fmt =
 244                                         sdps_format[insn.mm_fp0_format.fmt];
 245                                 mips32_insn.fp0_format.ft =
 246                                         insn.mm_fp0_format.ft;
 247                                 mips32_insn.fp0_format.fs =
 248                                         insn.mm_fp0_format.fs;
 249                                 mips32_insn.fp0_format.fd =
 250                                         insn.mm_fp0_format.fd;
 251                                 mips32_insn.fp0_format.func = func;
 252                         } else
 253                                 return SIGILL;
 254                         break;
 255                 case mm_32f_73_op:    /* POOL32FXF */
 256                         switch (insn.mm_fp1_format.op) {
 257                         case mm_movf0_op:
 258                         case mm_movf1_op:
 259                         case mm_movt0_op:
 260                         case mm_movt1_op:
 261                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 262                                     mm_movf0_op)
 263                                         op = 0;
 264                                 else
 265                                         op = 1;
 266                                 mips32_insn.r_format.opcode = spec_op;
 267                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 268                                 mips32_insn.r_format.rt =
 269                                         (insn.mm_fp4_format.cc << 2) + op;
 270                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 271                                 mips32_insn.r_format.re = 0;
 272                                 mips32_insn.r_format.func = movc_op;
 273                                 break;
 274                         case mm_fcvtd0_op:
 275                         case mm_fcvtd1_op:
 276                         case mm_fcvts0_op:
 277                         case mm_fcvts1_op:
 278                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 279                                     mm_fcvtd0_op) {
 280                                         func = fcvtd_op;
 281                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 282                                 } else {
 283                                         func = fcvts_op;
 284                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 285                                 }
 286                                 mips32_insn.fp0_format.opcode = cop1_op;
 287                                 mips32_insn.fp0_format.fmt = fmt;
 288                                 mips32_insn.fp0_format.ft = 0;
 289                                 mips32_insn.fp0_format.fs =
 290                                         insn.mm_fp3_format.fs;
 291                                 mips32_insn.fp0_format.fd =
 292                                         insn.mm_fp3_format.rt;
 293                                 mips32_insn.fp0_format.func = func;
 294                                 break;
 295                         case mm_fmov0_op:
 296                         case mm_fmov1_op:
 297                         case mm_fabs0_op:
 298                         case mm_fabs1_op:
 299                         case mm_fneg0_op:
 300                         case mm_fneg1_op:
 301                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 302                                     mm_fmov0_op)
 303                                         func = fmov_op;
 304                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 305                                          mm_fabs0_op)
 306                                         func = fabs_op;
 307                                 else
 308                                         func = fneg_op;
 309                                 mips32_insn.fp0_format.opcode = cop1_op;
 310                                 mips32_insn.fp0_format.fmt =
 311                                         sdps_format[insn.mm_fp3_format.fmt];
 312                                 mips32_insn.fp0_format.ft = 0;
 313                                 mips32_insn.fp0_format.fs =
 314                                         insn.mm_fp3_format.fs;
 315                                 mips32_insn.fp0_format.fd =
 316                                         insn.mm_fp3_format.rt;
 317                                 mips32_insn.fp0_format.func = func;
 318                                 break;
 319                         case mm_ffloorl_op:
 320                         case mm_ffloorw_op:
 321                         case mm_fceill_op:
 322                         case mm_fceilw_op:
 323                         case mm_ftruncl_op:
 324                         case mm_ftruncw_op:
 325                         case mm_froundl_op:
 326                         case mm_froundw_op:
 327                         case mm_fcvtl_op:
 328                         case mm_fcvtw_op:
 329                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 330                                         func = ffloorl_op;
 331                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 332                                         func = ffloor_op;
 333                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 334                                         func = fceill_op;
 335                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 336                                         func = fceil_op;
 337                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 338                                         func = ftruncl_op;
 339                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 340                                         func = ftrunc_op;
 341                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 342                                         func = froundl_op;
 343                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 344                                         func = fround_op;
 345                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 346                                         func = fcvtl_op;
 347                                 else
 348                                         func = fcvtw_op;
 349                                 mips32_insn.fp0_format.opcode = cop1_op;
 350                                 mips32_insn.fp0_format.fmt =
 351                                         sd_format[insn.mm_fp1_format.fmt];
 352                                 mips32_insn.fp0_format.ft = 0;
 353                                 mips32_insn.fp0_format.fs =
 354                                         insn.mm_fp1_format.fs;
 355                                 mips32_insn.fp0_format.fd =
 356                                         insn.mm_fp1_format.rt;
 357                                 mips32_insn.fp0_format.func = func;
 358                                 break;
 359                         case mm_frsqrt_op:
 360                         case mm_fsqrt_op:
 361                         case mm_frecip_op:
 362                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 363                                         func = frsqrt_op;
 364                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 365                                         func = fsqrt_op;
 366                                 else
 367                                         func = frecip_op;
 368                                 mips32_insn.fp0_format.opcode = cop1_op;
 369                                 mips32_insn.fp0_format.fmt =
 370                                         sdps_format[insn.mm_fp1_format.fmt];
 371                                 mips32_insn.fp0_format.ft = 0;
 372                                 mips32_insn.fp0_format.fs =
 373                                         insn.mm_fp1_format.fs;
 374                                 mips32_insn.fp0_format.fd =
 375                                         insn.mm_fp1_format.rt;
 376                                 mips32_insn.fp0_format.func = func;
 377                                 break;
 378                         case mm_mfc1_op:
 379                         case mm_mtc1_op:
 380                         case mm_cfc1_op:
 381                         case mm_ctc1_op:
 382                         case mm_mfhc1_op:
 383                         case mm_mthc1_op:
 384                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 385                                         op = mfc_op;
 386                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 387                                         op = mtc_op;
 388                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 389                                         op = cfc_op;
 390                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 391                                         op = ctc_op;
 392                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 393                                         op = mfhc_op;
 394                                 else
 395                                         op = mthc_op;
 396                                 mips32_insn.fp1_format.opcode = cop1_op;
 397                                 mips32_insn.fp1_format.op = op;
 398                                 mips32_insn.fp1_format.rt =
 399                                         insn.mm_fp1_format.rt;
 400                                 mips32_insn.fp1_format.fs =
 401                                         insn.mm_fp1_format.fs;
 402                                 mips32_insn.fp1_format.fd = 0;
 403                                 mips32_insn.fp1_format.func = 0;
 404                                 break;
 405                         default:
 406                                 return SIGILL;
 407                         }
 408                         break;
 409                 case mm_32f_74_op:      /* c.cond.fmt */
 410                         mips32_insn.fp0_format.opcode = cop1_op;
 411                         mips32_insn.fp0_format.fmt =
 412                                 sdps_format[insn.mm_fp4_format.fmt];
 413                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 414                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 415                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 416                         mips32_insn.fp0_format.func =
 417                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 418                         break;
 419                 default:
 420                         return SIGILL;
 421                 }
 422                 break;
 423         default:
 424                 return SIGILL;
 425         }
 426
 427         *insn_ptr = mips32_insn;
 428         return 0;
 429 }
 430
 431 /*
 432  * Redundant with logic already in kernel/branch.c,
 433  * embedded in compute_return_epc.  At some point,
 434  * a single subroutine should be used across both
 435  * modules.
 436  */
 437 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 438                          unsigned long *contpc)
 439 {
 440         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 441         unsigned int fcr31;
 442         unsigned int bit = 0;
 443
 444         switch (insn.i_format.opcode) {
 445         case spec_op:
 446                 switch (insn.r_format.func) {
 447                 case jalr_op:
 448                         regs->regs[insn.r_format.rd] =
 449                                 regs->cp0_epc + dec_insn.pc_inc +
 450                                 dec_insn.next_pc_inc;
 451                         /* Fall through */
 452                 case jr_op:
 453                         /* For R6, JR already emulated in jalr_op */
 454                         if (NO_R6EMU && insn.r_format.opcode == jr_op)
 455                                 break;
 456                         *contpc = regs->regs[insn.r_format.rs];
 457                         return 1;
 458                 }
 459                 break;
 460         case bcond_op:
 461                 switch (insn.i_format.rt) {
 462                 case bltzal_op:
 463                 case bltzall_op:
 464                         if (NO_R6EMU && (insn.i_format.rs ||
 465                             insn.i_format.rt == bltzall_op))
 466                                 break;
 467
 468                         regs->regs[31] = regs->cp0_epc +
 469                                 dec_insn.pc_inc +
 470                                 dec_insn.next_pc_inc;
 471                         /* Fall through */
 472                 case bltzl_op:
 473                         if (NO_R6EMU)
 474                                 break;
 475                 case bltz_op:
 476                         if ((long)regs->regs[insn.i_format.rs] < 0)
 477                                 *contpc = regs->cp0_epc +
 478                                         dec_insn.pc_inc +
 479                                         (insn.i_format.simmediate << 2);
 480                         else
 481                                 *contpc = regs->cp0_epc +
 482                                         dec_insn.pc_inc +
 483                                         dec_insn.next_pc_inc;
 484                         return 1;
 485                 case bgezal_op:
 486                 case bgezall_op:
 487                         if (NO_R6EMU && (insn.i_format.rs ||
 488                             insn.i_format.rt == bgezall_op))
 489                                 break;
 490
 491                         regs->regs[31] = regs->cp0_epc +
 492                                 dec_insn.pc_inc +
 493                                 dec_insn.next_pc_inc;
 494                         /* Fall through */
 495                 case bgezl_op:
 496                         if (NO_R6EMU)
 497                                 break;
 498                 case bgez_op:
 499                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 500                                 *contpc = regs->cp0_epc +
 501                                         dec_insn.pc_inc +
 502                                         (insn.i_format.simmediate << 2);
 503                         else
 504                                 *contpc = regs->cp0_epc +
 505                                         dec_insn.pc_inc +
 506                                         dec_insn.next_pc_inc;
 507                         return 1;
 508                 }
 509                 break;
 510         case jalx_op:
 511                 set_isa16_mode(bit);
 512         case jal_op:
 513                 regs->regs[31] = regs->cp0_epc +
 514                         dec_insn.pc_inc +
 515                         dec_insn.next_pc_inc;
 516                 /* Fall through */
 517         case j_op:
 518                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 519                 *contpc >>= 28;
 520                 *contpc <<= 28;
 521                 *contpc |= (insn.j_format.target << 2);
 522                 /* Set microMIPS mode bit: XOR for jalx. */
 523                 *contpc ^= bit;
 524                 return 1;
 525         case beql_op:
 526                 if (NO_R6EMU)
 527                         break;
 528         case beq_op:
 529                 if (regs->regs[insn.i_format.rs] ==
 530                     regs->regs[insn.i_format.rt])
 531                         *contpc = regs->cp0_epc +
 532                                 dec_insn.pc_inc +
 533                                 (insn.i_format.simmediate << 2);
 534                 else
 535                         *contpc = regs->cp0_epc +
 536                                 dec_insn.pc_inc +
 537                                 dec_insn.next_pc_inc;
 538                 return 1;
 539         case bnel_op:
 540                 if (NO_R6EMU)
 541                         break;
 542         case bne_op:
 543                 if (regs->regs[insn.i_format.rs] !=
 544                     regs->regs[insn.i_format.rt])
 545                         *contpc = regs->cp0_epc +
 546                                 dec_insn.pc_inc +
 547                                 (insn.i_format.simmediate << 2);
 548                 else
 549                         *contpc = regs->cp0_epc +
 550                                 dec_insn.pc_inc +
 551                                 dec_insn.next_pc_inc;
 552                 return 1;
 553         case blezl_op:
 554                 if (NO_R6EMU)
 555                         break;
 556         case blez_op:
 557
 558                 /*
 559                  * Compact branches for R6 for the
 560                  * blez and blezl opcodes.
 561                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
 562                  * BLEZ  | rs = rt != 0      == BGEZALC
 563                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
 564                  * BLEZL | rs = 0 | rt != 0  == BLEZC
 565                  * BLEZL | rs = rt != 0      == BGEZC
 566                  * BLEZL | rs != 0 | rt != 0 == BGEC
 567                  *
 568                  * For real BLEZ{,L}, rt is always 0.
 569                  */
 570                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 571                         if ((insn.i_format.opcode == blez_op) &&
 572                             ((!insn.i_format.rs && insn.i_format.rt) ||
 573                              (insn.i_format.rs == insn.i_format.rt)))
 574                                 regs->regs[31] = regs->cp0_epc +
 575                                         dec_insn.pc_inc;
 576                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 577                                 dec_insn.next_pc_inc;
 578
 579                         return 1;
 580                 }
 581                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 582                         *contpc = regs->cp0_epc +
 583                                 dec_insn.pc_inc +
 584                                 (insn.i_format.simmediate << 2);
 585                 else
 586                         *contpc = regs->cp0_epc +
 587                                 dec_insn.pc_inc +
 588                                 dec_insn.next_pc_inc;
 589                 return 1;
 590         case bgtzl_op:
 591                 if (NO_R6EMU)
 592                         break;
 593         case bgtz_op:
 594                 /*
 595                  * Compact branches for R6 for the
 596                  * bgtz and bgtzl opcodes.
 597                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
 598                  * BGTZ  | rs = rt != 0      == BLTZALC
 599                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
 600                  * BGTZL | rs = 0 | rt != 0  == BGTZC
 601                  * BGTZL | rs = rt != 0      == BLTZC
 602                  * BGTZL | rs != 0 | rt != 0 == BLTC
 603                  *
 604                  * *ZALC varint for BGTZ &&& rt != 0
 605                  * For real GTZ{,L}, rt is always 0.
 606                  */
 607                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 608                         if ((insn.i_format.opcode == blez_op) &&
 609                             ((!insn.i_format.rs && insn.i_format.rt) ||
 610                              (insn.i_format.rs == insn.i_format.rt)))
 611                                 regs->regs[31] = regs->cp0_epc +
 612                                         dec_insn.pc_inc;
 613                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 614                                 dec_insn.next_pc_inc;
 615
 616                         return 1;
 617                 }
 618
 619                 if ((long)regs->regs[insn.i_format.rs] > 0)
 620                         *contpc = regs->cp0_epc +
 621                                 dec_insn.pc_inc +
 622                                 (insn.i_format.simmediate << 2);
 623                 else
 624                         *contpc = regs->cp0_epc +
 625                                 dec_insn.pc_inc +
 626                                 dec_insn.next_pc_inc;
 627                 return 1;
 628         case cbcond0_op:
 629         case cbcond1_op:
 630                 if (!cpu_has_mips_r6)
 631                         break;
 632                 if (insn.i_format.rt && !insn.i_format.rs)
 633                         regs->regs[31] = regs->cp0_epc + 4;
 634                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 635                         dec_insn.next_pc_inc;
 636
 637                 return 1;
 638 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 639         case lwc2_op: /* This is bbit0 on Octeon */
 640                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 641                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 642                 else
 643                         *contpc = regs->cp0_epc + 8;
 644                 return 1;
 645         case ldc2_op: /* This is bbit032 on Octeon */
 646                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 647                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 648                 else
 649                         *contpc = regs->cp0_epc + 8;
 650                 return 1;
 651         case swc2_op: /* This is bbit1 on Octeon */
 652                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 653                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 654                 else
 655                         *contpc = regs->cp0_epc + 8;
 656                 return 1;
 657         case sdc2_op: /* This is bbit132 on Octeon */
 658                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 659                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 660                 else
 661                         *contpc = regs->cp0_epc + 8;
 662                 return 1;
 663 #else
 664         case bc6_op:
 665                 /*
 666                  * Only valid for MIPS R6 but we can still end up
 667                  * here from a broken userland so just tell emulator
 668                  * this is not a branch and let it break later on.
 669                  */
 670                 if  (!cpu_has_mips_r6)
 671                         break;
 672                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 673                         dec_insn.next_pc_inc;
 674
 675                 return 1;
 676         case balc6_op:
 677                 if (!cpu_has_mips_r6)
 678                         break;
 679                 regs->regs[31] = regs->cp0_epc + 4;
 680                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 681                         dec_insn.next_pc_inc;
 682
 683                 return 1;
 684         case beqzcjic_op:
 685                 if (!cpu_has_mips_r6)
 686                         break;
 687                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 688                         dec_insn.next_pc_inc;
 689
 690                 return 1;
 691         case bnezcjialc_op:
 692                 if (!cpu_has_mips_r6)
 693                         break;
 694                 if (!insn.i_format.rs)
 695                         regs->regs[31] = regs->cp0_epc + 4;
 696                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 697                         dec_insn.next_pc_inc;
 698
 699                 return 1;
 700 #endif
 701         case cop0_op:
 702         case cop1_op:
 703                 /* Need to check for R6 bc1nez and bc1eqz branches */
 704                 if (cpu_has_mips_r6 &&
 705                     ((insn.i_format.rs == bc1eqz_op) ||
 706                      (insn.i_format.rs == bc1nez_op))) {
 707                         bit = 0;
 708                         switch (insn.i_format.rs) {
 709                         case bc1eqz_op:
 710                                 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
 711                                     bit = 1;
 712                                 break;
 713                         case bc1nez_op:
 714                                 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
 715                                     bit = 1;
 716                                 break;
 717                         }
 718                         if (bit)
 719                                 *contpc = regs->cp0_epc +
 720                                         dec_insn.pc_inc +
 721                                         (insn.i_format.simmediate << 2);
 722                         else
 723                                 *contpc = regs->cp0_epc +
 724                                         dec_insn.pc_inc +
 725                                         dec_insn.next_pc_inc;
 726
 727                         return 1;
 728                 }
 729                 /* R2/R6 compatible cop1 instruction. Fall through */
 730         case cop2_op:
 731         case cop1x_op:
 732                 if (insn.i_format.rs == bc_op) {
 733                         preempt_disable();
 734                         if (is_fpu_owner())
 735                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 736                         else
 737                                 fcr31 = current->thread.fpu.fcr31;
 738                         preempt_enable();
 739
 740                         bit = (insn.i_format.rt >> 2);
 741                         bit += (bit != 0);
 742                         bit += 23;
 743                         switch (insn.i_format.rt & 3) {
 744                         case 0: /* bc1f */
 745                         case 2: /* bc1fl */
 746                                 if (~fcr31 & (1 << bit))
 747                                         *contpc = regs->cp0_epc +
 748                                                 dec_insn.pc_inc +
 749                                                 (insn.i_format.simmediate << 2);
 750                                 else
 751                                         *contpc = regs->cp0_epc +
 752                                                 dec_insn.pc_inc +
 753                                                 dec_insn.next_pc_inc;
 754                                 return 1;
 755                         case 1: /* bc1t */
 756                         case 3: /* bc1tl */
 757                                 if (fcr31 & (1 << bit))
 758                                         *contpc = regs->cp0_epc +
 759                                                 dec_insn.pc_inc +
 760                                                 (insn.i_format.simmediate << 2);
 761                                 else
 762                                         *contpc = regs->cp0_epc +
 763                                                 dec_insn.pc_inc +
 764                                                 dec_insn.next_pc_inc;
 765                                 return 1;
 766                         }
 767                 }
 768                 break;
 769         }
 770         return 0;
 771 }
 772
 773 /*
 774  * In the Linux kernel, we support selection of FPR format on the
 775  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 776  * is hardwired to zero, which would imply a 32-bit FPU even for
 777  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 778  * FPU emu is slow and bulky and optimizing this function offers fairly
 779  * sizeable benefits so we try to be clever and make this function return
 780  * a constant whenever possible, that is on 64-bit kernels without O32
 781  * compatibility enabled and on 32-bit without 64-bit FPU support.
 782  */
 783 static inline int cop1_64bit(struct pt_regs *xcp)
 784 {
 785         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 786                 return 1;
 787         else if (config_enabled(CONFIG_32BIT) &&
 788                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 789                 return 0;
 790
 791         return !test_thread_flag(TIF_32BIT_FPREGS);
 792 }
 793
 794 static inline bool hybrid_fprs(void)
 795 {
 796         return test_thread_flag(TIF_HYBRID_FPREGS);
 797 }
 798
 799 #define SIFROMREG(si, x)                                                \
 800 do {                                                                    \
 801         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 802                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 803         else                                                            \
 804                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 805 } while (0)
 806
 807 #define SITOREG(si, x)                                                  \
 808 do {                                                                    \
 809         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 810                 unsigned i;                                             \
 811                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 812                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 813                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 814         } else {                                                        \
 815                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 816         }                                                               \
 817 } while (0)
 818
 819 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 820
 821 #define SITOHREG(si, x)                                                 \
 822 do {                                                                    \
 823         unsigned i;                                                     \
 824         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 825         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 826                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 827 } while (0)
 828
 829 #define DIFROMREG(di, x)                                                \
 830         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 831
 832 #define DITOREG(di, x)                                                  \
 833 do {                                                                    \
 834         unsigned fpr, i;                                                \
 835         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 836         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 837         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 838                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 839 } while (0)
 840
 841 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 842 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 843 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 844 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 845
 846 /*
 847  * Emulate a CFC1 instruction.
 848  */
 849 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 850                             mips_instruction ir)
 851 {
 852         u32 fcr31 = ctx->fcr31;
 853         u32 value = 0;
 854
 855         switch (MIPSInst_RD(ir)) {
 856         case FPCREG_CSR:
 857                 value = fcr31;
 858                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 859                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 860                 break;
 861
 862         case FPCREG_FENR:
 863                 if (!cpu_has_mips_r)
 864                         break;
 865                 value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 866                         MIPS_FENR_FS;
 867                 value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
 868                 pr_debug("%p gpr[%d]<-enr=%08x\n",
 869                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 870                 break;
 871
 872         case FPCREG_FEXR:
 873                 if (!cpu_has_mips_r)
 874                         break;
 875                 value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 876                 pr_debug("%p gpr[%d]<-exr=%08x\n",
 877                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 878                 break;
 879
 880         case FPCREG_FCCR:
 881                 if (!cpu_has_mips_r)
 882                         break;
 883                 value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 884                         MIPS_FCCR_COND0;
 885                 value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 886                          (MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
 887                 pr_debug("%p gpr[%d]<-ccr=%08x\n",
 888                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 889                 break;
 890
 891         case FPCREG_RID:
 892                 value = current_cpu_data.fpu_id;
 893                 break;
 894
 895         default:
 896                 break;
 897         }
 898
 899         if (MIPSInst_RT(ir))
 900                 xcp->regs[MIPSInst_RT(ir)] = value;
 901 }
 902
 903 /*
 904  * Emulate a CTC1 instruction.
 905  */
 906 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 907                             mips_instruction ir)
 908 {
 909         u32 fcr31 = ctx->fcr31;
 910         u32 value;
 911
 912         if (MIPSInst_RT(ir) == 0)
 913                 value = 0;
 914         else
 915                 value = xcp->regs[MIPSInst_RT(ir)];
 916
 917         switch (MIPSInst_RD(ir)) {
 918         case FPCREG_CSR:
 919                 pr_debug("%p gpr[%d]->csr=%08x\n",
 920                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 921
 922                 /* Don't write reserved bits.  */
 923                 fcr31 = value & ~FPU_CSR_RSVD;
 924                 break;
 925
 926         case FPCREG_FENR:
 927                 if (!cpu_has_mips_r)
 928                         break;
 929                 pr_debug("%p gpr[%d]->enr=%08x\n",
 930                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 931                 fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
 932                 fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
 933                          FPU_CSR_FS;
 934                 fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
 935                 break;
 936
 937         case FPCREG_FEXR:
 938                 if (!cpu_has_mips_r)
 939                         break;
 940                 pr_debug("%p gpr[%d]->exr=%08x\n",
 941                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 942                 fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 943                 fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
 944                 break;
 945
 946         case FPCREG_FCCR:
 947                 if (!cpu_has_mips_r)
 948                         break;
 949                 pr_debug("%p gpr[%d]->ccr=%08x\n",
 950                          (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 951                 fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
 952                 fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
 953                          FPU_CSR_COND;
 954                 fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
 955                          FPU_CSR_CONDX;
 956                 break;
 957
 958         default:
 959                 break;
 960         }
 961
 962         ctx->fcr31 = fcr31;
 963 }
 964
 965 /*
 966  * Emulate the single floating point instruction pointed at by EPC.
 967  * Two instructions if the instruction is in a branch delay slot.
 968  */
 969
 970 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 971                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 972 {
 973         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 974         unsigned int cond, cbit;
 975         mips_instruction ir;
 976         int likely, pc_inc;
 977         u32 __user *wva;
 978         u64 __user *dva;
 979         u32 wval;
 980         u64 dval;
 981         int sig;
 982
 983         /*
 984          * These are giving gcc a gentle hint about what to expect in
 985          * dec_inst in order to do better optimization.
 986          */
 987         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 988                 unreachable();
 989
 990         /* XXX NEC Vr54xx bug workaround */
 991         if (delay_slot(xcp)) {
 992                 if (dec_insn.micro_mips_mode) {
 993                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 994                                 clear_delay_slot(xcp);
 995                 } else {
 996                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 997                                 clear_delay_slot(xcp);
 998                 }
 999         }
1000
1001         if (delay_slot(xcp)) {
1002                 /*
1003                  * The instruction to be emulated is in a branch delay slot
1004                  * which means that we have to  emulate the branch instruction
1005                  * BEFORE we do the cop1 instruction.
1006                  *
1007                  * This branch could be a COP1 branch, but in that case we
1008                  * would have had a trap for that instruction, and would not
1009                  * come through this route.
1010                  *
1011                  * Linux MIPS branch emulator operates on context, updating the
1012                  * cp0_epc.
1013                  */
1014                 ir = dec_insn.next_insn;  /* process delay slot instr */
1015                 pc_inc = dec_insn.next_pc_inc;
1016         } else {
1017                 ir = dec_insn.insn;       /* process current instr */
1018                 pc_inc = dec_insn.pc_inc;
1019         }
1020
1021         /*
1022          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
1023          * instructions, we want to convert microMIPS FPU instructions
1024          * into MIPS32 instructions so that we could reuse all of the
1025          * FPU emulation code.
1026          *
1027          * NOTE: We cannot do this for branch instructions since they
1028          *       are not a subset. Example: Cannot emulate a 16-bit
1029          *       aligned target address with a MIPS32 instruction.
1030          */
1031         if (dec_insn.micro_mips_mode) {
1032                 /*
1033                  * If next instruction is a 16-bit instruction, then it
1034                  * it cannot be a FPU instruction. This could happen
1035                  * since we can be called for non-FPU instructions.
1036                  */
1037                 if ((pc_inc == 2) ||
1038                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
1039                          == SIGILL))
1040                         return SIGILL;
1041         }
1042
1043 emul:
1044         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
1045         MIPS_FPU_EMU_INC_STATS(emulated);
1046         switch (MIPSInst_OPCODE(ir)) {
1047         case ldc1_op:
1048                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1049                                      MIPSInst_SIMM(ir));
1050                 MIPS_FPU_EMU_INC_STATS(loads);
1051
1052                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
1053                         MIPS_FPU_EMU_INC_STATS(errors);
1054                         *fault_addr = dva;
1055                         return SIGBUS;
1056                 }
1057                 if (__get_user(dval, dva)) {
1058                         MIPS_FPU_EMU_INC_STATS(errors);
1059                         *fault_addr = dva;
1060                         return SIGSEGV;
1061                 }
1062                 DITOREG(dval, MIPSInst_RT(ir));
1063                 break;
1064
1065         case sdc1_op:
1066                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1067                                       MIPSInst_SIMM(ir));
1068                 MIPS_FPU_EMU_INC_STATS(stores);
1069                 DIFROMREG(dval, MIPSInst_RT(ir));
1070                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
1071                         MIPS_FPU_EMU_INC_STATS(errors);
1072                         *fault_addr = dva;
1073                         return SIGBUS;
1074                 }
1075                 if (__put_user(dval, dva)) {
1076                         MIPS_FPU_EMU_INC_STATS(errors);
1077                         *fault_addr = dva;
1078                         return SIGSEGV;
1079                 }
1080                 break;
1081
1082         case lwc1_op:
1083                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1084                                       MIPSInst_SIMM(ir));
1085                 MIPS_FPU_EMU_INC_STATS(loads);
1086                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1087                         MIPS_FPU_EMU_INC_STATS(errors);
1088                         *fault_addr = wva;
1089                         return SIGBUS;
1090                 }
1091                 if (__get_user(wval, wva)) {
1092                         MIPS_FPU_EMU_INC_STATS(errors);
1093                         *fault_addr = wva;
1094                         return SIGSEGV;
1095                 }
1096                 SITOREG(wval, MIPSInst_RT(ir));
1097                 break;
1098
1099         case swc1_op:
1100                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1101                                       MIPSInst_SIMM(ir));
1102                 MIPS_FPU_EMU_INC_STATS(stores);
1103                 SIFROMREG(wval, MIPSInst_RT(ir));
1104                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1105                         MIPS_FPU_EMU_INC_STATS(errors);
1106                         *fault_addr = wva;
1107                         return SIGBUS;
1108                 }
1109                 if (__put_user(wval, wva)) {
1110                         MIPS_FPU_EMU_INC_STATS(errors);
1111                         *fault_addr = wva;
1112                         return SIGSEGV;
1113                 }
1114                 break;
1115
1116         case cop1_op:
1117                 switch (MIPSInst_RS(ir)) {
1118                 case dmfc_op:
1119                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1120                                 return SIGILL;
1121
1122                         /* copregister fs -> gpr[rt] */
1123                         if (MIPSInst_RT(ir) != 0) {
1124                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1125                                         MIPSInst_RD(ir));
1126                         }
1127                         break;
1128
1129                 case dmtc_op:
1130                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1131                                 return SIGILL;
1132
1133                         /* copregister fs <- rt */
1134                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1135                         break;
1136
1137                 case mfhc_op:
1138                         if (!cpu_has_mips_r2)
1139                                 goto sigill;
1140
1141                         /* copregister rd -> gpr[rt] */
1142                         if (MIPSInst_RT(ir) != 0) {
1143                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1144                                         MIPSInst_RD(ir));
1145                         }
1146                         break;
1147
1148                 case mthc_op:
1149                         if (!cpu_has_mips_r2)
1150                                 goto sigill;
1151
1152                         /* copregister rd <- gpr[rt] */
1153                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1154                         break;
1155
1156                 case mfc_op:
1157                         /* copregister rd -> gpr[rt] */
1158                         if (MIPSInst_RT(ir) != 0) {
1159                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1160                                         MIPSInst_RD(ir));
1161                         }
1162                         break;
1163
1164                 case mtc_op:
1165                         /* copregister rd <- rt */
1166                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1167                         break;
1168
1169                 case cfc_op:
1170                         /* cop control register rd -> gpr[rt] */
1171                         cop1_cfc(xcp, ctx, ir);
1172                         break;
1173
1174                 case ctc_op:
1175                         /* copregister rd <- rt */
1176                         cop1_ctc(xcp, ctx, ir);
1177                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1178                                 return SIGFPE;
1179                         }
1180                         break;
1181
1182                 case bc_op:
1183                         if (delay_slot(xcp))
1184                                 return SIGILL;
1185
1186                         if (cpu_has_mips_4_5_r)
1187                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1188                         else
1189                                 cbit = FPU_CSR_COND;
1190                         cond = ctx->fcr31 & cbit;
1191
1192                         likely = 0;
1193                         switch (MIPSInst_RT(ir) & 3) {
1194                         case bcfl_op:
1195                                 if (cpu_has_mips_2_3_4_5_r)
1196                                         likely = 1;
1197                                 /* Fall through */
1198                         case bcf_op:
1199                                 cond = !cond;
1200                                 break;
1201                         case bctl_op:
1202                                 if (cpu_has_mips_2_3_4_5_r)
1203                                         likely = 1;
1204                                 /* Fall through */
1205                         case bct_op:
1206                                 break;
1207                         }
1208
1209                         set_delay_slot(xcp);
1210                         if (cond) {
1211                                 /*
1212                                  * Branch taken: emulate dslot instruction
1213                                  */
1214                                 unsigned long bcpc;
1215
1216                                 /*
1217                                  * Remember EPC at the branch to point back
1218                                  * at so that any delay-slot instruction
1219                                  * signal is not silently ignored.
1220                                  */
1221                                 bcpc = xcp->cp0_epc;
1222                                 xcp->cp0_epc += dec_insn.pc_inc;
1223
1224                                 contpc = MIPSInst_SIMM(ir);
1225                                 ir = dec_insn.next_insn;
1226                                 if (dec_insn.micro_mips_mode) {
1227                                         contpc = (xcp->cp0_epc + (contpc << 1));
1228
1229                                         /* If 16-bit instruction, not FPU. */
1230                                         if ((dec_insn.next_pc_inc == 2) ||
1231                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1232
1233                                                 /*
1234                                                  * Since this instruction will
1235                                                  * be put on the stack with
1236                                                  * 32-bit words, get around
1237                                                  * this problem by putting a
1238                                                  * NOP16 as the second one.
1239                                                  */
1240                                                 if (dec_insn.next_pc_inc == 2)
1241                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1242
1243                                                 /*
1244                                                  * Single step the non-CP1
1245                                                  * instruction in the dslot.
1246                                                  */
1247                                                 sig = mips_dsemul(xcp, ir,
1248                                                                   contpc);
1249                                                 if (sig)
1250                                                         xcp->cp0_epc = bcpc;
1251                                                 /*
1252                                                  * SIGILL forces out of
1253                                                  * the emulation loop.
1254                                                  */
1255                                                 return sig ? sig : SIGILL;
1256                                         }
1257                                 } else
1258                                         contpc = (xcp->cp0_epc + (contpc << 2));
1259
1260                                 switch (MIPSInst_OPCODE(ir)) {
1261                                 case lwc1_op:
1262                                 case swc1_op:
1263                                         goto emul;
1264
1265                                 case ldc1_op:
1266                                 case sdc1_op:
1267                                         if (cpu_has_mips_2_3_4_5_r)
1268                                                 goto emul;
1269
1270                                         goto bc_sigill;
1271
1272                                 case cop1_op:
1273                                         goto emul;
1274
1275                                 case cop1x_op:
1276                                         if (cpu_has_mips_4_5_64_r2_r6)
1277                                                 /* its one of ours */
1278                                                 goto emul;
1279
1280                                         goto bc_sigill;
1281
1282                                 case spec_op:
1283                                         switch (MIPSInst_FUNC(ir)) {
1284                                         case movc_op:
1285                                                 if (cpu_has_mips_4_5_r)
1286                                                         goto emul;
1287
1288                                                 goto bc_sigill;
1289                                         }
1290                                         break;
1291
1292                                 bc_sigill:
1293                                         xcp->cp0_epc = bcpc;
1294                                         return SIGILL;
1295                                 }
1296
1297                                 /*
1298                                  * Single step the non-cp1
1299                                  * instruction in the dslot
1300                                  */
1301                                 sig = mips_dsemul(xcp, ir, contpc);
1302                                 if (sig)
1303                                         xcp->cp0_epc = bcpc;
1304                                 /* SIGILL forces out of the emulation loop.  */
1305                                 return sig ? sig : SIGILL;
1306                         } else if (likely) {    /* branch not taken */
1307                                 /*
1308                                  * branch likely nullifies
1309                                  * dslot if not taken
1310                                  */
1311                                 xcp->cp0_epc += dec_insn.pc_inc;
1312                                 contpc += dec_insn.pc_inc;
1313                                 /*
1314                                  * else continue & execute
1315                                  * dslot as normal insn
1316                                  */
1317                         }
1318                         break;
1319
1320                 default:
1321                         if (!(MIPSInst_RS(ir) & 0x10))
1322                                 return SIGILL;
1323
1324                         /* a real fpu computation instruction */
1325                         if ((sig = fpu_emu(xcp, ctx, ir)))
1326                                 return sig;
1327                 }
1328                 break;
1329
1330         case cop1x_op:
1331                 if (!cpu_has_mips_4_5_64_r2_r6)
1332                         return SIGILL;
1333
1334                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1335                 if (sig)
1336                         return sig;
1337                 break;
1338
1339         case spec_op:
1340                 if (!cpu_has_mips_4_5_r)
1341                         return SIGILL;
1342
1343                 if (MIPSInst_FUNC(ir) != movc_op)
1344                         return SIGILL;
1345                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1346                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1347                         xcp->regs[MIPSInst_RD(ir)] =
1348                                 xcp->regs[MIPSInst_RS(ir)];
1349                 break;
1350         default:
1351 sigill:
1352                 return SIGILL;
1353         }
1354
1355         /* we did it !! */
1356         xcp->cp0_epc = contpc;
1357         clear_delay_slot(xcp);
1358
1359         return 0;
1360 }
1361
1362 /*
1363  * Conversion table from MIPS compare ops 48-63
1364  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1365  */
1366 static const unsigned char cmptab[8] = {
1367         0,                      /* cmp_0 (sig) cmp_sf */
1368         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1369         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1370         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1371         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1372         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1373         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1374         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1375 };
1376
1377
1378 /*
1379  * Additional MIPS4 instructions
1380  */
1381
1382 #define DEF3OP(name, p, f1, f2, f3)                                     \
1383 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1384         union ieee754##p s, union ieee754##p t)                         \
1385 {                                                                       \
1386         struct _ieee754_csr ieee754_csr_save;                           \
1387         s = f1(s, t);                                                   \
1388         ieee754_csr_save = ieee754_csr;                                 \
1389         s = f2(s, r);                                                   \
1390         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1391         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1392         s = f3(s);                                                      \
1393         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1394         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1395         return s;                                                       \
1396 }
1397
1398 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1399 {
1400         return ieee754dp_div(ieee754dp_one(0), d);
1401 }
1402
1403 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1404 {
1405         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1406 }
1407
1408 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1409 {
1410         return ieee754sp_div(ieee754sp_one(0), s);
1411 }
1412
1413 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1414 {
1415         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1416 }
1417
1418 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1419 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1420 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1421 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1422 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1423 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1424 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1425 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1426
1427 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1428         mips_instruction ir, void *__user *fault_addr)
1429 {
1430         unsigned rcsr = 0;      /* resulting csr */
1431
1432         MIPS_FPU_EMU_INC_STATS(cp1xops);
1433
1434         switch (MIPSInst_FMA_FFMT(ir)) {
1435         case s_fmt:{            /* 0 */
1436
1437                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1438                 union ieee754sp fd, fr, fs, ft;
1439                 u32 __user *va;
1440                 u32 val;
1441
1442                 switch (MIPSInst_FUNC(ir)) {
1443                 case lwxc1_op:
1444                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1445                                 xcp->regs[MIPSInst_FT(ir)]);
1446
1447                         MIPS_FPU_EMU_INC_STATS(loads);
1448                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1449                                 MIPS_FPU_EMU_INC_STATS(errors);
1450                                 *fault_addr = va;
1451                                 return SIGBUS;
1452                         }
1453                         if (__get_user(val, va)) {
1454                                 MIPS_FPU_EMU_INC_STATS(errors);
1455                                 *fault_addr = va;
1456                                 return SIGSEGV;
1457                         }
1458                         SITOREG(val, MIPSInst_FD(ir));
1459                         break;
1460
1461                 case swxc1_op:
1462                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1463                                 xcp->regs[MIPSInst_FT(ir)]);
1464
1465                         MIPS_FPU_EMU_INC_STATS(stores);
1466
1467                         SIFROMREG(val, MIPSInst_FS(ir));
1468                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1469                                 MIPS_FPU_EMU_INC_STATS(errors);
1470                                 *fault_addr = va;
1471                                 return SIGBUS;
1472                         }
1473                         if (put_user(val, va)) {
1474                                 MIPS_FPU_EMU_INC_STATS(errors);
1475                                 *fault_addr = va;
1476                                 return SIGSEGV;
1477                         }
1478                         break;
1479
1480                 case madd_s_op:
1481                         handler = fpemu_sp_madd;
1482                         goto scoptop;
1483                 case msub_s_op:
1484                         handler = fpemu_sp_msub;
1485                         goto scoptop;
1486                 case nmadd_s_op:
1487                         handler = fpemu_sp_nmadd;
1488                         goto scoptop;
1489                 case nmsub_s_op:
1490                         handler = fpemu_sp_nmsub;
1491                         goto scoptop;
1492
1493                       scoptop:
1494                         SPFROMREG(fr, MIPSInst_FR(ir));
1495                         SPFROMREG(fs, MIPSInst_FS(ir));
1496                         SPFROMREG(ft, MIPSInst_FT(ir));
1497                         fd = (*handler) (fr, fs, ft);
1498                         SPTOREG(fd, MIPSInst_FD(ir));
1499
1500                       copcsr:
1501                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1502                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1503                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1504                         }
1505                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1506                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1507                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1508                         }
1509                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1510                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1511                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1512                         }
1513                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1514                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1515                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1516                         }
1517
1518                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1519                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1520                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1521                                    ctx->fcr31); */
1522                                 return SIGFPE;
1523                         }
1524
1525                         break;
1526
1527                 default:
1528                         return SIGILL;
1529                 }
1530                 break;
1531         }
1532
1533         case d_fmt:{            /* 1 */
1534                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1535                 union ieee754dp fd, fr, fs, ft;
1536                 u64 __user *va;
1537                 u64 val;
1538
1539                 switch (MIPSInst_FUNC(ir)) {
1540                 case ldxc1_op:
1541                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1542                                 xcp->regs[MIPSInst_FT(ir)]);
1543
1544                         MIPS_FPU_EMU_INC_STATS(loads);
1545                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1546                                 MIPS_FPU_EMU_INC_STATS(errors);
1547                                 *fault_addr = va;
1548                                 return SIGBUS;
1549                         }
1550                         if (__get_user(val, va)) {
1551                                 MIPS_FPU_EMU_INC_STATS(errors);
1552                                 *fault_addr = va;
1553                                 return SIGSEGV;
1554                         }
1555                         DITOREG(val, MIPSInst_FD(ir));
1556                         break;
1557
1558                 case sdxc1_op:
1559                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1560                                 xcp->regs[MIPSInst_FT(ir)]);
1561
1562                         MIPS_FPU_EMU_INC_STATS(stores);
1563                         DIFROMREG(val, MIPSInst_FS(ir));
1564                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1565                                 MIPS_FPU_EMU_INC_STATS(errors);
1566                                 *fault_addr = va;
1567                                 return SIGBUS;
1568                         }
1569                         if (__put_user(val, va)) {
1570                                 MIPS_FPU_EMU_INC_STATS(errors);
1571                                 *fault_addr = va;
1572                                 return SIGSEGV;
1573                         }
1574                         break;
1575
1576                 case madd_d_op:
1577                         handler = fpemu_dp_madd;
1578                         goto dcoptop;
1579                 case msub_d_op:
1580                         handler = fpemu_dp_msub;
1581                         goto dcoptop;
1582                 case nmadd_d_op:
1583                         handler = fpemu_dp_nmadd;
1584                         goto dcoptop;
1585                 case nmsub_d_op:
1586                         handler = fpemu_dp_nmsub;
1587                         goto dcoptop;
1588
1589                       dcoptop:
1590                         DPFROMREG(fr, MIPSInst_FR(ir));
1591                         DPFROMREG(fs, MIPSInst_FS(ir));
1592                         DPFROMREG(ft, MIPSInst_FT(ir));
1593                         fd = (*handler) (fr, fs, ft);
1594                         DPTOREG(fd, MIPSInst_FD(ir));
1595                         goto copcsr;
1596
1597                 default:
1598                         return SIGILL;
1599                 }
1600                 break;
1601         }
1602
1603         case 0x3:
1604                 if (MIPSInst_FUNC(ir) != pfetch_op)
1605                         return SIGILL;
1606
1607                 /* ignore prefx operation */
1608                 break;
1609
1610         default:
1611                 return SIGILL;
1612         }
1613
1614         return 0;
1615 }
1616
1617
1618
1619 /*
1620  * Emulate a single COP1 arithmetic instruction.
1621  */
1622 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1623         mips_instruction ir)
1624 {
1625         int rfmt;               /* resulting format */
1626         unsigned rcsr = 0;      /* resulting csr */
1627         unsigned int oldrm;
1628         unsigned int cbit;
1629         unsigned cond;
1630         union {
1631                 union ieee754dp d;
1632                 union ieee754sp s;
1633                 int w;
1634                 s64 l;
1635         } rv;                   /* resulting value */
1636         u64 bits;
1637
1638         MIPS_FPU_EMU_INC_STATS(cp1ops);
1639         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1640         case s_fmt: {           /* 0 */
1641                 union {
1642                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1643                         union ieee754sp(*u) (union ieee754sp);
1644                 } handler;
1645                 union ieee754sp fs, ft;
1646
1647                 switch (MIPSInst_FUNC(ir)) {
1648                         /* binary ops */
1649                 case fadd_op:
1650                         handler.b = ieee754sp_add;
1651                         goto scopbop;
1652                 case fsub_op:
1653                         handler.b = ieee754sp_sub;
1654                         goto scopbop;
1655                 case fmul_op:
1656                         handler.b = ieee754sp_mul;
1657                         goto scopbop;
1658                 case fdiv_op:
1659                         handler.b = ieee754sp_div;
1660                         goto scopbop;
1661
1662                         /* unary  ops */
1663                 case fsqrt_op:
1664                         if (!cpu_has_mips_2_3_4_5_r)
1665                                 return SIGILL;
1666
1667                         handler.u = ieee754sp_sqrt;
1668                         goto scopuop;
1669
1670                 /*
1671                  * Note that on some MIPS IV implementations such as the
1672                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1673                  * achieve full IEEE-754 accuracy - however this emulator does.
1674                  */
1675                 case frsqrt_op:
1676                         if (!cpu_has_mips_4_5_64_r2_r6)
1677                                 return SIGILL;
1678
1679                         handler.u = fpemu_sp_rsqrt;
1680                         goto scopuop;
1681
1682                 case frecip_op:
1683                         if (!cpu_has_mips_4_5_64_r2_r6)
1684                                 return SIGILL;
1685
1686                         handler.u = fpemu_sp_recip;
1687                         goto scopuop;
1688
1689                 case fmovc_op:
1690                         if (!cpu_has_mips_4_5_r)
1691                                 return SIGILL;
1692
1693                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1694                         if (((ctx->fcr31 & cond) != 0) !=
1695                                 ((MIPSInst_FT(ir) & 1) != 0))
1696                                 return 0;
1697                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1698                         break;
1699
1700                 case fmovz_op:
1701                         if (!cpu_has_mips_4_5_r)
1702                                 return SIGILL;
1703
1704                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1705                                 return 0;
1706                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1707                         break;
1708
1709                 case fmovn_op:
1710                         if (!cpu_has_mips_4_5_r)
1711                                 return SIGILL;
1712
1713                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1714                                 return 0;
1715                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1716                         break;
1717
1718                 case fabs_op:
1719                         handler.u = ieee754sp_abs;
1720                         goto scopuop;
1721
1722                 case fneg_op:
1723                         handler.u = ieee754sp_neg;
1724                         goto scopuop;
1725
1726                 case fmov_op:
1727                         /* an easy one */
1728                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1729                         goto copcsr;
1730
1731                         /* binary op on handler */
1732 scopbop:
1733                         SPFROMREG(fs, MIPSInst_FS(ir));
1734                         SPFROMREG(ft, MIPSInst_FT(ir));
1735
1736                         rv.s = (*handler.b) (fs, ft);
1737                         goto copcsr;
1738 scopuop:
1739                         SPFROMREG(fs, MIPSInst_FS(ir));
1740                         rv.s = (*handler.u) (fs);
1741                         goto copcsr;
1742 copcsr:
1743                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1744                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1745                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1746                         }
1747                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1748                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1749                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1750                         }
1751                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1752                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1753                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1754                         }
1755                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1756                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1757                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1758                         }
1759                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1760                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1761                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1762                         }
1763                         break;
1764
1765                         /* unary conv ops */
1766                 case fcvts_op:
1767                         return SIGILL;  /* not defined */
1768
1769                 case fcvtd_op:
1770                         SPFROMREG(fs, MIPSInst_FS(ir));
1771                         rv.d = ieee754dp_fsp(fs);
1772                         rfmt = d_fmt;
1773                         goto copcsr;
1774
1775                 case fcvtw_op:
1776                         SPFROMREG(fs, MIPSInst_FS(ir));
1777                         rv.w = ieee754sp_tint(fs);
1778                         rfmt = w_fmt;
1779                         goto copcsr;
1780
1781                 case fround_op:
1782                 case ftrunc_op:
1783                 case fceil_op:
1784                 case ffloor_op:
1785                         if (!cpu_has_mips_2_3_4_5_r)
1786                                 return SIGILL;
1787
1788                         oldrm = ieee754_csr.rm;
1789                         SPFROMREG(fs, MIPSInst_FS(ir));
1790                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1791                         rv.w = ieee754sp_tint(fs);
1792                         ieee754_csr.rm = oldrm;
1793                         rfmt = w_fmt;
1794                         goto copcsr;
1795
1796                 case fcvtl_op:
1797                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1798                                 return SIGILL;
1799
1800                         SPFROMREG(fs, MIPSInst_FS(ir));
1801                         rv.l = ieee754sp_tlong(fs);
1802                         rfmt = l_fmt;
1803                         goto copcsr;
1804
1805                 case froundl_op:
1806                 case ftruncl_op:
1807                 case fceill_op:
1808                 case ffloorl_op:
1809                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1810                                 return SIGILL;
1811
1812                         oldrm = ieee754_csr.rm;
1813                         SPFROMREG(fs, MIPSInst_FS(ir));
1814                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1815                         rv.l = ieee754sp_tlong(fs);
1816                         ieee754_csr.rm = oldrm;
1817                         rfmt = l_fmt;
1818                         goto copcsr;
1819
1820                 default:
1821                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1822                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1823                                 union ieee754sp fs, ft;
1824
1825                                 SPFROMREG(fs, MIPSInst_FS(ir));
1826                                 SPFROMREG(ft, MIPSInst_FT(ir));
1827                                 rv.w = ieee754sp_cmp(fs, ft,
1828                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1829                                 rfmt = -1;
1830                                 if ((cmpop & 0x8) && ieee754_cxtest
1831                                         (IEEE754_INVALID_OPERATION))
1832                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1833                                 else
1834                                         goto copcsr;
1835
1836                         } else
1837                                 return SIGILL;
1838                         break;
1839                 }
1840                 break;
1841         }
1842
1843         case d_fmt: {
1844                 union ieee754dp fs, ft;
1845                 union {
1846                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1847                         union ieee754dp(*u) (union ieee754dp);
1848                 } handler;
1849
1850                 switch (MIPSInst_FUNC(ir)) {
1851                         /* binary ops */
1852                 case fadd_op:
1853                         handler.b = ieee754dp_add;
1854                         goto dcopbop;
1855                 case fsub_op:
1856                         handler.b = ieee754dp_sub;
1857                         goto dcopbop;
1858                 case fmul_op:
1859                         handler.b = ieee754dp_mul;
1860                         goto dcopbop;
1861                 case fdiv_op:
1862                         handler.b = ieee754dp_div;
1863                         goto dcopbop;
1864
1865                         /* unary  ops */
1866                 case fsqrt_op:
1867                         if (!cpu_has_mips_2_3_4_5_r)
1868                                 return SIGILL;
1869
1870                         handler.u = ieee754dp_sqrt;
1871                         goto dcopuop;
1872                 /*
1873                  * Note that on some MIPS IV implementations such as the
1874                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1875                  * achieve full IEEE-754 accuracy - however this emulator does.
1876                  */
1877                 case frsqrt_op:
1878                         if (!cpu_has_mips_4_5_64_r2_r6)
1879                                 return SIGILL;
1880
1881                         handler.u = fpemu_dp_rsqrt;
1882                         goto dcopuop;
1883                 case frecip_op:
1884                         if (!cpu_has_mips_4_5_64_r2_r6)
1885                                 return SIGILL;
1886
1887                         handler.u = fpemu_dp_recip;
1888                         goto dcopuop;
1889                 case fmovc_op:
1890                         if (!cpu_has_mips_4_5_r)
1891                                 return SIGILL;
1892
1893                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1894                         if (((ctx->fcr31 & cond) != 0) !=
1895                                 ((MIPSInst_FT(ir) & 1) != 0))
1896                                 return 0;
1897                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1898                         break;
1899                 case fmovz_op:
1900                         if (!cpu_has_mips_4_5_r)
1901                                 return SIGILL;
1902
1903                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1904                                 return 0;
1905                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1906                         break;
1907                 case fmovn_op:
1908                         if (!cpu_has_mips_4_5_r)
1909                                 return SIGILL;
1910
1911                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1912                                 return 0;
1913                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1914                         break;
1915                 case fabs_op:
1916                         handler.u = ieee754dp_abs;
1917                         goto dcopuop;
1918
1919                 case fneg_op:
1920                         handler.u = ieee754dp_neg;
1921                         goto dcopuop;
1922
1923                 case fmov_op:
1924                         /* an easy one */
1925                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1926                         goto copcsr;
1927
1928                         /* binary op on handler */
1929 dcopbop:
1930                         DPFROMREG(fs, MIPSInst_FS(ir));
1931                         DPFROMREG(ft, MIPSInst_FT(ir));
1932
1933                         rv.d = (*handler.b) (fs, ft);
1934                         goto copcsr;
1935 dcopuop:
1936                         DPFROMREG(fs, MIPSInst_FS(ir));
1937                         rv.d = (*handler.u) (fs);
1938                         goto copcsr;
1939
1940                 /*
1941                  * unary conv ops
1942                  */
1943                 case fcvts_op:
1944                         DPFROMREG(fs, MIPSInst_FS(ir));
1945                         rv.s = ieee754sp_fdp(fs);
1946                         rfmt = s_fmt;
1947                         goto copcsr;
1948
1949                 case fcvtd_op:
1950                         return SIGILL;  /* not defined */
1951
1952                 case fcvtw_op:
1953                         DPFROMREG(fs, MIPSInst_FS(ir));
1954                         rv.w = ieee754dp_tint(fs);      /* wrong */
1955                         rfmt = w_fmt;
1956                         goto copcsr;
1957
1958                 case fround_op:
1959                 case ftrunc_op:
1960                 case fceil_op:
1961                 case ffloor_op:
1962                         if (!cpu_has_mips_2_3_4_5_r)
1963                                 return SIGILL;
1964
1965                         oldrm = ieee754_csr.rm;
1966                         DPFROMREG(fs, MIPSInst_FS(ir));
1967                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1968                         rv.w = ieee754dp_tint(fs);
1969                         ieee754_csr.rm = oldrm;
1970                         rfmt = w_fmt;
1971                         goto copcsr;
1972
1973                 case fcvtl_op:
1974                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1975                                 return SIGILL;
1976
1977                         DPFROMREG(fs, MIPSInst_FS(ir));
1978                         rv.l = ieee754dp_tlong(fs);
1979                         rfmt = l_fmt;
1980                         goto copcsr;
1981
1982                 case froundl_op:
1983                 case ftruncl_op:
1984                 case fceill_op:
1985                 case ffloorl_op:
1986                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1987                                 return SIGILL;
1988
1989                         oldrm = ieee754_csr.rm;
1990                         DPFROMREG(fs, MIPSInst_FS(ir));
1991                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1992                         rv.l = ieee754dp_tlong(fs);
1993                         ieee754_csr.rm = oldrm;
1994                         rfmt = l_fmt;
1995                         goto copcsr;
1996
1997                 default:
1998                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1999                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
2000                                 union ieee754dp fs, ft;
2001
2002                                 DPFROMREG(fs, MIPSInst_FS(ir));
2003                                 DPFROMREG(ft, MIPSInst_FT(ir));
2004                                 rv.w = ieee754dp_cmp(fs, ft,
2005                                         cmptab[cmpop & 0x7], cmpop & 0x8);
2006                                 rfmt = -1;
2007                                 if ((cmpop & 0x8)
2008                                         &&
2009                                         ieee754_cxtest
2010                                         (IEEE754_INVALID_OPERATION))
2011                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
2012                                 else
2013                                         goto copcsr;
2014
2015                         }
2016                         else {
2017                                 return SIGILL;
2018                         }
2019                         break;
2020                 }
2021                 break;
2022
2023         case w_fmt:
2024                 switch (MIPSInst_FUNC(ir)) {
2025                 case fcvts_op:
2026                         /* convert word to single precision real */
2027                         SPFROMREG(fs, MIPSInst_FS(ir));
2028                         rv.s = ieee754sp_fint(fs.bits);
2029                         rfmt = s_fmt;
2030                         goto copcsr;
2031                 case fcvtd_op:
2032                         /* convert word to double precision real */
2033                         SPFROMREG(fs, MIPSInst_FS(ir));
2034                         rv.d = ieee754dp_fint(fs.bits);
2035                         rfmt = d_fmt;
2036                         goto copcsr;
2037                 default:
2038                         return SIGILL;
2039                 }
2040                 break;
2041         }
2042
2043         case l_fmt:
2044
2045                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2046                         return SIGILL;
2047
2048                 DIFROMREG(bits, MIPSInst_FS(ir));
2049
2050                 switch (MIPSInst_FUNC(ir)) {
2051                 case fcvts_op:
2052                         /* convert long to single precision real */
2053                         rv.s = ieee754sp_flong(bits);
2054                         rfmt = s_fmt;
2055                         goto copcsr;
2056                 case fcvtd_op:
2057                         /* convert long to double precision real */
2058                         rv.d = ieee754dp_flong(bits);
2059                         rfmt = d_fmt;
2060                         goto copcsr;
2061                 default:
2062                         return SIGILL;
2063                 }
2064                 break;
2065
2066         default:
2067                 return SIGILL;
2068         }
2069
2070         /*
2071          * Update the fpu CSR register for this operation.
2072          * If an exception is required, generate a tidy SIGFPE exception,
2073          * without updating the result register.
2074          * Note: cause exception bits do not accumulate, they are rewritten
2075          * for each op; only the flag/sticky bits accumulate.
2076          */
2077         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2078         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2079                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2080                 return SIGFPE;
2081         }
2082
2083         /*
2084          * Now we can safely write the result back to the register file.
2085          */
2086         switch (rfmt) {
2087         case -1:
2088
2089                 if (cpu_has_mips_4_5_r)
2090                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2091                 else
2092                         cbit = FPU_CSR_COND;
2093                 if (rv.w)
2094                         ctx->fcr31 |= cbit;
2095                 else
2096                         ctx->fcr31 &= ~cbit;
2097                 break;
2098
2099         case d_fmt:
2100                 DPTOREG(rv.d, MIPSInst_FD(ir));
2101                 break;
2102         case s_fmt:
2103                 SPTOREG(rv.s, MIPSInst_FD(ir));
2104                 break;
2105         case w_fmt:
2106                 SITOREG(rv.w, MIPSInst_FD(ir));
2107                 break;
2108         case l_fmt:
2109                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2110                         return SIGILL;
2111
2112                 DITOREG(rv.l, MIPSInst_FD(ir));
2113                 break;
2114         default:
2115                 return SIGILL;
2116         }
2117
2118         return 0;
2119 }
2120
2121 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2122         int has_fpu, void *__user *fault_addr)
2123 {
2124         unsigned long oldepc, prevepc;
2125         struct mm_decoded_insn dec_insn;
2126         u16 instr[4];
2127         u16 *instr_ptr;
2128         int sig = 0;
2129
2130         oldepc = xcp->cp0_epc;
2131         do {
2132                 prevepc = xcp->cp0_epc;
2133
2134                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2135                         /*
2136                          * Get next 2 microMIPS instructions and convert them
2137                          * into 32-bit instructions.
2138                          */
2139                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2140                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2141                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2142                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2143                                 MIPS_FPU_EMU_INC_STATS(errors);
2144                                 return SIGBUS;
2145                         }
2146                         instr_ptr = instr;
2147
2148                         /* Get first instruction. */
2149                         if (mm_insn_16bit(*instr_ptr)) {
2150                                 /* Duplicate the half-word. */
2151                                 dec_insn.insn = (*instr_ptr << 16) |
2152                                         (*instr_ptr);
2153                                 /* 16-bit instruction. */
2154                                 dec_insn.pc_inc = 2;
2155                                 instr_ptr += 1;
2156                         } else {
2157                                 dec_insn.insn = (*instr_ptr << 16) |
2158                                         *(instr_ptr+1);
2159                                 /* 32-bit instruction. */
2160                                 dec_insn.pc_inc = 4;
2161                                 instr_ptr += 2;
2162                         }
2163                         /* Get second instruction. */
2164                         if (mm_insn_16bit(*instr_ptr)) {
2165                                 /* Duplicate the half-word. */
2166                                 dec_insn.next_insn = (*instr_ptr << 16) |
2167                                         (*instr_ptr);
2168                                 /* 16-bit instruction. */
2169                                 dec_insn.next_pc_inc = 2;
2170                         } else {
2171                                 dec_insn.next_insn = (*instr_ptr << 16) |
2172                                         *(instr_ptr+1);
2173                                 /* 32-bit instruction. */
2174                                 dec_insn.next_pc_inc = 4;
2175                         }
2176                         dec_insn.micro_mips_mode = 1;
2177                 } else {
2178                         if ((get_user(dec_insn.insn,
2179                             (mips_instruction __user *) xcp->cp0_epc)) ||
2180                             (get_user(dec_insn.next_insn,
2181                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2182                                 MIPS_FPU_EMU_INC_STATS(errors);
2183                                 return SIGBUS;
2184                         }
2185                         dec_insn.pc_inc = 4;
2186                         dec_insn.next_pc_inc = 4;
2187                         dec_insn.micro_mips_mode = 0;
2188                 }
2189
2190                 if ((dec_insn.insn == 0) ||
2191                    ((dec_insn.pc_inc == 2) &&
2192                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2193                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2194                 else {
2195                         /*
2196                          * The 'ieee754_csr' is an alias of ctx->fcr31.
2197                          * No need to copy ctx->fcr31 to ieee754_csr.
2198                          */
2199                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2200                 }
2201
2202                 if (has_fpu)
2203                         break;
2204                 if (sig)
2205                         break;
2206
2207                 cond_resched();
2208         } while (xcp->cp0_epc > prevepc);
2209
2210         /* SIGILL indicates a non-fpu instruction */
2211         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2212                 /* but if EPC has advanced, then ignore it */
2213                 sig = 0;
2214
2215         return sig;
2216 }