arch/mips/math-emu/cp1emu.c

   1 /*
   2  * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
   3  *
   4  * MIPS floating point support
   5  * Copyright (C) 1994-2000 Algorithmics Ltd.
   6  *
   7  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
   8  * Copyright (C) 2000  MIPS Technologies, Inc.
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
  22  *
  23  * A complete emulator for MIPS coprocessor 1 instructions.  This is
  24  * required for #float(switch) or #float(trap), where it catches all
  25  * COP1 instructions via the "CoProcessor Unusable" exception.
  26  *
  27  * More surprisingly it is also required for #float(ieee), to help out
  28  * the hardware FPU at the boundaries of the IEEE-754 representation
  29  * (denormalised values, infinities, underflow, etc).  It is made
  30  * quite nasty because emulation of some non-COP1 instructions is
  31  * required, e.g. in branch delay slots.
  32  *
  33  * Note if you know that you won't have an FPU, then you'll get much
  34  * better performance by compiling with -msoft-float!
  35  */
  36 #include <linux/sched.h>
  37 #include <linux/debugfs.h>
  38 #include <linux/kconfig.h>
  39 #include <linux/percpu-defs.h>
  40 #include <linux/perf_event.h>
  41
  42 #include <asm/branch.h>
  43 #include <asm/inst.h>
  44 #include <asm/ptrace.h>
  45 #include <asm/signal.h>
  46 #include <asm/uaccess.h>
  47
  48 #include <asm/cpu-info.h>
  49 #include <asm/processor.h>
  50 #include <asm/fpu_emulator.h>
  51 #include <asm/fpu.h>
  52 #include <asm/mips-r2-to-r6-emul.h>
  53
  54 #include "ieee754.h"
  55
  56 /* Function which emulates a floating point instruction. */
  57
  58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
  59         mips_instruction);
  60
  61 static int fpux_emu(struct pt_regs *,
  62         struct mips_fpu_struct *, mips_instruction, void *__user *);
  63
  64 /* Control registers */
  65
  66 #define FPCREG_RID      0       /* $0  = revision id */
  67 #define FPCREG_CSR      31      /* $31 = csr */
  68
  69 /* convert condition code register number to csr bit */
  70 const unsigned int fpucondbit[8] = {
  71         FPU_CSR_COND0,
  72         FPU_CSR_COND1,
  73         FPU_CSR_COND2,
  74         FPU_CSR_COND3,
  75         FPU_CSR_COND4,
  76         FPU_CSR_COND5,
  77         FPU_CSR_COND6,
  78         FPU_CSR_COND7
  79 };
  80
  81 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
  82 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
  83 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
  84 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
  85 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
  86
  87 /*
  88  * This functions translates a 32-bit microMIPS instruction
  89  * into a 32-bit MIPS32 instruction. Returns 0 on success
  90  * and SIGILL otherwise.
  91  */
  92 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
  93 {
  94         union mips_instruction insn = *insn_ptr;
  95         union mips_instruction mips32_insn = insn;
  96         int func, fmt, op;
  97
  98         switch (insn.mm_i_format.opcode) {
  99         case mm_ldc132_op:
 100                 mips32_insn.mm_i_format.opcode = ldc1_op;
 101                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 102                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 103                 break;
 104         case mm_lwc132_op:
 105                 mips32_insn.mm_i_format.opcode = lwc1_op;
 106                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 107                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 108                 break;
 109         case mm_sdc132_op:
 110                 mips32_insn.mm_i_format.opcode = sdc1_op;
 111                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 112                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 113                 break;
 114         case mm_swc132_op:
 115                 mips32_insn.mm_i_format.opcode = swc1_op;
 116                 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
 117                 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
 118                 break;
 119         case mm_pool32i_op:
 120                 /* NOTE: offset is << by 1 if in microMIPS mode. */
 121                 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
 122                     (insn.mm_i_format.rt == mm_bc1t_op)) {
 123                         mips32_insn.fb_format.opcode = cop1_op;
 124                         mips32_insn.fb_format.bc = bc_op;
 125                         mips32_insn.fb_format.flag =
 126                                 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
 127                 } else
 128                         return SIGILL;
 129                 break;
 130         case mm_pool32f_op:
 131                 switch (insn.mm_fp0_format.func) {
 132                 case mm_32f_01_op:
 133                 case mm_32f_11_op:
 134                 case mm_32f_02_op:
 135                 case mm_32f_12_op:
 136                 case mm_32f_41_op:
 137                 case mm_32f_51_op:
 138                 case mm_32f_42_op:
 139                 case mm_32f_52_op:
 140                         op = insn.mm_fp0_format.func;
 141                         if (op == mm_32f_01_op)
 142                                 func = madd_s_op;
 143                         else if (op == mm_32f_11_op)
 144                                 func = madd_d_op;
 145                         else if (op == mm_32f_02_op)
 146                                 func = nmadd_s_op;
 147                         else if (op == mm_32f_12_op)
 148                                 func = nmadd_d_op;
 149                         else if (op == mm_32f_41_op)
 150                                 func = msub_s_op;
 151                         else if (op == mm_32f_51_op)
 152                                 func = msub_d_op;
 153                         else if (op == mm_32f_42_op)
 154                                 func = nmsub_s_op;
 155                         else
 156                                 func = nmsub_d_op;
 157                         mips32_insn.fp6_format.opcode = cop1x_op;
 158                         mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
 159                         mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
 160                         mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
 161                         mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
 162                         mips32_insn.fp6_format.func = func;
 163                         break;
 164                 case mm_32f_10_op:
 165                         func = -1;      /* Invalid */
 166                         op = insn.mm_fp5_format.op & 0x7;
 167                         if (op == mm_ldxc1_op)
 168                                 func = ldxc1_op;
 169                         else if (op == mm_sdxc1_op)
 170                                 func = sdxc1_op;
 171                         else if (op == mm_lwxc1_op)
 172                                 func = lwxc1_op;
 173                         else if (op == mm_swxc1_op)
 174                                 func = swxc1_op;
 175
 176                         if (func != -1) {
 177                                 mips32_insn.r_format.opcode = cop1x_op;
 178                                 mips32_insn.r_format.rs =
 179                                         insn.mm_fp5_format.base;
 180                                 mips32_insn.r_format.rt =
 181                                         insn.mm_fp5_format.index;
 182                                 mips32_insn.r_format.rd = 0;
 183                                 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
 184                                 mips32_insn.r_format.func = func;
 185                         } else
 186                                 return SIGILL;
 187                         break;
 188                 case mm_32f_40_op:
 189                         op = -1;        /* Invalid */
 190                         if (insn.mm_fp2_format.op == mm_fmovt_op)
 191                                 op = 1;
 192                         else if (insn.mm_fp2_format.op == mm_fmovf_op)
 193                                 op = 0;
 194                         if (op != -1) {
 195                                 mips32_insn.fp0_format.opcode = cop1_op;
 196                                 mips32_insn.fp0_format.fmt =
 197                                         sdps_format[insn.mm_fp2_format.fmt];
 198                                 mips32_insn.fp0_format.ft =
 199                                         (insn.mm_fp2_format.cc<<2) + op;
 200                                 mips32_insn.fp0_format.fs =
 201                                         insn.mm_fp2_format.fs;
 202                                 mips32_insn.fp0_format.fd =
 203                                         insn.mm_fp2_format.fd;
 204                                 mips32_insn.fp0_format.func = fmovc_op;
 205                         } else
 206                                 return SIGILL;
 207                         break;
 208                 case mm_32f_60_op:
 209                         func = -1;      /* Invalid */
 210                         if (insn.mm_fp0_format.op == mm_fadd_op)
 211                                 func = fadd_op;
 212                         else if (insn.mm_fp0_format.op == mm_fsub_op)
 213                                 func = fsub_op;
 214                         else if (insn.mm_fp0_format.op == mm_fmul_op)
 215                                 func = fmul_op;
 216                         else if (insn.mm_fp0_format.op == mm_fdiv_op)
 217                                 func = fdiv_op;
 218                         if (func != -1) {
 219                                 mips32_insn.fp0_format.opcode = cop1_op;
 220                                 mips32_insn.fp0_format.fmt =
 221                                         sdps_format[insn.mm_fp0_format.fmt];
 222                                 mips32_insn.fp0_format.ft =
 223                                         insn.mm_fp0_format.ft;
 224                                 mips32_insn.fp0_format.fs =
 225                                         insn.mm_fp0_format.fs;
 226                                 mips32_insn.fp0_format.fd =
 227                                         insn.mm_fp0_format.fd;
 228                                 mips32_insn.fp0_format.func = func;
 229                         } else
 230                                 return SIGILL;
 231                         break;
 232                 case mm_32f_70_op:
 233                         func = -1;      /* Invalid */
 234                         if (insn.mm_fp0_format.op == mm_fmovn_op)
 235                                 func = fmovn_op;
 236                         else if (insn.mm_fp0_format.op == mm_fmovz_op)
 237                                 func = fmovz_op;
 238                         if (func != -1) {
 239                                 mips32_insn.fp0_format.opcode = cop1_op;
 240                                 mips32_insn.fp0_format.fmt =
 241                                         sdps_format[insn.mm_fp0_format.fmt];
 242                                 mips32_insn.fp0_format.ft =
 243                                         insn.mm_fp0_format.ft;
 244                                 mips32_insn.fp0_format.fs =
 245                                         insn.mm_fp0_format.fs;
 246                                 mips32_insn.fp0_format.fd =
 247                                         insn.mm_fp0_format.fd;
 248                                 mips32_insn.fp0_format.func = func;
 249                         } else
 250                                 return SIGILL;
 251                         break;
 252                 case mm_32f_73_op:    /* POOL32FXF */
 253                         switch (insn.mm_fp1_format.op) {
 254                         case mm_movf0_op:
 255                         case mm_movf1_op:
 256                         case mm_movt0_op:
 257                         case mm_movt1_op:
 258                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 259                                     mm_movf0_op)
 260                                         op = 0;
 261                                 else
 262                                         op = 1;
 263                                 mips32_insn.r_format.opcode = spec_op;
 264                                 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
 265                                 mips32_insn.r_format.rt =
 266                                         (insn.mm_fp4_format.cc << 2) + op;
 267                                 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
 268                                 mips32_insn.r_format.re = 0;
 269                                 mips32_insn.r_format.func = movc_op;
 270                                 break;
 271                         case mm_fcvtd0_op:
 272                         case mm_fcvtd1_op:
 273                         case mm_fcvts0_op:
 274                         case mm_fcvts1_op:
 275                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 276                                     mm_fcvtd0_op) {
 277                                         func = fcvtd_op;
 278                                         fmt = swl_format[insn.mm_fp3_format.fmt];
 279                                 } else {
 280                                         func = fcvts_op;
 281                                         fmt = dwl_format[insn.mm_fp3_format.fmt];
 282                                 }
 283                                 mips32_insn.fp0_format.opcode = cop1_op;
 284                                 mips32_insn.fp0_format.fmt = fmt;
 285                                 mips32_insn.fp0_format.ft = 0;
 286                                 mips32_insn.fp0_format.fs =
 287                                         insn.mm_fp3_format.fs;
 288                                 mips32_insn.fp0_format.fd =
 289                                         insn.mm_fp3_format.rt;
 290                                 mips32_insn.fp0_format.func = func;
 291                                 break;
 292                         case mm_fmov0_op:
 293                         case mm_fmov1_op:
 294                         case mm_fabs0_op:
 295                         case mm_fabs1_op:
 296                         case mm_fneg0_op:
 297                         case mm_fneg1_op:
 298                                 if ((insn.mm_fp1_format.op & 0x7f) ==
 299                                     mm_fmov0_op)
 300                                         func = fmov_op;
 301                                 else if ((insn.mm_fp1_format.op & 0x7f) ==
 302                                          mm_fabs0_op)
 303                                         func = fabs_op;
 304                                 else
 305                                         func = fneg_op;
 306                                 mips32_insn.fp0_format.opcode = cop1_op;
 307                                 mips32_insn.fp0_format.fmt =
 308                                         sdps_format[insn.mm_fp3_format.fmt];
 309                                 mips32_insn.fp0_format.ft = 0;
 310                                 mips32_insn.fp0_format.fs =
 311                                         insn.mm_fp3_format.fs;
 312                                 mips32_insn.fp0_format.fd =
 313                                         insn.mm_fp3_format.rt;
 314                                 mips32_insn.fp0_format.func = func;
 315                                 break;
 316                         case mm_ffloorl_op:
 317                         case mm_ffloorw_op:
 318                         case mm_fceill_op:
 319                         case mm_fceilw_op:
 320                         case mm_ftruncl_op:
 321                         case mm_ftruncw_op:
 322                         case mm_froundl_op:
 323                         case mm_froundw_op:
 324                         case mm_fcvtl_op:
 325                         case mm_fcvtw_op:
 326                                 if (insn.mm_fp1_format.op == mm_ffloorl_op)
 327                                         func = ffloorl_op;
 328                                 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
 329                                         func = ffloor_op;
 330                                 else if (insn.mm_fp1_format.op == mm_fceill_op)
 331                                         func = fceill_op;
 332                                 else if (insn.mm_fp1_format.op == mm_fceilw_op)
 333                                         func = fceil_op;
 334                                 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
 335                                         func = ftruncl_op;
 336                                 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
 337                                         func = ftrunc_op;
 338                                 else if (insn.mm_fp1_format.op == mm_froundl_op)
 339                                         func = froundl_op;
 340                                 else if (insn.mm_fp1_format.op == mm_froundw_op)
 341                                         func = fround_op;
 342                                 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
 343                                         func = fcvtl_op;
 344                                 else
 345                                         func = fcvtw_op;
 346                                 mips32_insn.fp0_format.opcode = cop1_op;
 347                                 mips32_insn.fp0_format.fmt =
 348                                         sd_format[insn.mm_fp1_format.fmt];
 349                                 mips32_insn.fp0_format.ft = 0;
 350                                 mips32_insn.fp0_format.fs =
 351                                         insn.mm_fp1_format.fs;
 352                                 mips32_insn.fp0_format.fd =
 353                                         insn.mm_fp1_format.rt;
 354                                 mips32_insn.fp0_format.func = func;
 355                                 break;
 356                         case mm_frsqrt_op:
 357                         case mm_fsqrt_op:
 358                         case mm_frecip_op:
 359                                 if (insn.mm_fp1_format.op == mm_frsqrt_op)
 360                                         func = frsqrt_op;
 361                                 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
 362                                         func = fsqrt_op;
 363                                 else
 364                                         func = frecip_op;
 365                                 mips32_insn.fp0_format.opcode = cop1_op;
 366                                 mips32_insn.fp0_format.fmt =
 367                                         sdps_format[insn.mm_fp1_format.fmt];
 368                                 mips32_insn.fp0_format.ft = 0;
 369                                 mips32_insn.fp0_format.fs =
 370                                         insn.mm_fp1_format.fs;
 371                                 mips32_insn.fp0_format.fd =
 372                                         insn.mm_fp1_format.rt;
 373                                 mips32_insn.fp0_format.func = func;
 374                                 break;
 375                         case mm_mfc1_op:
 376                         case mm_mtc1_op:
 377                         case mm_cfc1_op:
 378                         case mm_ctc1_op:
 379                         case mm_mfhc1_op:
 380                         case mm_mthc1_op:
 381                                 if (insn.mm_fp1_format.op == mm_mfc1_op)
 382                                         op = mfc_op;
 383                                 else if (insn.mm_fp1_format.op == mm_mtc1_op)
 384                                         op = mtc_op;
 385                                 else if (insn.mm_fp1_format.op == mm_cfc1_op)
 386                                         op = cfc_op;
 387                                 else if (insn.mm_fp1_format.op == mm_ctc1_op)
 388                                         op = ctc_op;
 389                                 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
 390                                         op = mfhc_op;
 391                                 else
 392                                         op = mthc_op;
 393                                 mips32_insn.fp1_format.opcode = cop1_op;
 394                                 mips32_insn.fp1_format.op = op;
 395                                 mips32_insn.fp1_format.rt =
 396                                         insn.mm_fp1_format.rt;
 397                                 mips32_insn.fp1_format.fs =
 398                                         insn.mm_fp1_format.fs;
 399                                 mips32_insn.fp1_format.fd = 0;
 400                                 mips32_insn.fp1_format.func = 0;
 401                                 break;
 402                         default:
 403                                 return SIGILL;
 404                         }
 405                         break;
 406                 case mm_32f_74_op:      /* c.cond.fmt */
 407                         mips32_insn.fp0_format.opcode = cop1_op;
 408                         mips32_insn.fp0_format.fmt =
 409                                 sdps_format[insn.mm_fp4_format.fmt];
 410                         mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
 411                         mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
 412                         mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
 413                         mips32_insn.fp0_format.func =
 414                                 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
 415                         break;
 416                 default:
 417                         return SIGILL;
 418                 }
 419                 break;
 420         default:
 421                 return SIGILL;
 422         }
 423
 424         *insn_ptr = mips32_insn;
 425         return 0;
 426 }
 427
 428 /*
 429  * Redundant with logic already in kernel/branch.c,
 430  * embedded in compute_return_epc.  At some point,
 431  * a single subroutine should be used across both
 432  * modules.
 433  */
 434 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 435                          unsigned long *contpc)
 436 {
 437         union mips_instruction insn = (union mips_instruction)dec_insn.insn;
 438         unsigned int fcr31;
 439         unsigned int bit = 0;
 440
 441         switch (insn.i_format.opcode) {
 442         case spec_op:
 443                 switch (insn.r_format.func) {
 444                 case jalr_op:
 445                         regs->regs[insn.r_format.rd] =
 446                                 regs->cp0_epc + dec_insn.pc_inc +
 447                                 dec_insn.next_pc_inc;
 448                         /* Fall through */
 449                 case jr_op:
 450                         /* For R6, JR already emulated in jalr_op */
 451                         if (NO_R6EMU && insn.r_format.opcode == jr_op)
 452                                 break;
 453                         *contpc = regs->regs[insn.r_format.rs];
 454                         return 1;
 455                 }
 456                 break;
 457         case bcond_op:
 458                 switch (insn.i_format.rt) {
 459                 case bltzal_op:
 460                 case bltzall_op:
 461                         if (NO_R6EMU && (insn.i_format.rs ||
 462                             insn.i_format.rt == bltzall_op))
 463                                 break;
 464
 465                         regs->regs[31] = regs->cp0_epc +
 466                                 dec_insn.pc_inc +
 467                                 dec_insn.next_pc_inc;
 468                         /* Fall through */
 469                 case bltzl_op:
 470                         if (NO_R6EMU)
 471                                 break;
 472                 case bltz_op:
 473                         if ((long)regs->regs[insn.i_format.rs] < 0)
 474                                 *contpc = regs->cp0_epc +
 475                                         dec_insn.pc_inc +
 476                                         (insn.i_format.simmediate << 2);
 477                         else
 478                                 *contpc = regs->cp0_epc +
 479                                         dec_insn.pc_inc +
 480                                         dec_insn.next_pc_inc;
 481                         return 1;
 482                 case bgezal_op:
 483                 case bgezall_op:
 484                         if (NO_R6EMU && (insn.i_format.rs ||
 485                             insn.i_format.rt == bgezall_op))
 486                                 break;
 487
 488                         regs->regs[31] = regs->cp0_epc +
 489                                 dec_insn.pc_inc +
 490                                 dec_insn.next_pc_inc;
 491                         /* Fall through */
 492                 case bgezl_op:
 493                         if (NO_R6EMU)
 494                                 break;
 495                 case bgez_op:
 496                         if ((long)regs->regs[insn.i_format.rs] >= 0)
 497                                 *contpc = regs->cp0_epc +
 498                                         dec_insn.pc_inc +
 499                                         (insn.i_format.simmediate << 2);
 500                         else
 501                                 *contpc = regs->cp0_epc +
 502                                         dec_insn.pc_inc +
 503                                         dec_insn.next_pc_inc;
 504                         return 1;
 505                 }
 506                 break;
 507         case jalx_op:
 508                 set_isa16_mode(bit);
 509         case jal_op:
 510                 regs->regs[31] = regs->cp0_epc +
 511                         dec_insn.pc_inc +
 512                         dec_insn.next_pc_inc;
 513                 /* Fall through */
 514         case j_op:
 515                 *contpc = regs->cp0_epc + dec_insn.pc_inc;
 516                 *contpc >>= 28;
 517                 *contpc <<= 28;
 518                 *contpc |= (insn.j_format.target << 2);
 519                 /* Set microMIPS mode bit: XOR for jalx. */
 520                 *contpc ^= bit;
 521                 return 1;
 522         case beql_op:
 523                 if (NO_R6EMU)
 524                         break;
 525         case beq_op:
 526                 if (regs->regs[insn.i_format.rs] ==
 527                     regs->regs[insn.i_format.rt])
 528                         *contpc = regs->cp0_epc +
 529                                 dec_insn.pc_inc +
 530                                 (insn.i_format.simmediate << 2);
 531                 else
 532                         *contpc = regs->cp0_epc +
 533                                 dec_insn.pc_inc +
 534                                 dec_insn.next_pc_inc;
 535                 return 1;
 536         case bnel_op:
 537                 if (NO_R6EMU)
 538                         break;
 539         case bne_op:
 540                 if (regs->regs[insn.i_format.rs] !=
 541                     regs->regs[insn.i_format.rt])
 542                         *contpc = regs->cp0_epc +
 543                                 dec_insn.pc_inc +
 544                                 (insn.i_format.simmediate << 2);
 545                 else
 546                         *contpc = regs->cp0_epc +
 547                                 dec_insn.pc_inc +
 548                                 dec_insn.next_pc_inc;
 549                 return 1;
 550         case blezl_op:
 551                 if (NO_R6EMU)
 552                         break;
 553         case blez_op:
 554
 555                 /*
 556                  * Compact branches for R6 for the
 557                  * blez and blezl opcodes.
 558                  * BLEZ  | rs = 0 | rt != 0  == BLEZALC
 559                  * BLEZ  | rs = rt != 0      == BGEZALC
 560                  * BLEZ  | rs != 0 | rt != 0 == BGEUC
 561                  * BLEZL | rs = 0 | rt != 0  == BLEZC
 562                  * BLEZL | rs = rt != 0      == BGEZC
 563                  * BLEZL | rs != 0 | rt != 0 == BGEC
 564                  *
 565                  * For real BLEZ{,L}, rt is always 0.
 566                  */
 567                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 568                         if ((insn.i_format.opcode == blez_op) &&
 569                             ((!insn.i_format.rs && insn.i_format.rt) ||
 570                              (insn.i_format.rs == insn.i_format.rt)))
 571                                 regs->regs[31] = regs->cp0_epc +
 572                                         dec_insn.pc_inc;
 573                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 574                                 dec_insn.next_pc_inc;
 575
 576                         return 1;
 577                 }
 578                 if ((long)regs->regs[insn.i_format.rs] <= 0)
 579                         *contpc = regs->cp0_epc +
 580                                 dec_insn.pc_inc +
 581                                 (insn.i_format.simmediate << 2);
 582                 else
 583                         *contpc = regs->cp0_epc +
 584                                 dec_insn.pc_inc +
 585                                 dec_insn.next_pc_inc;
 586                 return 1;
 587         case bgtzl_op:
 588                 if (NO_R6EMU)
 589                         break;
 590         case bgtz_op:
 591                 /*
 592                  * Compact branches for R6 for the
 593                  * bgtz and bgtzl opcodes.
 594                  * BGTZ  | rs = 0 | rt != 0  == BGTZALC
 595                  * BGTZ  | rs = rt != 0      == BLTZALC
 596                  * BGTZ  | rs != 0 | rt != 0 == BLTUC
 597                  * BGTZL | rs = 0 | rt != 0  == BGTZC
 598                  * BGTZL | rs = rt != 0      == BLTZC
 599                  * BGTZL | rs != 0 | rt != 0 == BLTC
 600                  *
 601                  * *ZALC varint for BGTZ &&& rt != 0
 602                  * For real GTZ{,L}, rt is always 0.
 603                  */
 604                 if (cpu_has_mips_r6 && insn.i_format.rt) {
 605                         if ((insn.i_format.opcode == blez_op) &&
 606                             ((!insn.i_format.rs && insn.i_format.rt) ||
 607                              (insn.i_format.rs == insn.i_format.rt)))
 608                                 regs->regs[31] = regs->cp0_epc +
 609                                         dec_insn.pc_inc;
 610                         *contpc = regs->cp0_epc + dec_insn.pc_inc +
 611                                 dec_insn.next_pc_inc;
 612
 613                         return 1;
 614                 }
 615
 616                 if ((long)regs->regs[insn.i_format.rs] > 0)
 617                         *contpc = regs->cp0_epc +
 618                                 dec_insn.pc_inc +
 619                                 (insn.i_format.simmediate << 2);
 620                 else
 621                         *contpc = regs->cp0_epc +
 622                                 dec_insn.pc_inc +
 623                                 dec_insn.next_pc_inc;
 624                 return 1;
 625         case cbcond0_op:
 626         case cbcond1_op:
 627                 if (!cpu_has_mips_r6)
 628                         break;
 629                 if (insn.i_format.rt && !insn.i_format.rs)
 630                         regs->regs[31] = regs->cp0_epc + 4;
 631                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 632                         dec_insn.next_pc_inc;
 633
 634                 return 1;
 635 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 636         case lwc2_op: /* This is bbit0 on Octeon */
 637                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
 638                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 639                 else
 640                         *contpc = regs->cp0_epc + 8;
 641                 return 1;
 642         case ldc2_op: /* This is bbit032 on Octeon */
 643                 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
 644                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 645                 else
 646                         *contpc = regs->cp0_epc + 8;
 647                 return 1;
 648         case swc2_op: /* This is bbit1 on Octeon */
 649                 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
 650                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 651                 else
 652                         *contpc = regs->cp0_epc + 8;
 653                 return 1;
 654         case sdc2_op: /* This is bbit132 on Octeon */
 655                 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
 656                         *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
 657                 else
 658                         *contpc = regs->cp0_epc + 8;
 659                 return 1;
 660 #else
 661         case bc6_op:
 662                 /*
 663                  * Only valid for MIPS R6 but we can still end up
 664                  * here from a broken userland so just tell emulator
 665                  * this is not a branch and let it break later on.
 666                  */
 667                 if  (!cpu_has_mips_r6)
 668                         break;
 669                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 670                         dec_insn.next_pc_inc;
 671
 672                 return 1;
 673         case balc6_op:
 674                 if (!cpu_has_mips_r6)
 675                         break;
 676                 regs->regs[31] = regs->cp0_epc + 4;
 677                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 678                         dec_insn.next_pc_inc;
 679
 680                 return 1;
 681         case beqzcjic_op:
 682                 if (!cpu_has_mips_r6)
 683                         break;
 684                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 685                         dec_insn.next_pc_inc;
 686
 687                 return 1;
 688         case bnezcjialc_op:
 689                 if (!cpu_has_mips_r6)
 690                         break;
 691                 if (!insn.i_format.rs)
 692                         regs->regs[31] = regs->cp0_epc + 4;
 693                 *contpc = regs->cp0_epc + dec_insn.pc_inc +
 694                         dec_insn.next_pc_inc;
 695
 696                 return 1;
 697 #endif
 698         case cop0_op:
 699         case cop1_op:
 700                 /* Need to check for R6 bc1nez and bc1eqz branches */
 701                 if (cpu_has_mips_r6 &&
 702                     ((insn.i_format.rs == bc1eqz_op) ||
 703                      (insn.i_format.rs == bc1nez_op))) {
 704                         bit = 0;
 705                         switch (insn.i_format.rs) {
 706                         case bc1eqz_op:
 707                                 if (get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
 708                                     bit = 1;
 709                                 break;
 710                         case bc1nez_op:
 711                                 if (!(get_fpr32(&current->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
 712                                     bit = 1;
 713                                 break;
 714                         }
 715                         if (bit)
 716                                 *contpc = regs->cp0_epc +
 717                                         dec_insn.pc_inc +
 718                                         (insn.i_format.simmediate << 2);
 719                         else
 720                                 *contpc = regs->cp0_epc +
 721                                         dec_insn.pc_inc +
 722                                         dec_insn.next_pc_inc;
 723
 724                         return 1;
 725                 }
 726                 /* R2/R6 compatible cop1 instruction. Fall through */
 727         case cop2_op:
 728         case cop1x_op:
 729                 if (insn.i_format.rs == bc_op) {
 730                         preempt_disable();
 731                         if (is_fpu_owner())
 732                                 fcr31 = read_32bit_cp1_register(CP1_STATUS);
 733                         else
 734                                 fcr31 = current->thread.fpu.fcr31;
 735                         preempt_enable();
 736
 737                         bit = (insn.i_format.rt >> 2);
 738                         bit += (bit != 0);
 739                         bit += 23;
 740                         switch (insn.i_format.rt & 3) {
 741                         case 0: /* bc1f */
 742                         case 2: /* bc1fl */
 743                                 if (~fcr31 & (1 << bit))
 744                                         *contpc = regs->cp0_epc +
 745                                                 dec_insn.pc_inc +
 746                                                 (insn.i_format.simmediate << 2);
 747                                 else
 748                                         *contpc = regs->cp0_epc +
 749                                                 dec_insn.pc_inc +
 750                                                 dec_insn.next_pc_inc;
 751                                 return 1;
 752                         case 1: /* bc1t */
 753                         case 3: /* bc1tl */
 754                                 if (fcr31 & (1 << bit))
 755                                         *contpc = regs->cp0_epc +
 756                                                 dec_insn.pc_inc +
 757                                                 (insn.i_format.simmediate << 2);
 758                                 else
 759                                         *contpc = regs->cp0_epc +
 760                                                 dec_insn.pc_inc +
 761                                                 dec_insn.next_pc_inc;
 762                                 return 1;
 763                         }
 764                 }
 765                 break;
 766         }
 767         return 0;
 768 }
 769
 770 /*
 771  * In the Linux kernel, we support selection of FPR format on the
 772  * basis of the Status.FR bit.  If an FPU is not present, the FR bit
 773  * is hardwired to zero, which would imply a 32-bit FPU even for
 774  * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
 775  * FPU emu is slow and bulky and optimizing this function offers fairly
 776  * sizeable benefits so we try to be clever and make this function return
 777  * a constant whenever possible, that is on 64-bit kernels without O32
 778  * compatibility enabled and on 32-bit without 64-bit FPU support.
 779  */
 780 static inline int cop1_64bit(struct pt_regs *xcp)
 781 {
 782         if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
 783                 return 1;
 784         else if (config_enabled(CONFIG_32BIT) &&
 785                  !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
 786                 return 0;
 787
 788         return !test_thread_flag(TIF_32BIT_FPREGS);
 789 }
 790
 791 static inline bool hybrid_fprs(void)
 792 {
 793         return test_thread_flag(TIF_HYBRID_FPREGS);
 794 }
 795
 796 #define SIFROMREG(si, x)                                                \
 797 do {                                                                    \
 798         if (cop1_64bit(xcp) && !hybrid_fprs())                          \
 799                 (si) = (int)get_fpr32(&ctx->fpr[x], 0);                 \
 800         else                                                            \
 801                 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1);    \
 802 } while (0)
 803
 804 #define SITOREG(si, x)                                                  \
 805 do {                                                                    \
 806         if (cop1_64bit(xcp) && !hybrid_fprs()) {                        \
 807                 unsigned i;                                             \
 808                 set_fpr32(&ctx->fpr[x], 0, si);                         \
 809                 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)     \
 810                         set_fpr32(&ctx->fpr[x], i, 0);                  \
 811         } else {                                                        \
 812                 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si);            \
 813         }                                                               \
 814 } while (0)
 815
 816 #define SIFROMHREG(si, x)       ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
 817
 818 #define SITOHREG(si, x)                                                 \
 819 do {                                                                    \
 820         unsigned i;                                                     \
 821         set_fpr32(&ctx->fpr[x], 1, si);                                 \
 822         for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++)             \
 823                 set_fpr32(&ctx->fpr[x], i, 0);                          \
 824 } while (0)
 825
 826 #define DIFROMREG(di, x)                                                \
 827         ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
 828
 829 #define DITOREG(di, x)                                                  \
 830 do {                                                                    \
 831         unsigned fpr, i;                                                \
 832         fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
 833         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
 834         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
 835                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
 836 } while (0)
 837
 838 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
 839 #define SPTOREG(sp, x)  SITOREG((sp).bits, x)
 840 #define DPFROMREG(dp, x)        DIFROMREG((dp).bits, x)
 841 #define DPTOREG(dp, x)  DITOREG((dp).bits, x)
 842
 843 /*
 844  * Emulate a CFC1 instruction.
 845  */
 846 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 847                             mips_instruction ir)
 848 {
 849         u32 value;
 850
 851         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 852                 value = ctx->fcr31;
 853                 pr_debug("%p gpr[%d]<-csr=%08x\n",
 854                          (void *)xcp->cp0_epc,
 855                          MIPSInst_RT(ir), value);
 856         } else if (MIPSInst_RD(ir) == FPCREG_RID)
 857                 value = current_cpu_data.fpu_id;
 858         else
 859                 value = 0;
 860         if (MIPSInst_RT(ir))
 861                 xcp->regs[MIPSInst_RT(ir)] = value;
 862 }
 863
 864 /*
 865  * Emulate a CTC1 instruction.
 866  */
 867 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 868                             mips_instruction ir)
 869 {
 870         u32 value;
 871
 872         if (MIPSInst_RT(ir) == 0)
 873                 value = 0;
 874         else
 875                 value = xcp->regs[MIPSInst_RT(ir)];
 876
 877         /* we only have one writable control reg
 878          */
 879         if (MIPSInst_RD(ir) == FPCREG_CSR) {
 880                 pr_debug("%p gpr[%d]->csr=%08x\n",
 881                          (void *)xcp->cp0_epc,
 882                          MIPSInst_RT(ir), value);
 883
 884                 /* Don't write reserved bits.  */
 885                 ctx->fcr31 = value & ~FPU_CSR_RSVD;
 886         }
 887 }
 888
 889 /*
 890  * Emulate the single floating point instruction pointed at by EPC.
 891  * Two instructions if the instruction is in a branch delay slot.
 892  */
 893
 894 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 895                 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
 896 {
 897         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
 898         unsigned int cond, cbit;
 899         mips_instruction ir;
 900         int likely, pc_inc;
 901         u32 __user *wva;
 902         u64 __user *dva;
 903         u32 wval;
 904         u64 dval;
 905         int sig;
 906
 907         /*
 908          * These are giving gcc a gentle hint about what to expect in
 909          * dec_inst in order to do better optimization.
 910          */
 911         if (!cpu_has_mmips && dec_insn.micro_mips_mode)
 912                 unreachable();
 913
 914         /* XXX NEC Vr54xx bug workaround */
 915         if (delay_slot(xcp)) {
 916                 if (dec_insn.micro_mips_mode) {
 917                         if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
 918                                 clear_delay_slot(xcp);
 919                 } else {
 920                         if (!isBranchInstr(xcp, dec_insn, &contpc))
 921                                 clear_delay_slot(xcp);
 922                 }
 923         }
 924
 925         if (delay_slot(xcp)) {
 926                 /*
 927                  * The instruction to be emulated is in a branch delay slot
 928                  * which means that we have to  emulate the branch instruction
 929                  * BEFORE we do the cop1 instruction.
 930                  *
 931                  * This branch could be a COP1 branch, but in that case we
 932                  * would have had a trap for that instruction, and would not
 933                  * come through this route.
 934                  *
 935                  * Linux MIPS branch emulator operates on context, updating the
 936                  * cp0_epc.
 937                  */
 938                 ir = dec_insn.next_insn;  /* process delay slot instr */
 939                 pc_inc = dec_insn.next_pc_inc;
 940         } else {
 941                 ir = dec_insn.insn;       /* process current instr */
 942                 pc_inc = dec_insn.pc_inc;
 943         }
 944
 945         /*
 946          * Since microMIPS FPU instructios are a subset of MIPS32 FPU
 947          * instructions, we want to convert microMIPS FPU instructions
 948          * into MIPS32 instructions so that we could reuse all of the
 949          * FPU emulation code.
 950          *
 951          * NOTE: We cannot do this for branch instructions since they
 952          *       are not a subset. Example: Cannot emulate a 16-bit
 953          *       aligned target address with a MIPS32 instruction.
 954          */
 955         if (dec_insn.micro_mips_mode) {
 956                 /*
 957                  * If next instruction is a 16-bit instruction, then it
 958                  * it cannot be a FPU instruction. This could happen
 959                  * since we can be called for non-FPU instructions.
 960                  */
 961                 if ((pc_inc == 2) ||
 962                         (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
 963                          == SIGILL))
 964                         return SIGILL;
 965         }
 966
 967 emul:
 968         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
 969         MIPS_FPU_EMU_INC_STATS(emulated);
 970         switch (MIPSInst_OPCODE(ir)) {
 971         case ldc1_op:
 972                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 973                                      MIPSInst_SIMM(ir));
 974                 MIPS_FPU_EMU_INC_STATS(loads);
 975
 976                 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
 977                         MIPS_FPU_EMU_INC_STATS(errors);
 978                         *fault_addr = dva;
 979                         return SIGBUS;
 980                 }
 981                 if (__get_user(dval, dva)) {
 982                         MIPS_FPU_EMU_INC_STATS(errors);
 983                         *fault_addr = dva;
 984                         return SIGSEGV;
 985                 }
 986                 DITOREG(dval, MIPSInst_RT(ir));
 987                 break;
 988
 989         case sdc1_op:
 990                 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
 991                                       MIPSInst_SIMM(ir));
 992                 MIPS_FPU_EMU_INC_STATS(stores);
 993                 DIFROMREG(dval, MIPSInst_RT(ir));
 994                 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
 995                         MIPS_FPU_EMU_INC_STATS(errors);
 996                         *fault_addr = dva;
 997                         return SIGBUS;
 998                 }
 999                 if (__put_user(dval, dva)) {
1000                         MIPS_FPU_EMU_INC_STATS(errors);
1001                         *fault_addr = dva;
1002                         return SIGSEGV;
1003                 }
1004                 break;
1005
1006         case lwc1_op:
1007                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1008                                       MIPSInst_SIMM(ir));
1009                 MIPS_FPU_EMU_INC_STATS(loads);
1010                 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1011                         MIPS_FPU_EMU_INC_STATS(errors);
1012                         *fault_addr = wva;
1013                         return SIGBUS;
1014                 }
1015                 if (__get_user(wval, wva)) {
1016                         MIPS_FPU_EMU_INC_STATS(errors);
1017                         *fault_addr = wva;
1018                         return SIGSEGV;
1019                 }
1020                 SITOREG(wval, MIPSInst_RT(ir));
1021                 break;
1022
1023         case swc1_op:
1024                 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1025                                       MIPSInst_SIMM(ir));
1026                 MIPS_FPU_EMU_INC_STATS(stores);
1027                 SIFROMREG(wval, MIPSInst_RT(ir));
1028                 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1029                         MIPS_FPU_EMU_INC_STATS(errors);
1030                         *fault_addr = wva;
1031                         return SIGBUS;
1032                 }
1033                 if (__put_user(wval, wva)) {
1034                         MIPS_FPU_EMU_INC_STATS(errors);
1035                         *fault_addr = wva;
1036                         return SIGSEGV;
1037                 }
1038                 break;
1039
1040         case cop1_op:
1041                 switch (MIPSInst_RS(ir)) {
1042                 case dmfc_op:
1043                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1044                                 return SIGILL;
1045
1046                         /* copregister fs -> gpr[rt] */
1047                         if (MIPSInst_RT(ir) != 0) {
1048                                 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1049                                         MIPSInst_RD(ir));
1050                         }
1051                         break;
1052
1053                 case dmtc_op:
1054                         if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1055                                 return SIGILL;
1056
1057                         /* copregister fs <- rt */
1058                         DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1059                         break;
1060
1061                 case mfhc_op:
1062                         if (!cpu_has_mips_r2)
1063                                 goto sigill;
1064
1065                         /* copregister rd -> gpr[rt] */
1066                         if (MIPSInst_RT(ir) != 0) {
1067                                 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1068                                         MIPSInst_RD(ir));
1069                         }
1070                         break;
1071
1072                 case mthc_op:
1073                         if (!cpu_has_mips_r2)
1074                                 goto sigill;
1075
1076                         /* copregister rd <- gpr[rt] */
1077                         SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1078                         break;
1079
1080                 case mfc_op:
1081                         /* copregister rd -> gpr[rt] */
1082                         if (MIPSInst_RT(ir) != 0) {
1083                                 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1084                                         MIPSInst_RD(ir));
1085                         }
1086                         break;
1087
1088                 case mtc_op:
1089                         /* copregister rd <- rt */
1090                         SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1091                         break;
1092
1093                 case cfc_op:
1094                         /* cop control register rd -> gpr[rt] */
1095                         cop1_cfc(xcp, ctx, ir);
1096                         break;
1097
1098                 case ctc_op:
1099                         /* copregister rd <- rt */
1100                         cop1_ctc(xcp, ctx, ir);
1101                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1102                                 return SIGFPE;
1103                         }
1104                         break;
1105
1106                 case bc_op:
1107                         if (delay_slot(xcp))
1108                                 return SIGILL;
1109
1110                         if (cpu_has_mips_4_5_r)
1111                                 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1112                         else
1113                                 cbit = FPU_CSR_COND;
1114                         cond = ctx->fcr31 & cbit;
1115
1116                         likely = 0;
1117                         switch (MIPSInst_RT(ir) & 3) {
1118                         case bcfl_op:
1119                                 if (cpu_has_mips_2_3_4_5_r)
1120                                         likely = 1;
1121                                 /* Fall through */
1122                         case bcf_op:
1123                                 cond = !cond;
1124                                 break;
1125                         case bctl_op:
1126                                 if (cpu_has_mips_2_3_4_5_r)
1127                                         likely = 1;
1128                                 /* Fall through */
1129                         case bct_op:
1130                                 break;
1131                         }
1132
1133                         set_delay_slot(xcp);
1134                         if (cond) {
1135                                 /*
1136                                  * Branch taken: emulate dslot instruction
1137                                  */
1138                                 unsigned long bcpc;
1139
1140                                 /*
1141                                  * Remember EPC at the branch to point back
1142                                  * at so that any delay-slot instruction
1143                                  * signal is not silently ignored.
1144                                  */
1145                                 bcpc = xcp->cp0_epc;
1146                                 xcp->cp0_epc += dec_insn.pc_inc;
1147
1148                                 contpc = MIPSInst_SIMM(ir);
1149                                 ir = dec_insn.next_insn;
1150                                 if (dec_insn.micro_mips_mode) {
1151                                         contpc = (xcp->cp0_epc + (contpc << 1));
1152
1153                                         /* If 16-bit instruction, not FPU. */
1154                                         if ((dec_insn.next_pc_inc == 2) ||
1155                                                 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1156
1157                                                 /*
1158                                                  * Since this instruction will
1159                                                  * be put on the stack with
1160                                                  * 32-bit words, get around
1161                                                  * this problem by putting a
1162                                                  * NOP16 as the second one.
1163                                                  */
1164                                                 if (dec_insn.next_pc_inc == 2)
1165                                                         ir = (ir & (~0xffff)) | MM_NOP16;
1166
1167                                                 /*
1168                                                  * Single step the non-CP1
1169                                                  * instruction in the dslot.
1170                                                  */
1171                                                 sig = mips_dsemul(xcp, ir,
1172                                                                   contpc);
1173                                                 if (sig)
1174                                                         xcp->cp0_epc = bcpc;
1175                                                 /*
1176                                                  * SIGILL forces out of
1177                                                  * the emulation loop.
1178                                                  */
1179                                                 return sig ? sig : SIGILL;
1180                                         }
1181                                 } else
1182                                         contpc = (xcp->cp0_epc + (contpc << 2));
1183
1184                                 switch (MIPSInst_OPCODE(ir)) {
1185                                 case lwc1_op:
1186                                 case swc1_op:
1187                                         goto emul;
1188
1189                                 case ldc1_op:
1190                                 case sdc1_op:
1191                                         if (cpu_has_mips_2_3_4_5_r)
1192                                                 goto emul;
1193
1194                                         goto bc_sigill;
1195
1196                                 case cop1_op:
1197                                         goto emul;
1198
1199                                 case cop1x_op:
1200                                         if (cpu_has_mips_4_5_64_r2_r6)
1201                                                 /* its one of ours */
1202                                                 goto emul;
1203
1204                                         goto bc_sigill;
1205
1206                                 case spec_op:
1207                                         switch (MIPSInst_FUNC(ir)) {
1208                                         case movc_op:
1209                                                 if (cpu_has_mips_4_5_r)
1210                                                         goto emul;
1211
1212                                                 goto bc_sigill;
1213                                         }
1214                                         break;
1215
1216                                 bc_sigill:
1217                                         xcp->cp0_epc = bcpc;
1218                                         return SIGILL;
1219                                 }
1220
1221                                 /*
1222                                  * Single step the non-cp1
1223                                  * instruction in the dslot
1224                                  */
1225                                 sig = mips_dsemul(xcp, ir, contpc);
1226                                 if (sig)
1227                                         xcp->cp0_epc = bcpc;
1228                                 /* SIGILL forces out of the emulation loop.  */
1229                                 return sig ? sig : SIGILL;
1230                         } else if (likely) {    /* branch not taken */
1231                                 /*
1232                                  * branch likely nullifies
1233                                  * dslot if not taken
1234                                  */
1235                                 xcp->cp0_epc += dec_insn.pc_inc;
1236                                 contpc += dec_insn.pc_inc;
1237                                 /*
1238                                  * else continue & execute
1239                                  * dslot as normal insn
1240                                  */
1241                         }
1242                         break;
1243
1244                 default:
1245                         if (!(MIPSInst_RS(ir) & 0x10))
1246                                 return SIGILL;
1247
1248                         /* a real fpu computation instruction */
1249                         if ((sig = fpu_emu(xcp, ctx, ir)))
1250                                 return sig;
1251                 }
1252                 break;
1253
1254         case cop1x_op:
1255                 if (!cpu_has_mips_4_5_64_r2_r6)
1256                         return SIGILL;
1257
1258                 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1259                 if (sig)
1260                         return sig;
1261                 break;
1262
1263         case spec_op:
1264                 if (!cpu_has_mips_4_5_r)
1265                         return SIGILL;
1266
1267                 if (MIPSInst_FUNC(ir) != movc_op)
1268                         return SIGILL;
1269                 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1270                 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1271                         xcp->regs[MIPSInst_RD(ir)] =
1272                                 xcp->regs[MIPSInst_RS(ir)];
1273                 break;
1274         default:
1275 sigill:
1276                 return SIGILL;
1277         }
1278
1279         /* we did it !! */
1280         xcp->cp0_epc = contpc;
1281         clear_delay_slot(xcp);
1282
1283         return 0;
1284 }
1285
1286 /*
1287  * Conversion table from MIPS compare ops 48-63
1288  * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1289  */
1290 static const unsigned char cmptab[8] = {
1291         0,                      /* cmp_0 (sig) cmp_sf */
1292         IEEE754_CUN,            /* cmp_un (sig) cmp_ngle */
1293         IEEE754_CEQ,            /* cmp_eq (sig) cmp_seq */
1294         IEEE754_CEQ | IEEE754_CUN,      /* cmp_ueq (sig) cmp_ngl  */
1295         IEEE754_CLT,            /* cmp_olt (sig) cmp_lt */
1296         IEEE754_CLT | IEEE754_CUN,      /* cmp_ult (sig) cmp_nge */
1297         IEEE754_CLT | IEEE754_CEQ,      /* cmp_ole (sig) cmp_le */
1298         IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN,        /* cmp_ule (sig) cmp_ngt */
1299 };
1300
1301
1302 /*
1303  * Additional MIPS4 instructions
1304  */
1305
1306 #define DEF3OP(name, p, f1, f2, f3)                                     \
1307 static union ieee754##p fpemu_##p##_##name(union ieee754##p r,          \
1308         union ieee754##p s, union ieee754##p t)                         \
1309 {                                                                       \
1310         struct _ieee754_csr ieee754_csr_save;                           \
1311         s = f1(s, t);                                                   \
1312         ieee754_csr_save = ieee754_csr;                                 \
1313         s = f2(s, r);                                                   \
1314         ieee754_csr_save.cx |= ieee754_csr.cx;                          \
1315         ieee754_csr_save.sx |= ieee754_csr.sx;                          \
1316         s = f3(s);                                                      \
1317         ieee754_csr.cx |= ieee754_csr_save.cx;                          \
1318         ieee754_csr.sx |= ieee754_csr_save.sx;                          \
1319         return s;                                                       \
1320 }
1321
1322 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1323 {
1324         return ieee754dp_div(ieee754dp_one(0), d);
1325 }
1326
1327 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1328 {
1329         return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1330 }
1331
1332 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1333 {
1334         return ieee754sp_div(ieee754sp_one(0), s);
1335 }
1336
1337 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1338 {
1339         return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1340 }
1341
1342 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1343 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1344 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1345 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1346 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1347 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1348 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1349 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1350
1351 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1352         mips_instruction ir, void *__user *fault_addr)
1353 {
1354         unsigned rcsr = 0;      /* resulting csr */
1355
1356         MIPS_FPU_EMU_INC_STATS(cp1xops);
1357
1358         switch (MIPSInst_FMA_FFMT(ir)) {
1359         case s_fmt:{            /* 0 */
1360
1361                 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1362                 union ieee754sp fd, fr, fs, ft;
1363                 u32 __user *va;
1364                 u32 val;
1365
1366                 switch (MIPSInst_FUNC(ir)) {
1367                 case lwxc1_op:
1368                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1369                                 xcp->regs[MIPSInst_FT(ir)]);
1370
1371                         MIPS_FPU_EMU_INC_STATS(loads);
1372                         if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1373                                 MIPS_FPU_EMU_INC_STATS(errors);
1374                                 *fault_addr = va;
1375                                 return SIGBUS;
1376                         }
1377                         if (__get_user(val, va)) {
1378                                 MIPS_FPU_EMU_INC_STATS(errors);
1379                                 *fault_addr = va;
1380                                 return SIGSEGV;
1381                         }
1382                         SITOREG(val, MIPSInst_FD(ir));
1383                         break;
1384
1385                 case swxc1_op:
1386                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1387                                 xcp->regs[MIPSInst_FT(ir)]);
1388
1389                         MIPS_FPU_EMU_INC_STATS(stores);
1390
1391                         SIFROMREG(val, MIPSInst_FS(ir));
1392                         if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1393                                 MIPS_FPU_EMU_INC_STATS(errors);
1394                                 *fault_addr = va;
1395                                 return SIGBUS;
1396                         }
1397                         if (put_user(val, va)) {
1398                                 MIPS_FPU_EMU_INC_STATS(errors);
1399                                 *fault_addr = va;
1400                                 return SIGSEGV;
1401                         }
1402                         break;
1403
1404                 case madd_s_op:
1405                         handler = fpemu_sp_madd;
1406                         goto scoptop;
1407                 case msub_s_op:
1408                         handler = fpemu_sp_msub;
1409                         goto scoptop;
1410                 case nmadd_s_op:
1411                         handler = fpemu_sp_nmadd;
1412                         goto scoptop;
1413                 case nmsub_s_op:
1414                         handler = fpemu_sp_nmsub;
1415                         goto scoptop;
1416
1417                       scoptop:
1418                         SPFROMREG(fr, MIPSInst_FR(ir));
1419                         SPFROMREG(fs, MIPSInst_FS(ir));
1420                         SPFROMREG(ft, MIPSInst_FT(ir));
1421                         fd = (*handler) (fr, fs, ft);
1422                         SPTOREG(fd, MIPSInst_FD(ir));
1423
1424                       copcsr:
1425                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1426                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1427                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1428                         }
1429                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1430                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1431                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1432                         }
1433                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1434                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1435                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1436                         }
1437                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1438                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1439                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1440                         }
1441
1442                         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1443                         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1444                                 /*printk ("SIGFPE: FPU csr = %08x\n",
1445                                    ctx->fcr31); */
1446                                 return SIGFPE;
1447                         }
1448
1449                         break;
1450
1451                 default:
1452                         return SIGILL;
1453                 }
1454                 break;
1455         }
1456
1457         case d_fmt:{            /* 1 */
1458                 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1459                 union ieee754dp fd, fr, fs, ft;
1460                 u64 __user *va;
1461                 u64 val;
1462
1463                 switch (MIPSInst_FUNC(ir)) {
1464                 case ldxc1_op:
1465                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1466                                 xcp->regs[MIPSInst_FT(ir)]);
1467
1468                         MIPS_FPU_EMU_INC_STATS(loads);
1469                         if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1470                                 MIPS_FPU_EMU_INC_STATS(errors);
1471                                 *fault_addr = va;
1472                                 return SIGBUS;
1473                         }
1474                         if (__get_user(val, va)) {
1475                                 MIPS_FPU_EMU_INC_STATS(errors);
1476                                 *fault_addr = va;
1477                                 return SIGSEGV;
1478                         }
1479                         DITOREG(val, MIPSInst_FD(ir));
1480                         break;
1481
1482                 case sdxc1_op:
1483                         va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1484                                 xcp->regs[MIPSInst_FT(ir)]);
1485
1486                         MIPS_FPU_EMU_INC_STATS(stores);
1487                         DIFROMREG(val, MIPSInst_FS(ir));
1488                         if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1489                                 MIPS_FPU_EMU_INC_STATS(errors);
1490                                 *fault_addr = va;
1491                                 return SIGBUS;
1492                         }
1493                         if (__put_user(val, va)) {
1494                                 MIPS_FPU_EMU_INC_STATS(errors);
1495                                 *fault_addr = va;
1496                                 return SIGSEGV;
1497                         }
1498                         break;
1499
1500                 case madd_d_op:
1501                         handler = fpemu_dp_madd;
1502                         goto dcoptop;
1503                 case msub_d_op:
1504                         handler = fpemu_dp_msub;
1505                         goto dcoptop;
1506                 case nmadd_d_op:
1507                         handler = fpemu_dp_nmadd;
1508                         goto dcoptop;
1509                 case nmsub_d_op:
1510                         handler = fpemu_dp_nmsub;
1511                         goto dcoptop;
1512
1513                       dcoptop:
1514                         DPFROMREG(fr, MIPSInst_FR(ir));
1515                         DPFROMREG(fs, MIPSInst_FS(ir));
1516                         DPFROMREG(ft, MIPSInst_FT(ir));
1517                         fd = (*handler) (fr, fs, ft);
1518                         DPTOREG(fd, MIPSInst_FD(ir));
1519                         goto copcsr;
1520
1521                 default:
1522                         return SIGILL;
1523                 }
1524                 break;
1525         }
1526
1527         case 0x3:
1528                 if (MIPSInst_FUNC(ir) != pfetch_op)
1529                         return SIGILL;
1530
1531                 /* ignore prefx operation */
1532                 break;
1533
1534         default:
1535                 return SIGILL;
1536         }
1537
1538         return 0;
1539 }
1540
1541
1542
1543 /*
1544  * Emulate a single COP1 arithmetic instruction.
1545  */
1546 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1547         mips_instruction ir)
1548 {
1549         int rfmt;               /* resulting format */
1550         unsigned rcsr = 0;      /* resulting csr */
1551         unsigned int oldrm;
1552         unsigned int cbit;
1553         unsigned cond;
1554         union {
1555                 union ieee754dp d;
1556                 union ieee754sp s;
1557                 int w;
1558                 s64 l;
1559         } rv;                   /* resulting value */
1560         u64 bits;
1561
1562         MIPS_FPU_EMU_INC_STATS(cp1ops);
1563         switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1564         case s_fmt: {           /* 0 */
1565                 union {
1566                         union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1567                         union ieee754sp(*u) (union ieee754sp);
1568                 } handler;
1569                 union ieee754sp fs, ft;
1570
1571                 switch (MIPSInst_FUNC(ir)) {
1572                         /* binary ops */
1573                 case fadd_op:
1574                         handler.b = ieee754sp_add;
1575                         goto scopbop;
1576                 case fsub_op:
1577                         handler.b = ieee754sp_sub;
1578                         goto scopbop;
1579                 case fmul_op:
1580                         handler.b = ieee754sp_mul;
1581                         goto scopbop;
1582                 case fdiv_op:
1583                         handler.b = ieee754sp_div;
1584                         goto scopbop;
1585
1586                         /* unary  ops */
1587                 case fsqrt_op:
1588                         if (!cpu_has_mips_2_3_4_5_r)
1589                                 return SIGILL;
1590
1591                         handler.u = ieee754sp_sqrt;
1592                         goto scopuop;
1593
1594                 /*
1595                  * Note that on some MIPS IV implementations such as the
1596                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1597                  * achieve full IEEE-754 accuracy - however this emulator does.
1598                  */
1599                 case frsqrt_op:
1600                         if (!cpu_has_mips_4_5_64_r2_r6)
1601                                 return SIGILL;
1602
1603                         handler.u = fpemu_sp_rsqrt;
1604                         goto scopuop;
1605
1606                 case frecip_op:
1607                         if (!cpu_has_mips_4_5_64_r2_r6)
1608                                 return SIGILL;
1609
1610                         handler.u = fpemu_sp_recip;
1611                         goto scopuop;
1612
1613                 case fmovc_op:
1614                         if (!cpu_has_mips_4_5_r)
1615                                 return SIGILL;
1616
1617                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1618                         if (((ctx->fcr31 & cond) != 0) !=
1619                                 ((MIPSInst_FT(ir) & 1) != 0))
1620                                 return 0;
1621                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1622                         break;
1623
1624                 case fmovz_op:
1625                         if (!cpu_has_mips_4_5_r)
1626                                 return SIGILL;
1627
1628                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1629                                 return 0;
1630                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1631                         break;
1632
1633                 case fmovn_op:
1634                         if (!cpu_has_mips_4_5_r)
1635                                 return SIGILL;
1636
1637                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1638                                 return 0;
1639                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1640                         break;
1641
1642                 case fabs_op:
1643                         handler.u = ieee754sp_abs;
1644                         goto scopuop;
1645
1646                 case fneg_op:
1647                         handler.u = ieee754sp_neg;
1648                         goto scopuop;
1649
1650                 case fmov_op:
1651                         /* an easy one */
1652                         SPFROMREG(rv.s, MIPSInst_FS(ir));
1653                         goto copcsr;
1654
1655                         /* binary op on handler */
1656 scopbop:
1657                         SPFROMREG(fs, MIPSInst_FS(ir));
1658                         SPFROMREG(ft, MIPSInst_FT(ir));
1659
1660                         rv.s = (*handler.b) (fs, ft);
1661                         goto copcsr;
1662 scopuop:
1663                         SPFROMREG(fs, MIPSInst_FS(ir));
1664                         rv.s = (*handler.u) (fs);
1665                         goto copcsr;
1666 copcsr:
1667                         if (ieee754_cxtest(IEEE754_INEXACT)) {
1668                                 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1669                                 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1670                         }
1671                         if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1672                                 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1673                                 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1674                         }
1675                         if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1676                                 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1677                                 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1678                         }
1679                         if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1680                                 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1681                                 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1682                         }
1683                         if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1684                                 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1685                                 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1686                         }
1687                         break;
1688
1689                         /* unary conv ops */
1690                 case fcvts_op:
1691                         return SIGILL;  /* not defined */
1692
1693                 case fcvtd_op:
1694                         SPFROMREG(fs, MIPSInst_FS(ir));
1695                         rv.d = ieee754dp_fsp(fs);
1696                         rfmt = d_fmt;
1697                         goto copcsr;
1698
1699                 case fcvtw_op:
1700                         SPFROMREG(fs, MIPSInst_FS(ir));
1701                         rv.w = ieee754sp_tint(fs);
1702                         rfmt = w_fmt;
1703                         goto copcsr;
1704
1705                 case fround_op:
1706                 case ftrunc_op:
1707                 case fceil_op:
1708                 case ffloor_op:
1709                         if (!cpu_has_mips_2_3_4_5_r)
1710                                 return SIGILL;
1711
1712                         oldrm = ieee754_csr.rm;
1713                         SPFROMREG(fs, MIPSInst_FS(ir));
1714                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1715                         rv.w = ieee754sp_tint(fs);
1716                         ieee754_csr.rm = oldrm;
1717                         rfmt = w_fmt;
1718                         goto copcsr;
1719
1720                 case fcvtl_op:
1721                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1722                                 return SIGILL;
1723
1724                         SPFROMREG(fs, MIPSInst_FS(ir));
1725                         rv.l = ieee754sp_tlong(fs);
1726                         rfmt = l_fmt;
1727                         goto copcsr;
1728
1729                 case froundl_op:
1730                 case ftruncl_op:
1731                 case fceill_op:
1732                 case ffloorl_op:
1733                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1734                                 return SIGILL;
1735
1736                         oldrm = ieee754_csr.rm;
1737                         SPFROMREG(fs, MIPSInst_FS(ir));
1738                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1739                         rv.l = ieee754sp_tlong(fs);
1740                         ieee754_csr.rm = oldrm;
1741                         rfmt = l_fmt;
1742                         goto copcsr;
1743
1744                 default:
1745                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1746                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1747                                 union ieee754sp fs, ft;
1748
1749                                 SPFROMREG(fs, MIPSInst_FS(ir));
1750                                 SPFROMREG(ft, MIPSInst_FT(ir));
1751                                 rv.w = ieee754sp_cmp(fs, ft,
1752                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1753                                 rfmt = -1;
1754                                 if ((cmpop & 0x8) && ieee754_cxtest
1755                                         (IEEE754_INVALID_OPERATION))
1756                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1757                                 else
1758                                         goto copcsr;
1759
1760                         } else
1761                                 return SIGILL;
1762                         break;
1763                 }
1764                 break;
1765         }
1766
1767         case d_fmt: {
1768                 union ieee754dp fs, ft;
1769                 union {
1770                         union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1771                         union ieee754dp(*u) (union ieee754dp);
1772                 } handler;
1773
1774                 switch (MIPSInst_FUNC(ir)) {
1775                         /* binary ops */
1776                 case fadd_op:
1777                         handler.b = ieee754dp_add;
1778                         goto dcopbop;
1779                 case fsub_op:
1780                         handler.b = ieee754dp_sub;
1781                         goto dcopbop;
1782                 case fmul_op:
1783                         handler.b = ieee754dp_mul;
1784                         goto dcopbop;
1785                 case fdiv_op:
1786                         handler.b = ieee754dp_div;
1787                         goto dcopbop;
1788
1789                         /* unary  ops */
1790                 case fsqrt_op:
1791                         if (!cpu_has_mips_2_3_4_5_r)
1792                                 return SIGILL;
1793
1794                         handler.u = ieee754dp_sqrt;
1795                         goto dcopuop;
1796                 /*
1797                  * Note that on some MIPS IV implementations such as the
1798                  * R5000 and R8000 the FSQRT and FRECIP instructions do not
1799                  * achieve full IEEE-754 accuracy - however this emulator does.
1800                  */
1801                 case frsqrt_op:
1802                         if (!cpu_has_mips_4_5_64_r2_r6)
1803                                 return SIGILL;
1804
1805                         handler.u = fpemu_dp_rsqrt;
1806                         goto dcopuop;
1807                 case frecip_op:
1808                         if (!cpu_has_mips_4_5_64_r2_r6)
1809                                 return SIGILL;
1810
1811                         handler.u = fpemu_dp_recip;
1812                         goto dcopuop;
1813                 case fmovc_op:
1814                         if (!cpu_has_mips_4_5_r)
1815                                 return SIGILL;
1816
1817                         cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1818                         if (((ctx->fcr31 & cond) != 0) !=
1819                                 ((MIPSInst_FT(ir) & 1) != 0))
1820                                 return 0;
1821                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1822                         break;
1823                 case fmovz_op:
1824                         if (!cpu_has_mips_4_5_r)
1825                                 return SIGILL;
1826
1827                         if (xcp->regs[MIPSInst_FT(ir)] != 0)
1828                                 return 0;
1829                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1830                         break;
1831                 case fmovn_op:
1832                         if (!cpu_has_mips_4_5_r)
1833                                 return SIGILL;
1834
1835                         if (xcp->regs[MIPSInst_FT(ir)] == 0)
1836                                 return 0;
1837                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1838                         break;
1839                 case fabs_op:
1840                         handler.u = ieee754dp_abs;
1841                         goto dcopuop;
1842
1843                 case fneg_op:
1844                         handler.u = ieee754dp_neg;
1845                         goto dcopuop;
1846
1847                 case fmov_op:
1848                         /* an easy one */
1849                         DPFROMREG(rv.d, MIPSInst_FS(ir));
1850                         goto copcsr;
1851
1852                         /* binary op on handler */
1853 dcopbop:
1854                         DPFROMREG(fs, MIPSInst_FS(ir));
1855                         DPFROMREG(ft, MIPSInst_FT(ir));
1856
1857                         rv.d = (*handler.b) (fs, ft);
1858                         goto copcsr;
1859 dcopuop:
1860                         DPFROMREG(fs, MIPSInst_FS(ir));
1861                         rv.d = (*handler.u) (fs);
1862                         goto copcsr;
1863
1864                 /*
1865                  * unary conv ops
1866                  */
1867                 case fcvts_op:
1868                         DPFROMREG(fs, MIPSInst_FS(ir));
1869                         rv.s = ieee754sp_fdp(fs);
1870                         rfmt = s_fmt;
1871                         goto copcsr;
1872
1873                 case fcvtd_op:
1874                         return SIGILL;  /* not defined */
1875
1876                 case fcvtw_op:
1877                         DPFROMREG(fs, MIPSInst_FS(ir));
1878                         rv.w = ieee754dp_tint(fs);      /* wrong */
1879                         rfmt = w_fmt;
1880                         goto copcsr;
1881
1882                 case fround_op:
1883                 case ftrunc_op:
1884                 case fceil_op:
1885                 case ffloor_op:
1886                         if (!cpu_has_mips_2_3_4_5_r)
1887                                 return SIGILL;
1888
1889                         oldrm = ieee754_csr.rm;
1890                         DPFROMREG(fs, MIPSInst_FS(ir));
1891                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1892                         rv.w = ieee754dp_tint(fs);
1893                         ieee754_csr.rm = oldrm;
1894                         rfmt = w_fmt;
1895                         goto copcsr;
1896
1897                 case fcvtl_op:
1898                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1899                                 return SIGILL;
1900
1901                         DPFROMREG(fs, MIPSInst_FS(ir));
1902                         rv.l = ieee754dp_tlong(fs);
1903                         rfmt = l_fmt;
1904                         goto copcsr;
1905
1906                 case froundl_op:
1907                 case ftruncl_op:
1908                 case fceill_op:
1909                 case ffloorl_op:
1910                         if (!cpu_has_mips_3_4_5_64_r2_r6)
1911                                 return SIGILL;
1912
1913                         oldrm = ieee754_csr.rm;
1914                         DPFROMREG(fs, MIPSInst_FS(ir));
1915                         ieee754_csr.rm = MIPSInst_FUNC(ir);
1916                         rv.l = ieee754dp_tlong(fs);
1917                         ieee754_csr.rm = oldrm;
1918                         rfmt = l_fmt;
1919                         goto copcsr;
1920
1921                 default:
1922                         if (MIPSInst_FUNC(ir) >= fcmp_op) {
1923                                 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1924                                 union ieee754dp fs, ft;
1925
1926                                 DPFROMREG(fs, MIPSInst_FS(ir));
1927                                 DPFROMREG(ft, MIPSInst_FT(ir));
1928                                 rv.w = ieee754dp_cmp(fs, ft,
1929                                         cmptab[cmpop & 0x7], cmpop & 0x8);
1930                                 rfmt = -1;
1931                                 if ((cmpop & 0x8)
1932                                         &&
1933                                         ieee754_cxtest
1934                                         (IEEE754_INVALID_OPERATION))
1935                                         rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1936                                 else
1937                                         goto copcsr;
1938
1939                         }
1940                         else {
1941                                 return SIGILL;
1942                         }
1943                         break;
1944                 }
1945                 break;
1946
1947         case w_fmt:
1948                 switch (MIPSInst_FUNC(ir)) {
1949                 case fcvts_op:
1950                         /* convert word to single precision real */
1951                         SPFROMREG(fs, MIPSInst_FS(ir));
1952                         rv.s = ieee754sp_fint(fs.bits);
1953                         rfmt = s_fmt;
1954                         goto copcsr;
1955                 case fcvtd_op:
1956                         /* convert word to double precision real */
1957                         SPFROMREG(fs, MIPSInst_FS(ir));
1958                         rv.d = ieee754dp_fint(fs.bits);
1959                         rfmt = d_fmt;
1960                         goto copcsr;
1961                 default:
1962                         return SIGILL;
1963                 }
1964                 break;
1965         }
1966
1967         case l_fmt:
1968
1969                 if (!cpu_has_mips_3_4_5_64_r2_r6)
1970                         return SIGILL;
1971
1972                 DIFROMREG(bits, MIPSInst_FS(ir));
1973
1974                 switch (MIPSInst_FUNC(ir)) {
1975                 case fcvts_op:
1976                         /* convert long to single precision real */
1977                         rv.s = ieee754sp_flong(bits);
1978                         rfmt = s_fmt;
1979                         goto copcsr;
1980                 case fcvtd_op:
1981                         /* convert long to double precision real */
1982                         rv.d = ieee754dp_flong(bits);
1983                         rfmt = d_fmt;
1984                         goto copcsr;
1985                 default:
1986                         return SIGILL;
1987                 }
1988                 break;
1989
1990         default:
1991                 return SIGILL;
1992         }
1993
1994         /*
1995          * Update the fpu CSR register for this operation.
1996          * If an exception is required, generate a tidy SIGFPE exception,
1997          * without updating the result register.
1998          * Note: cause exception bits do not accumulate, they are rewritten
1999          * for each op; only the flag/sticky bits accumulate.
2000          */
2001         ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2002         if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2003                 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2004                 return SIGFPE;
2005         }
2006
2007         /*
2008          * Now we can safely write the result back to the register file.
2009          */
2010         switch (rfmt) {
2011         case -1:
2012
2013                 if (cpu_has_mips_4_5_r)
2014                         cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2015                 else
2016                         cbit = FPU_CSR_COND;
2017                 if (rv.w)
2018                         ctx->fcr31 |= cbit;
2019                 else
2020                         ctx->fcr31 &= ~cbit;
2021                 break;
2022
2023         case d_fmt:
2024                 DPTOREG(rv.d, MIPSInst_FD(ir));
2025                 break;
2026         case s_fmt:
2027                 SPTOREG(rv.s, MIPSInst_FD(ir));
2028                 break;
2029         case w_fmt:
2030                 SITOREG(rv.w, MIPSInst_FD(ir));
2031                 break;
2032         case l_fmt:
2033                 if (!cpu_has_mips_3_4_5_64_r2_r6)
2034                         return SIGILL;
2035
2036                 DITOREG(rv.l, MIPSInst_FD(ir));
2037                 break;
2038         default:
2039                 return SIGILL;
2040         }
2041
2042         return 0;
2043 }
2044
2045 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2046         int has_fpu, void *__user *fault_addr)
2047 {
2048         unsigned long oldepc, prevepc;
2049         struct mm_decoded_insn dec_insn;
2050         u16 instr[4];
2051         u16 *instr_ptr;
2052         int sig = 0;
2053
2054         oldepc = xcp->cp0_epc;
2055         do {
2056                 prevepc = xcp->cp0_epc;
2057
2058                 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2059                         /*
2060                          * Get next 2 microMIPS instructions and convert them
2061                          * into 32-bit instructions.
2062                          */
2063                         if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2064                             (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2065                             (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2066                             (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2067                                 MIPS_FPU_EMU_INC_STATS(errors);
2068                                 return SIGBUS;
2069                         }
2070                         instr_ptr = instr;
2071
2072                         /* Get first instruction. */
2073                         if (mm_insn_16bit(*instr_ptr)) {
2074                                 /* Duplicate the half-word. */
2075                                 dec_insn.insn = (*instr_ptr << 16) |
2076                                         (*instr_ptr);
2077                                 /* 16-bit instruction. */
2078                                 dec_insn.pc_inc = 2;
2079                                 instr_ptr += 1;
2080                         } else {
2081                                 dec_insn.insn = (*instr_ptr << 16) |
2082                                         *(instr_ptr+1);
2083                                 /* 32-bit instruction. */
2084                                 dec_insn.pc_inc = 4;
2085                                 instr_ptr += 2;
2086                         }
2087                         /* Get second instruction. */
2088                         if (mm_insn_16bit(*instr_ptr)) {
2089                                 /* Duplicate the half-word. */
2090                                 dec_insn.next_insn = (*instr_ptr << 16) |
2091                                         (*instr_ptr);
2092                                 /* 16-bit instruction. */
2093                                 dec_insn.next_pc_inc = 2;
2094                         } else {
2095                                 dec_insn.next_insn = (*instr_ptr << 16) |
2096                                         *(instr_ptr+1);
2097                                 /* 32-bit instruction. */
2098                                 dec_insn.next_pc_inc = 4;
2099                         }
2100                         dec_insn.micro_mips_mode = 1;
2101                 } else {
2102                         if ((get_user(dec_insn.insn,
2103                             (mips_instruction __user *) xcp->cp0_epc)) ||
2104                             (get_user(dec_insn.next_insn,
2105                             (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2106                                 MIPS_FPU_EMU_INC_STATS(errors);
2107                                 return SIGBUS;
2108                         }
2109                         dec_insn.pc_inc = 4;
2110                         dec_insn.next_pc_inc = 4;
2111                         dec_insn.micro_mips_mode = 0;
2112                 }
2113
2114                 if ((dec_insn.insn == 0) ||
2115                    ((dec_insn.pc_inc == 2) &&
2116                    ((dec_insn.insn & 0xffff) == MM_NOP16)))
2117                         xcp->cp0_epc += dec_insn.pc_inc;        /* Skip NOPs */
2118                 else {
2119                         /*
2120                          * The 'ieee754_csr' is an alias of ctx->fcr31.
2121                          * No need to copy ctx->fcr31 to ieee754_csr.
2122                          */
2123                         sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2124                 }
2125
2126                 if (has_fpu)
2127                         break;
2128                 if (sig)
2129                         break;
2130
2131                 cond_resched();
2132         } while (xcp->cp0_epc > prevepc);
2133
2134         /* SIGILL indicates a non-fpu instruction */
2135         if (sig == SIGILL && xcp->cp0_epc != oldepc)
2136                 /* but if EPC has advanced, then ignore it */
2137                 sig = 0;
2138
2139         return sig;
2140 }