2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
23 * A complete emulator for MIPS coprocessor 1 instructions. This is
24 * required for #float(switch) or #float(trap), where it catches all
25 * COP1 instructions via the "CoProcessor Unusable" exception.
27 * More surprisingly it is also required for #float(ieee), to help out
28 * the hardware FPU at the boundaries of the IEEE-754 representation
29 * (denormalised values, infinities, underflow, etc). It is made
30 * quite nasty because emulation of some non-COP1 instructions is
31 * required, e.g. in branch delay slots.
33 * Note if you know that you won't have an FPU, then you'll get much
34 * better performance by compiling with -msoft-float!
36 #include <linux/sched.h>
37 #include <linux/debugfs.h>
38 #include <linux/kconfig.h>
39 #include <linux/percpu-defs.h>
40 #include <linux/perf_event.h>
42 #include <asm/branch.h>
44 #include <asm/ptrace.h>
45 #include <asm/signal.h>
46 #include <asm/uaccess.h>
48 #include <asm/cpu-info.h>
49 #include <asm/processor.h>
50 #include <asm/fpu_emulator.h>
52 #include <asm/mips-r2-to-r6-emul.h>
56 /* Function which emulates a floating point instruction. */
58 static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
61 static int fpux_emu(struct pt_regs *,
62 struct mips_fpu_struct *, mips_instruction, void *__user *);
64 /* Control registers */
66 #define FPCREG_RID 0 /* $0 = revision id */
67 #define FPCREG_CSR 31 /* $31 = csr */
69 /* convert condition code register number to csr bit */
70 const unsigned int fpucondbit[8] = {
81 /* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
82 static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
83 static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
84 static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
85 static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
88 * This functions translates a 32-bit microMIPS instruction
89 * into a 32-bit MIPS32 instruction. Returns 0 on success
90 * and SIGILL otherwise.
92 static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
94 union mips_instruction insn = *insn_ptr;
95 union mips_instruction mips32_insn = insn;
98 switch (insn.mm_i_format.opcode) {
100 mips32_insn.mm_i_format.opcode = ldc1_op;
101 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
102 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
105 mips32_insn.mm_i_format.opcode = lwc1_op;
106 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
107 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
110 mips32_insn.mm_i_format.opcode = sdc1_op;
111 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
112 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
115 mips32_insn.mm_i_format.opcode = swc1_op;
116 mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
117 mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
120 /* NOTE: offset is << by 1 if in microMIPS mode. */
121 if ((insn.mm_i_format.rt == mm_bc1f_op) ||
122 (insn.mm_i_format.rt == mm_bc1t_op)) {
123 mips32_insn.fb_format.opcode = cop1_op;
124 mips32_insn.fb_format.bc = bc_op;
125 mips32_insn.fb_format.flag =
126 (insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
131 switch (insn.mm_fp0_format.func) {
140 op = insn.mm_fp0_format.func;
141 if (op == mm_32f_01_op)
143 else if (op == mm_32f_11_op)
145 else if (op == mm_32f_02_op)
147 else if (op == mm_32f_12_op)
149 else if (op == mm_32f_41_op)
151 else if (op == mm_32f_51_op)
153 else if (op == mm_32f_42_op)
157 mips32_insn.fp6_format.opcode = cop1x_op;
158 mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
159 mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
160 mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
161 mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
162 mips32_insn.fp6_format.func = func;
165 func = -1; /* Invalid */
166 op = insn.mm_fp5_format.op & 0x7;
167 if (op == mm_ldxc1_op)
169 else if (op == mm_sdxc1_op)
171 else if (op == mm_lwxc1_op)
173 else if (op == mm_swxc1_op)
177 mips32_insn.r_format.opcode = cop1x_op;
178 mips32_insn.r_format.rs =
179 insn.mm_fp5_format.base;
180 mips32_insn.r_format.rt =
181 insn.mm_fp5_format.index;
182 mips32_insn.r_format.rd = 0;
183 mips32_insn.r_format.re = insn.mm_fp5_format.fd;
184 mips32_insn.r_format.func = func;
189 op = -1; /* Invalid */
190 if (insn.mm_fp2_format.op == mm_fmovt_op)
192 else if (insn.mm_fp2_format.op == mm_fmovf_op)
195 mips32_insn.fp0_format.opcode = cop1_op;
196 mips32_insn.fp0_format.fmt =
197 sdps_format[insn.mm_fp2_format.fmt];
198 mips32_insn.fp0_format.ft =
199 (insn.mm_fp2_format.cc<<2) + op;
200 mips32_insn.fp0_format.fs =
201 insn.mm_fp2_format.fs;
202 mips32_insn.fp0_format.fd =
203 insn.mm_fp2_format.fd;
204 mips32_insn.fp0_format.func = fmovc_op;
209 func = -1; /* Invalid */
210 if (insn.mm_fp0_format.op == mm_fadd_op)
212 else if (insn.mm_fp0_format.op == mm_fsub_op)
214 else if (insn.mm_fp0_format.op == mm_fmul_op)
216 else if (insn.mm_fp0_format.op == mm_fdiv_op)
219 mips32_insn.fp0_format.opcode = cop1_op;
220 mips32_insn.fp0_format.fmt =
221 sdps_format[insn.mm_fp0_format.fmt];
222 mips32_insn.fp0_format.ft =
223 insn.mm_fp0_format.ft;
224 mips32_insn.fp0_format.fs =
225 insn.mm_fp0_format.fs;
226 mips32_insn.fp0_format.fd =
227 insn.mm_fp0_format.fd;
228 mips32_insn.fp0_format.func = func;
233 func = -1; /* Invalid */
234 if (insn.mm_fp0_format.op == mm_fmovn_op)
236 else if (insn.mm_fp0_format.op == mm_fmovz_op)
239 mips32_insn.fp0_format.opcode = cop1_op;
240 mips32_insn.fp0_format.fmt =
241 sdps_format[insn.mm_fp0_format.fmt];
242 mips32_insn.fp0_format.ft =
243 insn.mm_fp0_format.ft;
244 mips32_insn.fp0_format.fs =
245 insn.mm_fp0_format.fs;
246 mips32_insn.fp0_format.fd =
247 insn.mm_fp0_format.fd;
248 mips32_insn.fp0_format.func = func;
252 case mm_32f_73_op: /* POOL32FXF */
253 switch (insn.mm_fp1_format.op) {
258 if ((insn.mm_fp1_format.op & 0x7f) ==
263 mips32_insn.r_format.opcode = spec_op;
264 mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
265 mips32_insn.r_format.rt =
266 (insn.mm_fp4_format.cc << 2) + op;
267 mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
268 mips32_insn.r_format.re = 0;
269 mips32_insn.r_format.func = movc_op;
275 if ((insn.mm_fp1_format.op & 0x7f) ==
278 fmt = swl_format[insn.mm_fp3_format.fmt];
281 fmt = dwl_format[insn.mm_fp3_format.fmt];
283 mips32_insn.fp0_format.opcode = cop1_op;
284 mips32_insn.fp0_format.fmt = fmt;
285 mips32_insn.fp0_format.ft = 0;
286 mips32_insn.fp0_format.fs =
287 insn.mm_fp3_format.fs;
288 mips32_insn.fp0_format.fd =
289 insn.mm_fp3_format.rt;
290 mips32_insn.fp0_format.func = func;
298 if ((insn.mm_fp1_format.op & 0x7f) ==
301 else if ((insn.mm_fp1_format.op & 0x7f) ==
306 mips32_insn.fp0_format.opcode = cop1_op;
307 mips32_insn.fp0_format.fmt =
308 sdps_format[insn.mm_fp3_format.fmt];
309 mips32_insn.fp0_format.ft = 0;
310 mips32_insn.fp0_format.fs =
311 insn.mm_fp3_format.fs;
312 mips32_insn.fp0_format.fd =
313 insn.mm_fp3_format.rt;
314 mips32_insn.fp0_format.func = func;
326 if (insn.mm_fp1_format.op == mm_ffloorl_op)
328 else if (insn.mm_fp1_format.op == mm_ffloorw_op)
330 else if (insn.mm_fp1_format.op == mm_fceill_op)
332 else if (insn.mm_fp1_format.op == mm_fceilw_op)
334 else if (insn.mm_fp1_format.op == mm_ftruncl_op)
336 else if (insn.mm_fp1_format.op == mm_ftruncw_op)
338 else if (insn.mm_fp1_format.op == mm_froundl_op)
340 else if (insn.mm_fp1_format.op == mm_froundw_op)
342 else if (insn.mm_fp1_format.op == mm_fcvtl_op)
346 mips32_insn.fp0_format.opcode = cop1_op;
347 mips32_insn.fp0_format.fmt =
348 sd_format[insn.mm_fp1_format.fmt];
349 mips32_insn.fp0_format.ft = 0;
350 mips32_insn.fp0_format.fs =
351 insn.mm_fp1_format.fs;
352 mips32_insn.fp0_format.fd =
353 insn.mm_fp1_format.rt;
354 mips32_insn.fp0_format.func = func;
359 if (insn.mm_fp1_format.op == mm_frsqrt_op)
361 else if (insn.mm_fp1_format.op == mm_fsqrt_op)
365 mips32_insn.fp0_format.opcode = cop1_op;
366 mips32_insn.fp0_format.fmt =
367 sdps_format[insn.mm_fp1_format.fmt];
368 mips32_insn.fp0_format.ft = 0;
369 mips32_insn.fp0_format.fs =
370 insn.mm_fp1_format.fs;
371 mips32_insn.fp0_format.fd =
372 insn.mm_fp1_format.rt;
373 mips32_insn.fp0_format.func = func;
381 if (insn.mm_fp1_format.op == mm_mfc1_op)
383 else if (insn.mm_fp1_format.op == mm_mtc1_op)
385 else if (insn.mm_fp1_format.op == mm_cfc1_op)
387 else if (insn.mm_fp1_format.op == mm_ctc1_op)
389 else if (insn.mm_fp1_format.op == mm_mfhc1_op)
393 mips32_insn.fp1_format.opcode = cop1_op;
394 mips32_insn.fp1_format.op = op;
395 mips32_insn.fp1_format.rt =
396 insn.mm_fp1_format.rt;
397 mips32_insn.fp1_format.fs =
398 insn.mm_fp1_format.fs;
399 mips32_insn.fp1_format.fd = 0;
400 mips32_insn.fp1_format.func = 0;
406 case mm_32f_74_op: /* c.cond.fmt */
407 mips32_insn.fp0_format.opcode = cop1_op;
408 mips32_insn.fp0_format.fmt =
409 sdps_format[insn.mm_fp4_format.fmt];
410 mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
411 mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
412 mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
413 mips32_insn.fp0_format.func =
414 insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
424 *insn_ptr = mips32_insn;
429 * Redundant with logic already in kernel/branch.c,
430 * embedded in compute_return_epc. At some point,
431 * a single subroutine should be used across both
434 static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
435 unsigned long *contpc)
437 union mips_instruction insn = (union mips_instruction)dec_insn.insn;
439 unsigned int bit = 0;
441 switch (insn.i_format.opcode) {
443 switch (insn.r_format.func) {
445 regs->regs[insn.r_format.rd] =
446 regs->cp0_epc + dec_insn.pc_inc +
447 dec_insn.next_pc_inc;
450 /* For R6, JR already emulated in jalr_op */
451 if (NO_R6EMU && insn.r_format.opcode == jr_op)
453 *contpc = regs->regs[insn.r_format.rs];
458 switch (insn.i_format.rt) {
461 if (NO_R6EMU && (insn.i_format.rs ||
462 insn.i_format.rt == bltzall_op))
465 regs->regs[31] = regs->cp0_epc +
467 dec_insn.next_pc_inc;
473 if ((long)regs->regs[insn.i_format.rs] < 0)
474 *contpc = regs->cp0_epc +
476 (insn.i_format.simmediate << 2);
478 *contpc = regs->cp0_epc +
480 dec_insn.next_pc_inc;
484 if (NO_R6EMU && (insn.i_format.rs ||
485 insn.i_format.rt == bgezall_op))
488 regs->regs[31] = regs->cp0_epc +
490 dec_insn.next_pc_inc;
496 if ((long)regs->regs[insn.i_format.rs] >= 0)
497 *contpc = regs->cp0_epc +
499 (insn.i_format.simmediate << 2);
501 *contpc = regs->cp0_epc +
503 dec_insn.next_pc_inc;
510 regs->regs[31] = regs->cp0_epc +
512 dec_insn.next_pc_inc;
515 *contpc = regs->cp0_epc + dec_insn.pc_inc;
518 *contpc |= (insn.j_format.target << 2);
519 /* Set microMIPS mode bit: XOR for jalx. */
526 if (regs->regs[insn.i_format.rs] ==
527 regs->regs[insn.i_format.rt])
528 *contpc = regs->cp0_epc +
530 (insn.i_format.simmediate << 2);
532 *contpc = regs->cp0_epc +
534 dec_insn.next_pc_inc;
540 if (regs->regs[insn.i_format.rs] !=
541 regs->regs[insn.i_format.rt])
542 *contpc = regs->cp0_epc +
544 (insn.i_format.simmediate << 2);
546 *contpc = regs->cp0_epc +
548 dec_insn.next_pc_inc;
556 * Compact branches for R6 for the
557 * blez and blezl opcodes.
558 * BLEZ | rs = 0 | rt != 0 == BLEZALC
559 * BLEZ | rs = rt != 0 == BGEZALC
560 * BLEZ | rs != 0 | rt != 0 == BGEUC
561 * BLEZL | rs = 0 | rt != 0 == BLEZC
562 * BLEZL | rs = rt != 0 == BGEZC
563 * BLEZL | rs != 0 | rt != 0 == BGEC
565 * For real BLEZ{,L}, rt is always 0.
567 if (cpu_has_mips_r6 && insn.i_format.rt) {
568 if ((insn.i_format.opcode == blez_op) &&
569 ((!insn.i_format.rs && insn.i_format.rt) ||
570 (insn.i_format.rs == insn.i_format.rt)))
571 regs->regs[31] = regs->cp0_epc +
573 *contpc = regs->cp0_epc + dec_insn.pc_inc +
574 dec_insn.next_pc_inc;
578 if ((long)regs->regs[insn.i_format.rs] <= 0)
579 *contpc = regs->cp0_epc +
581 (insn.i_format.simmediate << 2);
583 *contpc = regs->cp0_epc +
585 dec_insn.next_pc_inc;
592 * Compact branches for R6 for the
593 * bgtz and bgtzl opcodes.
594 * BGTZ | rs = 0 | rt != 0 == BGTZALC
595 * BGTZ | rs = rt != 0 == BLTZALC
596 * BGTZ | rs != 0 | rt != 0 == BLTUC
597 * BGTZL | rs = 0 | rt != 0 == BGTZC
598 * BGTZL | rs = rt != 0 == BLTZC
599 * BGTZL | rs != 0 | rt != 0 == BLTC
601 * *ZALC varint for BGTZ &&& rt != 0
602 * For real GTZ{,L}, rt is always 0.
604 if (cpu_has_mips_r6 && insn.i_format.rt) {
605 if ((insn.i_format.opcode == blez_op) &&
606 ((!insn.i_format.rs && insn.i_format.rt) ||
607 (insn.i_format.rs == insn.i_format.rt)))
608 regs->regs[31] = regs->cp0_epc +
610 *contpc = regs->cp0_epc + dec_insn.pc_inc +
611 dec_insn.next_pc_inc;
616 if ((long)regs->regs[insn.i_format.rs] > 0)
617 *contpc = regs->cp0_epc +
619 (insn.i_format.simmediate << 2);
621 *contpc = regs->cp0_epc +
623 dec_insn.next_pc_inc;
627 if (!cpu_has_mips_r6)
629 if (insn.i_format.rt && !insn.i_format.rs)
630 regs->regs[31] = regs->cp0_epc + 4;
631 *contpc = regs->cp0_epc + dec_insn.pc_inc +
632 dec_insn.next_pc_inc;
635 #ifdef CONFIG_CPU_CAVIUM_OCTEON
636 case lwc2_op: /* This is bbit0 on Octeon */
637 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
638 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
640 *contpc = regs->cp0_epc + 8;
642 case ldc2_op: /* This is bbit032 on Octeon */
643 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
644 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
646 *contpc = regs->cp0_epc + 8;
648 case swc2_op: /* This is bbit1 on Octeon */
649 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
650 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
652 *contpc = regs->cp0_epc + 8;
654 case sdc2_op: /* This is bbit132 on Octeon */
655 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
656 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
658 *contpc = regs->cp0_epc + 8;
663 * Only valid for MIPS R6 but we can still end up
664 * here from a broken userland so just tell emulator
665 * this is not a branch and let it break later on.
667 if (!cpu_has_mips_r6)
669 *contpc = regs->cp0_epc + dec_insn.pc_inc +
670 dec_insn.next_pc_inc;
674 if (!cpu_has_mips_r6)
676 regs->regs[31] = regs->cp0_epc + 4;
677 *contpc = regs->cp0_epc + dec_insn.pc_inc +
678 dec_insn.next_pc_inc;
682 if (!cpu_has_mips_r6)
684 *contpc = regs->cp0_epc + dec_insn.pc_inc +
685 dec_insn.next_pc_inc;
689 if (!cpu_has_mips_r6)
691 if (!insn.i_format.rs)
692 regs->regs[31] = regs->cp0_epc + 4;
693 *contpc = regs->cp0_epc + dec_insn.pc_inc +
694 dec_insn.next_pc_inc;
700 /* Need to check for R6 bc1nez and bc1eqz branches */
701 if (cpu_has_mips_r6 &&
702 ((insn.i_format.rs == bc1eqz_op) ||
703 (insn.i_format.rs == bc1nez_op))) {
705 switch (insn.i_format.rs) {
707 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)
711 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1))
716 *contpc = regs->cp0_epc +
718 (insn.i_format.simmediate << 2);
720 *contpc = regs->cp0_epc +
722 dec_insn.next_pc_inc;
726 /* R2/R6 compatible cop1 instruction. Fall through */
729 if (insn.i_format.rs == bc_op) {
732 fcr31 = read_32bit_cp1_register(CP1_STATUS);
734 fcr31 = current->thread.fpu.fcr31;
737 bit = (insn.i_format.rt >> 2);
740 switch (insn.i_format.rt & 3) {
743 if (~fcr31 & (1 << bit))
744 *contpc = regs->cp0_epc +
746 (insn.i_format.simmediate << 2);
748 *contpc = regs->cp0_epc +
750 dec_insn.next_pc_inc;
754 if (fcr31 & (1 << bit))
755 *contpc = regs->cp0_epc +
757 (insn.i_format.simmediate << 2);
759 *contpc = regs->cp0_epc +
761 dec_insn.next_pc_inc;
771 * In the Linux kernel, we support selection of FPR format on the
772 * basis of the Status.FR bit. If an FPU is not present, the FR bit
773 * is hardwired to zero, which would imply a 32-bit FPU even for
774 * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
775 * FPU emu is slow and bulky and optimizing this function offers fairly
776 * sizeable benefits so we try to be clever and make this function return
777 * a constant whenever possible, that is on 64-bit kernels without O32
778 * compatibility enabled and on 32-bit without 64-bit FPU support.
780 static inline int cop1_64bit(struct pt_regs *xcp)
782 if (config_enabled(CONFIG_64BIT) && !config_enabled(CONFIG_MIPS32_O32))
784 else if (config_enabled(CONFIG_32BIT) &&
785 !config_enabled(CONFIG_MIPS_O32_FP64_SUPPORT))
788 return !test_thread_flag(TIF_32BIT_FPREGS);
791 static inline bool hybrid_fprs(void)
793 return test_thread_flag(TIF_HYBRID_FPREGS);
796 #define SIFROMREG(si, x) \
798 if (cop1_64bit(xcp) && !hybrid_fprs()) \
799 (si) = (int)get_fpr32(&ctx->fpr[x], 0); \
801 (si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
804 #define SITOREG(si, x) \
806 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
808 set_fpr32(&ctx->fpr[x], 0, si); \
809 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
810 set_fpr32(&ctx->fpr[x], i, 0); \
812 set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
816 #define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
818 #define SITOHREG(si, x) \
821 set_fpr32(&ctx->fpr[x], 1, si); \
822 for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
823 set_fpr32(&ctx->fpr[x], i, 0); \
826 #define DIFROMREG(di, x) \
827 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
829 #define DITOREG(di, x) \
832 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
833 set_fpr64(&ctx->fpr[fpr], 0, di); \
834 for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
835 set_fpr64(&ctx->fpr[fpr], i, 0); \
838 #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
839 #define SPTOREG(sp, x) SITOREG((sp).bits, x)
840 #define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
841 #define DPTOREG(dp, x) DITOREG((dp).bits, x)
844 * Emulate a CFC1 instruction.
846 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
851 if (MIPSInst_RD(ir) == FPCREG_CSR) {
853 pr_debug("%p gpr[%d]<-csr=%08x\n",
854 (void *)xcp->cp0_epc,
855 MIPSInst_RT(ir), value);
856 } else if (MIPSInst_RD(ir) == FPCREG_RID)
857 value = current_cpu_data.fpu_id;
861 xcp->regs[MIPSInst_RT(ir)] = value;
865 * Emulate a CTC1 instruction.
867 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
872 if (MIPSInst_RT(ir) == 0)
875 value = xcp->regs[MIPSInst_RT(ir)];
877 /* we only have one writable control reg
879 if (MIPSInst_RD(ir) == FPCREG_CSR) {
880 pr_debug("%p gpr[%d]->csr=%08x\n",
881 (void *)xcp->cp0_epc,
882 MIPSInst_RT(ir), value);
884 /* Don't write reserved bits. */
885 ctx->fcr31 = value & ~FPU_CSR_RSVD;
890 * Emulate the single floating point instruction pointed at by EPC.
891 * Two instructions if the instruction is in a branch delay slot.
894 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
895 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
897 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
898 unsigned int cond, cbit;
908 * These are giving gcc a gentle hint about what to expect in
909 * dec_inst in order to do better optimization.
911 if (!cpu_has_mmips && dec_insn.micro_mips_mode)
914 /* XXX NEC Vr54xx bug workaround */
915 if (delay_slot(xcp)) {
916 if (dec_insn.micro_mips_mode) {
917 if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
918 clear_delay_slot(xcp);
920 if (!isBranchInstr(xcp, dec_insn, &contpc))
921 clear_delay_slot(xcp);
925 if (delay_slot(xcp)) {
927 * The instruction to be emulated is in a branch delay slot
928 * which means that we have to emulate the branch instruction
929 * BEFORE we do the cop1 instruction.
931 * This branch could be a COP1 branch, but in that case we
932 * would have had a trap for that instruction, and would not
933 * come through this route.
935 * Linux MIPS branch emulator operates on context, updating the
938 ir = dec_insn.next_insn; /* process delay slot instr */
939 pc_inc = dec_insn.next_pc_inc;
941 ir = dec_insn.insn; /* process current instr */
942 pc_inc = dec_insn.pc_inc;
946 * Since microMIPS FPU instructios are a subset of MIPS32 FPU
947 * instructions, we want to convert microMIPS FPU instructions
948 * into MIPS32 instructions so that we could reuse all of the
949 * FPU emulation code.
951 * NOTE: We cannot do this for branch instructions since they
952 * are not a subset. Example: Cannot emulate a 16-bit
953 * aligned target address with a MIPS32 instruction.
955 if (dec_insn.micro_mips_mode) {
957 * If next instruction is a 16-bit instruction, then it
958 * it cannot be a FPU instruction. This could happen
959 * since we can be called for non-FPU instructions.
962 (microMIPS32_to_MIPS32((union mips_instruction *)&ir)
968 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
969 MIPS_FPU_EMU_INC_STATS(emulated);
970 switch (MIPSInst_OPCODE(ir)) {
972 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
974 MIPS_FPU_EMU_INC_STATS(loads);
976 if (!access_ok(VERIFY_READ, dva, sizeof(u64))) {
977 MIPS_FPU_EMU_INC_STATS(errors);
981 if (__get_user(dval, dva)) {
982 MIPS_FPU_EMU_INC_STATS(errors);
986 DITOREG(dval, MIPSInst_RT(ir));
990 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
992 MIPS_FPU_EMU_INC_STATS(stores);
993 DIFROMREG(dval, MIPSInst_RT(ir));
994 if (!access_ok(VERIFY_WRITE, dva, sizeof(u64))) {
995 MIPS_FPU_EMU_INC_STATS(errors);
999 if (__put_user(dval, dva)) {
1000 MIPS_FPU_EMU_INC_STATS(errors);
1007 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1009 MIPS_FPU_EMU_INC_STATS(loads);
1010 if (!access_ok(VERIFY_READ, wva, sizeof(u32))) {
1011 MIPS_FPU_EMU_INC_STATS(errors);
1015 if (__get_user(wval, wva)) {
1016 MIPS_FPU_EMU_INC_STATS(errors);
1020 SITOREG(wval, MIPSInst_RT(ir));
1024 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
1026 MIPS_FPU_EMU_INC_STATS(stores);
1027 SIFROMREG(wval, MIPSInst_RT(ir));
1028 if (!access_ok(VERIFY_WRITE, wva, sizeof(u32))) {
1029 MIPS_FPU_EMU_INC_STATS(errors);
1033 if (__put_user(wval, wva)) {
1034 MIPS_FPU_EMU_INC_STATS(errors);
1041 switch (MIPSInst_RS(ir)) {
1043 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1046 /* copregister fs -> gpr[rt] */
1047 if (MIPSInst_RT(ir) != 0) {
1048 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1054 if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
1057 /* copregister fs <- rt */
1058 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1062 if (!cpu_has_mips_r2)
1065 /* copregister rd -> gpr[rt] */
1066 if (MIPSInst_RT(ir) != 0) {
1067 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
1073 if (!cpu_has_mips_r2)
1076 /* copregister rd <- gpr[rt] */
1077 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1081 /* copregister rd -> gpr[rt] */
1082 if (MIPSInst_RT(ir) != 0) {
1083 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
1089 /* copregister rd <- rt */
1090 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1094 /* cop control register rd -> gpr[rt] */
1095 cop1_cfc(xcp, ctx, ir);
1099 /* copregister rd <- rt */
1100 cop1_ctc(xcp, ctx, ir);
1101 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1107 if (delay_slot(xcp))
1110 if (cpu_has_mips_4_5_r)
1111 cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
1113 cbit = FPU_CSR_COND;
1114 cond = ctx->fcr31 & cbit;
1117 switch (MIPSInst_RT(ir) & 3) {
1119 if (cpu_has_mips_2_3_4_5_r)
1126 if (cpu_has_mips_2_3_4_5_r)
1133 set_delay_slot(xcp);
1136 * Branch taken: emulate dslot instruction
1141 * Remember EPC at the branch to point back
1142 * at so that any delay-slot instruction
1143 * signal is not silently ignored.
1145 bcpc = xcp->cp0_epc;
1146 xcp->cp0_epc += dec_insn.pc_inc;
1148 contpc = MIPSInst_SIMM(ir);
1149 ir = dec_insn.next_insn;
1150 if (dec_insn.micro_mips_mode) {
1151 contpc = (xcp->cp0_epc + (contpc << 1));
1153 /* If 16-bit instruction, not FPU. */
1154 if ((dec_insn.next_pc_inc == 2) ||
1155 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
1158 * Since this instruction will
1159 * be put on the stack with
1160 * 32-bit words, get around
1161 * this problem by putting a
1162 * NOP16 as the second one.
1164 if (dec_insn.next_pc_inc == 2)
1165 ir = (ir & (~0xffff)) | MM_NOP16;
1168 * Single step the non-CP1
1169 * instruction in the dslot.
1171 sig = mips_dsemul(xcp, ir,
1174 xcp->cp0_epc = bcpc;
1176 * SIGILL forces out of
1177 * the emulation loop.
1179 return sig ? sig : SIGILL;
1182 contpc = (xcp->cp0_epc + (contpc << 2));
1184 switch (MIPSInst_OPCODE(ir)) {
1191 if (cpu_has_mips_2_3_4_5_r)
1200 if (cpu_has_mips_4_5_64_r2_r6)
1201 /* its one of ours */
1207 switch (MIPSInst_FUNC(ir)) {
1209 if (cpu_has_mips_4_5_r)
1217 xcp->cp0_epc = bcpc;
1222 * Single step the non-cp1
1223 * instruction in the dslot
1225 sig = mips_dsemul(xcp, ir, contpc);
1227 xcp->cp0_epc = bcpc;
1228 /* SIGILL forces out of the emulation loop. */
1229 return sig ? sig : SIGILL;
1230 } else if (likely) { /* branch not taken */
1232 * branch likely nullifies
1233 * dslot if not taken
1235 xcp->cp0_epc += dec_insn.pc_inc;
1236 contpc += dec_insn.pc_inc;
1238 * else continue & execute
1239 * dslot as normal insn
1245 if (!(MIPSInst_RS(ir) & 0x10))
1248 /* a real fpu computation instruction */
1249 if ((sig = fpu_emu(xcp, ctx, ir)))
1255 if (!cpu_has_mips_4_5_64_r2_r6)
1258 sig = fpux_emu(xcp, ctx, ir, fault_addr);
1264 if (!cpu_has_mips_4_5_r)
1267 if (MIPSInst_FUNC(ir) != movc_op)
1269 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1270 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1271 xcp->regs[MIPSInst_RD(ir)] =
1272 xcp->regs[MIPSInst_RS(ir)];
1280 xcp->cp0_epc = contpc;
1281 clear_delay_slot(xcp);
1287 * Conversion table from MIPS compare ops 48-63
1288 * cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
1290 static const unsigned char cmptab[8] = {
1291 0, /* cmp_0 (sig) cmp_sf */
1292 IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
1293 IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
1294 IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
1295 IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
1296 IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
1297 IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
1298 IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
1303 * Additional MIPS4 instructions
1306 #define DEF3OP(name, p, f1, f2, f3) \
1307 static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
1308 union ieee754##p s, union ieee754##p t) \
1310 struct _ieee754_csr ieee754_csr_save; \
1312 ieee754_csr_save = ieee754_csr; \
1314 ieee754_csr_save.cx |= ieee754_csr.cx; \
1315 ieee754_csr_save.sx |= ieee754_csr.sx; \
1317 ieee754_csr.cx |= ieee754_csr_save.cx; \
1318 ieee754_csr.sx |= ieee754_csr_save.sx; \
1322 static union ieee754dp fpemu_dp_recip(union ieee754dp d)
1324 return ieee754dp_div(ieee754dp_one(0), d);
1327 static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
1329 return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
1332 static union ieee754sp fpemu_sp_recip(union ieee754sp s)
1334 return ieee754sp_div(ieee754sp_one(0), s);
1337 static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
1339 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
1342 DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
1343 DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
1344 DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
1345 DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
1346 DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
1347 DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
1348 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
1349 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
1351 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1352 mips_instruction ir, void *__user *fault_addr)
1354 unsigned rcsr = 0; /* resulting csr */
1356 MIPS_FPU_EMU_INC_STATS(cp1xops);
1358 switch (MIPSInst_FMA_FFMT(ir)) {
1359 case s_fmt:{ /* 0 */
1361 union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
1362 union ieee754sp fd, fr, fs, ft;
1366 switch (MIPSInst_FUNC(ir)) {
1368 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1369 xcp->regs[MIPSInst_FT(ir)]);
1371 MIPS_FPU_EMU_INC_STATS(loads);
1372 if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
1373 MIPS_FPU_EMU_INC_STATS(errors);
1377 if (__get_user(val, va)) {
1378 MIPS_FPU_EMU_INC_STATS(errors);
1382 SITOREG(val, MIPSInst_FD(ir));
1386 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1387 xcp->regs[MIPSInst_FT(ir)]);
1389 MIPS_FPU_EMU_INC_STATS(stores);
1391 SIFROMREG(val, MIPSInst_FS(ir));
1392 if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
1393 MIPS_FPU_EMU_INC_STATS(errors);
1397 if (put_user(val, va)) {
1398 MIPS_FPU_EMU_INC_STATS(errors);
1405 handler = fpemu_sp_madd;
1408 handler = fpemu_sp_msub;
1411 handler = fpemu_sp_nmadd;
1414 handler = fpemu_sp_nmsub;
1418 SPFROMREG(fr, MIPSInst_FR(ir));
1419 SPFROMREG(fs, MIPSInst_FS(ir));
1420 SPFROMREG(ft, MIPSInst_FT(ir));
1421 fd = (*handler) (fr, fs, ft);
1422 SPTOREG(fd, MIPSInst_FD(ir));
1425 if (ieee754_cxtest(IEEE754_INEXACT)) {
1426 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1427 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1429 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1430 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1431 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1433 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1434 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1435 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1437 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1438 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1439 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1442 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1443 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1444 /*printk ("SIGFPE: FPU csr = %08x\n",
1457 case d_fmt:{ /* 1 */
1458 union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
1459 union ieee754dp fd, fr, fs, ft;
1463 switch (MIPSInst_FUNC(ir)) {
1465 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1466 xcp->regs[MIPSInst_FT(ir)]);
1468 MIPS_FPU_EMU_INC_STATS(loads);
1469 if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
1470 MIPS_FPU_EMU_INC_STATS(errors);
1474 if (__get_user(val, va)) {
1475 MIPS_FPU_EMU_INC_STATS(errors);
1479 DITOREG(val, MIPSInst_FD(ir));
1483 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1484 xcp->regs[MIPSInst_FT(ir)]);
1486 MIPS_FPU_EMU_INC_STATS(stores);
1487 DIFROMREG(val, MIPSInst_FS(ir));
1488 if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
1489 MIPS_FPU_EMU_INC_STATS(errors);
1493 if (__put_user(val, va)) {
1494 MIPS_FPU_EMU_INC_STATS(errors);
1501 handler = fpemu_dp_madd;
1504 handler = fpemu_dp_msub;
1507 handler = fpemu_dp_nmadd;
1510 handler = fpemu_dp_nmsub;
1514 DPFROMREG(fr, MIPSInst_FR(ir));
1515 DPFROMREG(fs, MIPSInst_FS(ir));
1516 DPFROMREG(ft, MIPSInst_FT(ir));
1517 fd = (*handler) (fr, fs, ft);
1518 DPTOREG(fd, MIPSInst_FD(ir));
1528 if (MIPSInst_FUNC(ir) != pfetch_op)
1531 /* ignore prefx operation */
1544 * Emulate a single COP1 arithmetic instruction.
1546 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
1547 mips_instruction ir)
1549 int rfmt; /* resulting format */
1550 unsigned rcsr = 0; /* resulting csr */
1559 } rv; /* resulting value */
1562 MIPS_FPU_EMU_INC_STATS(cp1ops);
1563 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1564 case s_fmt: { /* 0 */
1566 union ieee754sp(*b) (union ieee754sp, union ieee754sp);
1567 union ieee754sp(*u) (union ieee754sp);
1569 union ieee754sp fs, ft;
1571 switch (MIPSInst_FUNC(ir)) {
1574 handler.b = ieee754sp_add;
1577 handler.b = ieee754sp_sub;
1580 handler.b = ieee754sp_mul;
1583 handler.b = ieee754sp_div;
1588 if (!cpu_has_mips_2_3_4_5_r)
1591 handler.u = ieee754sp_sqrt;
1595 * Note that on some MIPS IV implementations such as the
1596 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1597 * achieve full IEEE-754 accuracy - however this emulator does.
1600 if (!cpu_has_mips_4_5_64_r2_r6)
1603 handler.u = fpemu_sp_rsqrt;
1607 if (!cpu_has_mips_4_5_64_r2_r6)
1610 handler.u = fpemu_sp_recip;
1614 if (!cpu_has_mips_4_5_r)
1617 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1618 if (((ctx->fcr31 & cond) != 0) !=
1619 ((MIPSInst_FT(ir) & 1) != 0))
1621 SPFROMREG(rv.s, MIPSInst_FS(ir));
1625 if (!cpu_has_mips_4_5_r)
1628 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1630 SPFROMREG(rv.s, MIPSInst_FS(ir));
1634 if (!cpu_has_mips_4_5_r)
1637 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1639 SPFROMREG(rv.s, MIPSInst_FS(ir));
1643 handler.u = ieee754sp_abs;
1647 handler.u = ieee754sp_neg;
1652 SPFROMREG(rv.s, MIPSInst_FS(ir));
1655 /* binary op on handler */
1657 SPFROMREG(fs, MIPSInst_FS(ir));
1658 SPFROMREG(ft, MIPSInst_FT(ir));
1660 rv.s = (*handler.b) (fs, ft);
1663 SPFROMREG(fs, MIPSInst_FS(ir));
1664 rv.s = (*handler.u) (fs);
1667 if (ieee754_cxtest(IEEE754_INEXACT)) {
1668 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1669 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1671 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1672 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1673 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1675 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1676 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1677 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1679 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1680 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1681 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1683 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1684 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1685 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1689 /* unary conv ops */
1691 return SIGILL; /* not defined */
1694 SPFROMREG(fs, MIPSInst_FS(ir));
1695 rv.d = ieee754dp_fsp(fs);
1700 SPFROMREG(fs, MIPSInst_FS(ir));
1701 rv.w = ieee754sp_tint(fs);
1709 if (!cpu_has_mips_2_3_4_5_r)
1712 oldrm = ieee754_csr.rm;
1713 SPFROMREG(fs, MIPSInst_FS(ir));
1714 ieee754_csr.rm = MIPSInst_FUNC(ir);
1715 rv.w = ieee754sp_tint(fs);
1716 ieee754_csr.rm = oldrm;
1721 if (!cpu_has_mips_3_4_5_64_r2_r6)
1724 SPFROMREG(fs, MIPSInst_FS(ir));
1725 rv.l = ieee754sp_tlong(fs);
1733 if (!cpu_has_mips_3_4_5_64_r2_r6)
1736 oldrm = ieee754_csr.rm;
1737 SPFROMREG(fs, MIPSInst_FS(ir));
1738 ieee754_csr.rm = MIPSInst_FUNC(ir);
1739 rv.l = ieee754sp_tlong(fs);
1740 ieee754_csr.rm = oldrm;
1745 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1746 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1747 union ieee754sp fs, ft;
1749 SPFROMREG(fs, MIPSInst_FS(ir));
1750 SPFROMREG(ft, MIPSInst_FT(ir));
1751 rv.w = ieee754sp_cmp(fs, ft,
1752 cmptab[cmpop & 0x7], cmpop & 0x8);
1754 if ((cmpop & 0x8) && ieee754_cxtest
1755 (IEEE754_INVALID_OPERATION))
1756 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1768 union ieee754dp fs, ft;
1770 union ieee754dp(*b) (union ieee754dp, union ieee754dp);
1771 union ieee754dp(*u) (union ieee754dp);
1774 switch (MIPSInst_FUNC(ir)) {
1777 handler.b = ieee754dp_add;
1780 handler.b = ieee754dp_sub;
1783 handler.b = ieee754dp_mul;
1786 handler.b = ieee754dp_div;
1791 if (!cpu_has_mips_2_3_4_5_r)
1794 handler.u = ieee754dp_sqrt;
1797 * Note that on some MIPS IV implementations such as the
1798 * R5000 and R8000 the FSQRT and FRECIP instructions do not
1799 * achieve full IEEE-754 accuracy - however this emulator does.
1802 if (!cpu_has_mips_4_5_64_r2_r6)
1805 handler.u = fpemu_dp_rsqrt;
1808 if (!cpu_has_mips_4_5_64_r2_r6)
1811 handler.u = fpemu_dp_recip;
1814 if (!cpu_has_mips_4_5_r)
1817 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1818 if (((ctx->fcr31 & cond) != 0) !=
1819 ((MIPSInst_FT(ir) & 1) != 0))
1821 DPFROMREG(rv.d, MIPSInst_FS(ir));
1824 if (!cpu_has_mips_4_5_r)
1827 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1829 DPFROMREG(rv.d, MIPSInst_FS(ir));
1832 if (!cpu_has_mips_4_5_r)
1835 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1837 DPFROMREG(rv.d, MIPSInst_FS(ir));
1840 handler.u = ieee754dp_abs;
1844 handler.u = ieee754dp_neg;
1849 DPFROMREG(rv.d, MIPSInst_FS(ir));
1852 /* binary op on handler */
1854 DPFROMREG(fs, MIPSInst_FS(ir));
1855 DPFROMREG(ft, MIPSInst_FT(ir));
1857 rv.d = (*handler.b) (fs, ft);
1860 DPFROMREG(fs, MIPSInst_FS(ir));
1861 rv.d = (*handler.u) (fs);
1868 DPFROMREG(fs, MIPSInst_FS(ir));
1869 rv.s = ieee754sp_fdp(fs);
1874 return SIGILL; /* not defined */
1877 DPFROMREG(fs, MIPSInst_FS(ir));
1878 rv.w = ieee754dp_tint(fs); /* wrong */
1886 if (!cpu_has_mips_2_3_4_5_r)
1889 oldrm = ieee754_csr.rm;
1890 DPFROMREG(fs, MIPSInst_FS(ir));
1891 ieee754_csr.rm = MIPSInst_FUNC(ir);
1892 rv.w = ieee754dp_tint(fs);
1893 ieee754_csr.rm = oldrm;
1898 if (!cpu_has_mips_3_4_5_64_r2_r6)
1901 DPFROMREG(fs, MIPSInst_FS(ir));
1902 rv.l = ieee754dp_tlong(fs);
1910 if (!cpu_has_mips_3_4_5_64_r2_r6)
1913 oldrm = ieee754_csr.rm;
1914 DPFROMREG(fs, MIPSInst_FS(ir));
1915 ieee754_csr.rm = MIPSInst_FUNC(ir);
1916 rv.l = ieee754dp_tlong(fs);
1917 ieee754_csr.rm = oldrm;
1922 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1923 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1924 union ieee754dp fs, ft;
1926 DPFROMREG(fs, MIPSInst_FS(ir));
1927 DPFROMREG(ft, MIPSInst_FT(ir));
1928 rv.w = ieee754dp_cmp(fs, ft,
1929 cmptab[cmpop & 0x7], cmpop & 0x8);
1934 (IEEE754_INVALID_OPERATION))
1935 rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
1948 switch (MIPSInst_FUNC(ir)) {
1950 /* convert word to single precision real */
1951 SPFROMREG(fs, MIPSInst_FS(ir));
1952 rv.s = ieee754sp_fint(fs.bits);
1956 /* convert word to double precision real */
1957 SPFROMREG(fs, MIPSInst_FS(ir));
1958 rv.d = ieee754dp_fint(fs.bits);
1969 if (!cpu_has_mips_3_4_5_64_r2_r6)
1972 DIFROMREG(bits, MIPSInst_FS(ir));
1974 switch (MIPSInst_FUNC(ir)) {
1976 /* convert long to single precision real */
1977 rv.s = ieee754sp_flong(bits);
1981 /* convert long to double precision real */
1982 rv.d = ieee754dp_flong(bits);
1995 * Update the fpu CSR register for this operation.
1996 * If an exception is required, generate a tidy SIGFPE exception,
1997 * without updating the result register.
1998 * Note: cause exception bits do not accumulate, they are rewritten
1999 * for each op; only the flag/sticky bits accumulate.
2001 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
2002 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
2003 /*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
2008 * Now we can safely write the result back to the register file.
2013 if (cpu_has_mips_4_5_r)
2014 cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
2016 cbit = FPU_CSR_COND;
2020 ctx->fcr31 &= ~cbit;
2024 DPTOREG(rv.d, MIPSInst_FD(ir));
2027 SPTOREG(rv.s, MIPSInst_FD(ir));
2030 SITOREG(rv.w, MIPSInst_FD(ir));
2033 if (!cpu_has_mips_3_4_5_64_r2_r6)
2036 DITOREG(rv.l, MIPSInst_FD(ir));
2045 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
2046 int has_fpu, void *__user *fault_addr)
2048 unsigned long oldepc, prevepc;
2049 struct mm_decoded_insn dec_insn;
2054 oldepc = xcp->cp0_epc;
2056 prevepc = xcp->cp0_epc;
2058 if (get_isa16_mode(prevepc) && cpu_has_mmips) {
2060 * Get next 2 microMIPS instructions and convert them
2061 * into 32-bit instructions.
2063 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
2064 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
2065 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
2066 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
2067 MIPS_FPU_EMU_INC_STATS(errors);
2072 /* Get first instruction. */
2073 if (mm_insn_16bit(*instr_ptr)) {
2074 /* Duplicate the half-word. */
2075 dec_insn.insn = (*instr_ptr << 16) |
2077 /* 16-bit instruction. */
2078 dec_insn.pc_inc = 2;
2081 dec_insn.insn = (*instr_ptr << 16) |
2083 /* 32-bit instruction. */
2084 dec_insn.pc_inc = 4;
2087 /* Get second instruction. */
2088 if (mm_insn_16bit(*instr_ptr)) {
2089 /* Duplicate the half-word. */
2090 dec_insn.next_insn = (*instr_ptr << 16) |
2092 /* 16-bit instruction. */
2093 dec_insn.next_pc_inc = 2;
2095 dec_insn.next_insn = (*instr_ptr << 16) |
2097 /* 32-bit instruction. */
2098 dec_insn.next_pc_inc = 4;
2100 dec_insn.micro_mips_mode = 1;
2102 if ((get_user(dec_insn.insn,
2103 (mips_instruction __user *) xcp->cp0_epc)) ||
2104 (get_user(dec_insn.next_insn,
2105 (mips_instruction __user *)(xcp->cp0_epc+4)))) {
2106 MIPS_FPU_EMU_INC_STATS(errors);
2109 dec_insn.pc_inc = 4;
2110 dec_insn.next_pc_inc = 4;
2111 dec_insn.micro_mips_mode = 0;
2114 if ((dec_insn.insn == 0) ||
2115 ((dec_insn.pc_inc == 2) &&
2116 ((dec_insn.insn & 0xffff) == MM_NOP16)))
2117 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
2120 * The 'ieee754_csr' is an alias of ctx->fcr31.
2121 * No need to copy ctx->fcr31 to ieee754_csr.
2123 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
2132 } while (xcp->cp0_epc > prevepc);
2134 /* SIGILL indicates a non-fpu instruction */
2135 if (sig == SIGILL && xcp->cp0_epc != oldepc)
2136 /* but if EPC has advanced, then ignore it */