2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * KVM/MIPS: Instruction/Exception emulation
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/ktime.h>
15 #include <linux/kvm_host.h>
16 #include <linux/module.h>
17 #include <linux/vmalloc.h>
19 #include <linux/bootmem.h>
20 #include <linux/random.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cacheops.h>
24 #include <asm/cpu-info.h>
25 #include <asm/mmu_context.h>
26 #include <asm/tlbflush.h>
30 #include <asm/r4kcache.h>
31 #define CONFIG_MIPS_MT
34 #include "interrupt.h"
40 * Compute the return address and do emulate branch simulation, if required.
41 * This function should be called only in branch delay slot active.
43 unsigned long kvm_compute_return_epc(struct kvm_vcpu *vcpu,
46 unsigned int dspcontrol;
47 union mips_instruction insn;
48 struct kvm_vcpu_arch *arch = &vcpu->arch;
50 long nextpc = KVM_INVALID_INST;
55 /* Read the instruction */
56 insn.word = kvm_get_inst((uint32_t *) epc, vcpu);
58 if (insn.word == KVM_INVALID_INST)
59 return KVM_INVALID_INST;
61 switch (insn.i_format.opcode) {
62 /* jr and jalr are in r_format format. */
64 switch (insn.r_format.func) {
66 arch->gprs[insn.r_format.rd] = epc + 8;
69 nextpc = arch->gprs[insn.r_format.rs];
75 * This group contains:
76 * bltz_op, bgez_op, bltzl_op, bgezl_op,
77 * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
80 switch (insn.i_format.rt) {
83 if ((long)arch->gprs[insn.i_format.rs] < 0)
84 epc = epc + 4 + (insn.i_format.simmediate << 2);
92 if ((long)arch->gprs[insn.i_format.rs] >= 0)
93 epc = epc + 4 + (insn.i_format.simmediate << 2);
101 arch->gprs[31] = epc + 8;
102 if ((long)arch->gprs[insn.i_format.rs] < 0)
103 epc = epc + 4 + (insn.i_format.simmediate << 2);
111 arch->gprs[31] = epc + 8;
112 if ((long)arch->gprs[insn.i_format.rs] >= 0)
113 epc = epc + 4 + (insn.i_format.simmediate << 2);
122 dspcontrol = rddsp(0x01);
124 if (dspcontrol >= 32)
125 epc = epc + 4 + (insn.i_format.simmediate << 2);
133 /* These are unconditional and in j_format. */
135 arch->gprs[31] = instpc + 8;
140 epc |= (insn.j_format.target << 2);
144 /* These are conditional and in i_format. */
147 if (arch->gprs[insn.i_format.rs] ==
148 arch->gprs[insn.i_format.rt])
149 epc = epc + 4 + (insn.i_format.simmediate << 2);
157 if (arch->gprs[insn.i_format.rs] !=
158 arch->gprs[insn.i_format.rt])
159 epc = epc + 4 + (insn.i_format.simmediate << 2);
165 case blez_op: /* not really i_format */
167 /* rt field assumed to be zero */
168 if ((long)arch->gprs[insn.i_format.rs] <= 0)
169 epc = epc + 4 + (insn.i_format.simmediate << 2);
177 /* rt field assumed to be zero */
178 if ((long)arch->gprs[insn.i_format.rs] > 0)
179 epc = epc + 4 + (insn.i_format.simmediate << 2);
185 /* And now the FPA/cp1 branch instructions. */
187 kvm_err("%s: unsupported cop1_op\n", __func__);
194 kvm_err("%s: unaligned epc\n", __func__);
198 kvm_err("%s: DSP branch but not DSP ASE\n", __func__);
202 enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause)
204 unsigned long branch_pc;
205 enum emulation_result er = EMULATE_DONE;
207 if (cause & CAUSEF_BD) {
208 branch_pc = kvm_compute_return_epc(vcpu, vcpu->arch.pc);
209 if (branch_pc == KVM_INVALID_INST) {
212 vcpu->arch.pc = branch_pc;
213 kvm_debug("BD update_pc(): New PC: %#lx\n",
219 kvm_debug("update_pc(): New PC: %#lx\n", vcpu->arch.pc);
225 * kvm_mips_count_disabled() - Find whether the CP0_Count timer is disabled.
226 * @vcpu: Virtual CPU.
228 * Returns: 1 if the CP0_Count timer is disabled by either the guest
229 * CP0_Cause.DC bit or the count_ctl.DC bit.
230 * 0 otherwise (in which case CP0_Count timer is running).
232 static inline int kvm_mips_count_disabled(struct kvm_vcpu *vcpu)
234 struct mips_coproc *cop0 = vcpu->arch.cop0;
236 return (vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) ||
237 (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC);
241 * kvm_mips_ktime_to_count() - Scale ktime_t to a 32-bit count.
243 * Caches the dynamic nanosecond bias in vcpu->arch.count_dyn_bias.
245 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
247 static uint32_t kvm_mips_ktime_to_count(struct kvm_vcpu *vcpu, ktime_t now)
252 now_ns = ktime_to_ns(now);
253 delta = now_ns + vcpu->arch.count_dyn_bias;
255 if (delta >= vcpu->arch.count_period) {
256 /* If delta is out of safe range the bias needs adjusting */
257 periods = div64_s64(now_ns, vcpu->arch.count_period);
258 vcpu->arch.count_dyn_bias = -periods * vcpu->arch.count_period;
259 /* Recalculate delta with new bias */
260 delta = now_ns + vcpu->arch.count_dyn_bias;
264 * We've ensured that:
265 * delta < count_period
267 * Therefore the intermediate delta*count_hz will never overflow since
268 * at the boundary condition:
269 * delta = count_period
270 * delta = NSEC_PER_SEC * 2^32 / count_hz
271 * delta * count_hz = NSEC_PER_SEC * 2^32
273 return div_u64(delta * vcpu->arch.count_hz, NSEC_PER_SEC);
277 * kvm_mips_count_time() - Get effective current time.
278 * @vcpu: Virtual CPU.
280 * Get effective monotonic ktime. This is usually a straightforward ktime_get(),
281 * except when the master disable bit is set in count_ctl, in which case it is
282 * count_resume, i.e. the time that the count was disabled.
284 * Returns: Effective monotonic ktime for CP0_Count.
286 static inline ktime_t kvm_mips_count_time(struct kvm_vcpu *vcpu)
288 if (unlikely(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
289 return vcpu->arch.count_resume;
295 * kvm_mips_read_count_running() - Read the current count value as if running.
296 * @vcpu: Virtual CPU.
297 * @now: Kernel time to read CP0_Count at.
299 * Returns the current guest CP0_Count register at time @now and handles if the
300 * timer interrupt is pending and hasn't been handled yet.
302 * Returns: The current value of the guest CP0_Count register.
304 static uint32_t kvm_mips_read_count_running(struct kvm_vcpu *vcpu, ktime_t now)
309 /* Is the hrtimer pending? */
310 expires = hrtimer_get_expires(&vcpu->arch.comparecount_timer);
311 if (ktime_compare(now, expires) >= 0) {
313 * Cancel it while we handle it so there's no chance of
314 * interference with the timeout handler.
316 running = hrtimer_cancel(&vcpu->arch.comparecount_timer);
318 /* Nothing should be waiting on the timeout */
319 kvm_mips_callbacks->queue_timer_int(vcpu);
322 * Restart the timer if it was running based on the expiry time
323 * we read, so that we don't push it back 2 periods.
326 expires = ktime_add_ns(expires,
327 vcpu->arch.count_period);
328 hrtimer_start(&vcpu->arch.comparecount_timer, expires,
333 /* Return the biased and scaled guest CP0_Count */
334 return vcpu->arch.count_bias + kvm_mips_ktime_to_count(vcpu, now);
338 * kvm_mips_read_count() - Read the current count value.
339 * @vcpu: Virtual CPU.
341 * Read the current guest CP0_Count value, taking into account whether the timer
344 * Returns: The current guest CP0_Count value.
346 uint32_t kvm_mips_read_count(struct kvm_vcpu *vcpu)
348 struct mips_coproc *cop0 = vcpu->arch.cop0;
350 /* If count disabled just read static copy of count */
351 if (kvm_mips_count_disabled(vcpu))
352 return kvm_read_c0_guest_count(cop0);
354 return kvm_mips_read_count_running(vcpu, ktime_get());
358 * kvm_mips_freeze_hrtimer() - Safely stop the hrtimer.
359 * @vcpu: Virtual CPU.
360 * @count: Output pointer for CP0_Count value at point of freeze.
362 * Freeze the hrtimer safely and return both the ktime and the CP0_Count value
363 * at the point it was frozen. It is guaranteed that any pending interrupts at
364 * the point it was frozen are handled, and none after that point.
366 * This is useful where the time/CP0_Count is needed in the calculation of the
369 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
371 * Returns: The ktime at the point of freeze.
373 static ktime_t kvm_mips_freeze_hrtimer(struct kvm_vcpu *vcpu,
378 /* stop hrtimer before finding time */
379 hrtimer_cancel(&vcpu->arch.comparecount_timer);
382 /* find count at this point and handle pending hrtimer */
383 *count = kvm_mips_read_count_running(vcpu, now);
389 * kvm_mips_resume_hrtimer() - Resume hrtimer, updating expiry.
390 * @vcpu: Virtual CPU.
391 * @now: ktime at point of resume.
392 * @count: CP0_Count at point of resume.
394 * Resumes the timer and updates the timer expiry based on @now and @count.
395 * This can be used in conjunction with kvm_mips_freeze_timer() when timer
396 * parameters need to be changed.
398 * It is guaranteed that a timer interrupt immediately after resume will be
399 * handled, but not if CP_Compare is exactly at @count. That case is already
400 * handled by kvm_mips_freeze_timer().
402 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
404 static void kvm_mips_resume_hrtimer(struct kvm_vcpu *vcpu,
405 ktime_t now, uint32_t count)
407 struct mips_coproc *cop0 = vcpu->arch.cop0;
412 /* Calculate timeout (wrap 0 to 2^32) */
413 compare = kvm_read_c0_guest_compare(cop0);
414 delta = (u64)(uint32_t)(compare - count - 1) + 1;
415 delta = div_u64(delta * NSEC_PER_SEC, vcpu->arch.count_hz);
416 expire = ktime_add_ns(now, delta);
418 /* Update hrtimer to use new timeout */
419 hrtimer_cancel(&vcpu->arch.comparecount_timer);
420 hrtimer_start(&vcpu->arch.comparecount_timer, expire, HRTIMER_MODE_ABS);
424 * kvm_mips_update_hrtimer() - Update next expiry time of hrtimer.
425 * @vcpu: Virtual CPU.
427 * Recalculates and updates the expiry time of the hrtimer. This can be used
428 * after timer parameters have been altered which do not depend on the time that
429 * the change occurs (in those cases kvm_mips_freeze_hrtimer() and
430 * kvm_mips_resume_hrtimer() are used directly).
432 * It is guaranteed that no timer interrupts will be lost in the process.
434 * Assumes !kvm_mips_count_disabled(@vcpu) (guest CP0_Count timer is running).
436 static void kvm_mips_update_hrtimer(struct kvm_vcpu *vcpu)
442 * freeze_hrtimer takes care of a timer interrupts <= count, and
443 * resume_hrtimer the hrtimer takes care of a timer interrupts > count.
445 now = kvm_mips_freeze_hrtimer(vcpu, &count);
446 kvm_mips_resume_hrtimer(vcpu, now, count);
450 * kvm_mips_write_count() - Modify the count and update timer.
451 * @vcpu: Virtual CPU.
452 * @count: Guest CP0_Count value to set.
454 * Sets the CP0_Count value and updates the timer accordingly.
456 void kvm_mips_write_count(struct kvm_vcpu *vcpu, uint32_t count)
458 struct mips_coproc *cop0 = vcpu->arch.cop0;
462 now = kvm_mips_count_time(vcpu);
463 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
465 if (kvm_mips_count_disabled(vcpu))
466 /* The timer's disabled, adjust the static count */
467 kvm_write_c0_guest_count(cop0, count);
470 kvm_mips_resume_hrtimer(vcpu, now, count);
474 * kvm_mips_init_count() - Initialise timer.
475 * @vcpu: Virtual CPU.
477 * Initialise the timer to a sensible frequency, namely 100MHz, zero it, and set
478 * it going if it's enabled.
480 void kvm_mips_init_count(struct kvm_vcpu *vcpu)
483 vcpu->arch.count_hz = 100*1000*1000;
484 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32,
485 vcpu->arch.count_hz);
486 vcpu->arch.count_dyn_bias = 0;
489 kvm_mips_write_count(vcpu, 0);
493 * kvm_mips_set_count_hz() - Update the frequency of the timer.
494 * @vcpu: Virtual CPU.
495 * @count_hz: Frequency of CP0_Count timer in Hz.
497 * Change the frequency of the CP0_Count timer. This is done atomically so that
498 * CP0_Count is continuous and no timer interrupt is lost.
500 * Returns: -EINVAL if @count_hz is out of range.
503 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz)
505 struct mips_coproc *cop0 = vcpu->arch.cop0;
510 /* ensure the frequency is in a sensible range... */
511 if (count_hz <= 0 || count_hz > NSEC_PER_SEC)
513 /* ... and has actually changed */
514 if (vcpu->arch.count_hz == count_hz)
517 /* Safely freeze timer so we can keep it continuous */
518 dc = kvm_mips_count_disabled(vcpu);
520 now = kvm_mips_count_time(vcpu);
521 count = kvm_read_c0_guest_count(cop0);
523 now = kvm_mips_freeze_hrtimer(vcpu, &count);
526 /* Update the frequency */
527 vcpu->arch.count_hz = count_hz;
528 vcpu->arch.count_period = div_u64((u64)NSEC_PER_SEC << 32, count_hz);
529 vcpu->arch.count_dyn_bias = 0;
531 /* Calculate adjusted bias so dynamic count is unchanged */
532 vcpu->arch.count_bias = count - kvm_mips_ktime_to_count(vcpu, now);
534 /* Update and resume hrtimer */
536 kvm_mips_resume_hrtimer(vcpu, now, count);
541 * kvm_mips_write_compare() - Modify compare and update timer.
542 * @vcpu: Virtual CPU.
543 * @compare: New CP0_Compare value.
545 * Update CP0_Compare to a new value and update the timeout.
547 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, uint32_t compare)
549 struct mips_coproc *cop0 = vcpu->arch.cop0;
551 /* if unchanged, must just be an ack */
552 if (kvm_read_c0_guest_compare(cop0) == compare)
556 kvm_write_c0_guest_compare(cop0, compare);
558 /* Update timeout if count enabled */
559 if (!kvm_mips_count_disabled(vcpu))
560 kvm_mips_update_hrtimer(vcpu);
564 * kvm_mips_count_disable() - Disable count.
565 * @vcpu: Virtual CPU.
567 * Disable the CP0_Count timer. A timer interrupt on or before the final stop
568 * time will be handled but not after.
570 * Assumes CP0_Count was previously enabled but now Guest.CP0_Cause.DC or
571 * count_ctl.DC has been set (count disabled).
573 * Returns: The time that the timer was stopped.
575 static ktime_t kvm_mips_count_disable(struct kvm_vcpu *vcpu)
577 struct mips_coproc *cop0 = vcpu->arch.cop0;
582 hrtimer_cancel(&vcpu->arch.comparecount_timer);
584 /* Set the static count from the dynamic count, handling pending TI */
586 count = kvm_mips_read_count_running(vcpu, now);
587 kvm_write_c0_guest_count(cop0, count);
593 * kvm_mips_count_disable_cause() - Disable count using CP0_Cause.DC.
594 * @vcpu: Virtual CPU.
596 * Disable the CP0_Count timer and set CP0_Cause.DC. A timer interrupt on or
597 * before the final stop time will be handled if the timer isn't disabled by
598 * count_ctl.DC, but not after.
600 * Assumes CP0_Cause.DC is clear (count enabled).
602 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu)
604 struct mips_coproc *cop0 = vcpu->arch.cop0;
606 kvm_set_c0_guest_cause(cop0, CAUSEF_DC);
607 if (!(vcpu->arch.count_ctl & KVM_REG_MIPS_COUNT_CTL_DC))
608 kvm_mips_count_disable(vcpu);
612 * kvm_mips_count_enable_cause() - Enable count using CP0_Cause.DC.
613 * @vcpu: Virtual CPU.
615 * Enable the CP0_Count timer and clear CP0_Cause.DC. A timer interrupt after
616 * the start time will be handled if the timer isn't disabled by count_ctl.DC,
617 * potentially before even returning, so the caller should be careful with
618 * ordering of CP0_Cause modifications so as not to lose it.
620 * Assumes CP0_Cause.DC is set (count disabled).
622 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu)
624 struct mips_coproc *cop0 = vcpu->arch.cop0;
627 kvm_clear_c0_guest_cause(cop0, CAUSEF_DC);
630 * Set the dynamic count to match the static count.
631 * This starts the hrtimer if count_ctl.DC allows it.
632 * Otherwise it conveniently updates the biases.
634 count = kvm_read_c0_guest_count(cop0);
635 kvm_mips_write_count(vcpu, count);
639 * kvm_mips_set_count_ctl() - Update the count control KVM register.
640 * @vcpu: Virtual CPU.
641 * @count_ctl: Count control register new value.
643 * Set the count control KVM register. The timer is updated accordingly.
645 * Returns: -EINVAL if reserved bits are set.
648 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl)
650 struct mips_coproc *cop0 = vcpu->arch.cop0;
651 s64 changed = count_ctl ^ vcpu->arch.count_ctl;
654 uint32_t count, compare;
656 /* Only allow defined bits to be changed */
657 if (changed & ~(s64)(KVM_REG_MIPS_COUNT_CTL_DC))
660 /* Apply new value */
661 vcpu->arch.count_ctl = count_ctl;
663 /* Master CP0_Count disable */
664 if (changed & KVM_REG_MIPS_COUNT_CTL_DC) {
665 /* Is CP0_Cause.DC already disabling CP0_Count? */
666 if (kvm_read_c0_guest_cause(cop0) & CAUSEF_DC) {
667 if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC)
668 /* Just record the current time */
669 vcpu->arch.count_resume = ktime_get();
670 } else if (count_ctl & KVM_REG_MIPS_COUNT_CTL_DC) {
671 /* disable timer and record current time */
672 vcpu->arch.count_resume = kvm_mips_count_disable(vcpu);
675 * Calculate timeout relative to static count at resume
676 * time (wrap 0 to 2^32).
678 count = kvm_read_c0_guest_count(cop0);
679 compare = kvm_read_c0_guest_compare(cop0);
680 delta = (u64)(uint32_t)(compare - count - 1) + 1;
681 delta = div_u64(delta * NSEC_PER_SEC,
682 vcpu->arch.count_hz);
683 expire = ktime_add_ns(vcpu->arch.count_resume, delta);
685 /* Handle pending interrupt */
687 if (ktime_compare(now, expire) >= 0)
688 /* Nothing should be waiting on the timeout */
689 kvm_mips_callbacks->queue_timer_int(vcpu);
691 /* Resume hrtimer without changing bias */
692 count = kvm_mips_read_count_running(vcpu, now);
693 kvm_mips_resume_hrtimer(vcpu, now, count);
701 * kvm_mips_set_count_resume() - Update the count resume KVM register.
702 * @vcpu: Virtual CPU.
703 * @count_resume: Count resume register new value.
705 * Set the count resume KVM register.
707 * Returns: -EINVAL if out of valid range (0..now).
710 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume)
713 * It doesn't make sense for the resume time to be in the future, as it
714 * would be possible for the next interrupt to be more than a full
715 * period in the future.
717 if (count_resume < 0 || count_resume > ktime_to_ns(ktime_get()))
720 vcpu->arch.count_resume = ns_to_ktime(count_resume);
725 * kvm_mips_count_timeout() - Push timer forward on timeout.
726 * @vcpu: Virtual CPU.
728 * Handle an hrtimer event by push the hrtimer forward a period.
730 * Returns: The hrtimer_restart value to return to the hrtimer subsystem.
732 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu)
734 /* Add the Count period to the current expiry time */
735 hrtimer_add_expires_ns(&vcpu->arch.comparecount_timer,
736 vcpu->arch.count_period);
737 return HRTIMER_RESTART;
740 enum emulation_result kvm_mips_emul_eret(struct kvm_vcpu *vcpu)
742 struct mips_coproc *cop0 = vcpu->arch.cop0;
743 enum emulation_result er = EMULATE_DONE;
745 if (kvm_read_c0_guest_status(cop0) & ST0_EXL) {
746 kvm_debug("[%#lx] ERET to %#lx\n", vcpu->arch.pc,
747 kvm_read_c0_guest_epc(cop0));
748 kvm_clear_c0_guest_status(cop0, ST0_EXL);
749 vcpu->arch.pc = kvm_read_c0_guest_epc(cop0);
751 } else if (kvm_read_c0_guest_status(cop0) & ST0_ERL) {
752 kvm_clear_c0_guest_status(cop0, ST0_ERL);
753 vcpu->arch.pc = kvm_read_c0_guest_errorepc(cop0);
755 kvm_err("[%#lx] ERET when MIPS_SR_EXL|MIPS_SR_ERL == 0\n",
763 enum emulation_result kvm_mips_emul_wait(struct kvm_vcpu *vcpu)
765 kvm_debug("[%#lx] !!!WAIT!!! (%#lx)\n", vcpu->arch.pc,
766 vcpu->arch.pending_exceptions);
768 ++vcpu->stat.wait_exits;
769 trace_kvm_exit(vcpu, WAIT_EXITS);
770 if (!vcpu->arch.pending_exceptions) {
772 kvm_vcpu_block(vcpu);
775 * We we are runnable, then definitely go off to user space to
776 * check if any I/O interrupts are pending.
778 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
779 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
780 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
788 * XXXKYMA: Linux doesn't seem to use TLBR, return EMULATE_FAIL for now so that
789 * we can catch this, if things ever change
791 enum emulation_result kvm_mips_emul_tlbr(struct kvm_vcpu *vcpu)
793 struct mips_coproc *cop0 = vcpu->arch.cop0;
794 uint32_t pc = vcpu->arch.pc;
796 kvm_err("[%#x] COP0_TLBR [%ld]\n", pc, kvm_read_c0_guest_index(cop0));
800 /* Write Guest TLB Entry @ Index */
801 enum emulation_result kvm_mips_emul_tlbwi(struct kvm_vcpu *vcpu)
803 struct mips_coproc *cop0 = vcpu->arch.cop0;
804 int index = kvm_read_c0_guest_index(cop0);
805 struct kvm_mips_tlb *tlb = NULL;
806 uint32_t pc = vcpu->arch.pc;
808 if (index < 0 || index >= KVM_MIPS_GUEST_TLB_SIZE) {
809 kvm_debug("%s: illegal index: %d\n", __func__, index);
810 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
811 pc, index, kvm_read_c0_guest_entryhi(cop0),
812 kvm_read_c0_guest_entrylo0(cop0),
813 kvm_read_c0_guest_entrylo1(cop0),
814 kvm_read_c0_guest_pagemask(cop0));
815 index = (index & ~0x80000000) % KVM_MIPS_GUEST_TLB_SIZE;
818 tlb = &vcpu->arch.guest_tlb[index];
820 * Probe the shadow host TLB for the entry being overwritten, if one
821 * matches, invalidate it
823 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
825 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
826 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
827 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
828 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
830 kvm_debug("[%#x] COP0_TLBWI [%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx, mask: %#lx)\n",
831 pc, index, kvm_read_c0_guest_entryhi(cop0),
832 kvm_read_c0_guest_entrylo0(cop0),
833 kvm_read_c0_guest_entrylo1(cop0),
834 kvm_read_c0_guest_pagemask(cop0));
839 /* Write Guest TLB Entry @ Random Index */
840 enum emulation_result kvm_mips_emul_tlbwr(struct kvm_vcpu *vcpu)
842 struct mips_coproc *cop0 = vcpu->arch.cop0;
843 struct kvm_mips_tlb *tlb = NULL;
844 uint32_t pc = vcpu->arch.pc;
847 get_random_bytes(&index, sizeof(index));
848 index &= (KVM_MIPS_GUEST_TLB_SIZE - 1);
850 tlb = &vcpu->arch.guest_tlb[index];
853 * Probe the shadow host TLB for the entry being overwritten, if one
854 * matches, invalidate it
856 kvm_mips_host_tlb_inv(vcpu, tlb->tlb_hi);
858 tlb->tlb_mask = kvm_read_c0_guest_pagemask(cop0);
859 tlb->tlb_hi = kvm_read_c0_guest_entryhi(cop0);
860 tlb->tlb_lo0 = kvm_read_c0_guest_entrylo0(cop0);
861 tlb->tlb_lo1 = kvm_read_c0_guest_entrylo1(cop0);
863 kvm_debug("[%#x] COP0_TLBWR[%d] (entryhi: %#lx, entrylo0: %#lx entrylo1: %#lx)\n",
864 pc, index, kvm_read_c0_guest_entryhi(cop0),
865 kvm_read_c0_guest_entrylo0(cop0),
866 kvm_read_c0_guest_entrylo1(cop0));
871 enum emulation_result kvm_mips_emul_tlbp(struct kvm_vcpu *vcpu)
873 struct mips_coproc *cop0 = vcpu->arch.cop0;
874 long entryhi = kvm_read_c0_guest_entryhi(cop0);
875 uint32_t pc = vcpu->arch.pc;
878 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
880 kvm_write_c0_guest_index(cop0, index);
882 kvm_debug("[%#x] COP0_TLBP (entryhi: %#lx), index: %d\n", pc, entryhi,
889 * kvm_mips_config1_wrmask() - Find mask of writable bits in guest Config1
890 * @vcpu: Virtual CPU.
892 * Finds the mask of bits which are writable in the guest's Config1 CP0
893 * register, by userland (currently read-only to the guest).
895 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu)
897 unsigned int mask = 0;
899 /* Permit FPU to be present if FPU is supported */
900 if (kvm_mips_guest_can_have_fpu(&vcpu->arch))
901 mask |= MIPS_CONF1_FP;
907 * kvm_mips_config3_wrmask() - Find mask of writable bits in guest Config3
908 * @vcpu: Virtual CPU.
910 * Finds the mask of bits which are writable in the guest's Config3 CP0
911 * register, by userland (currently read-only to the guest).
913 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu)
915 /* Config4 is optional */
916 unsigned int mask = MIPS_CONF_M;
918 /* Permit MSA to be present if MSA is supported */
919 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
920 mask |= MIPS_CONF3_MSA;
926 * kvm_mips_config4_wrmask() - Find mask of writable bits in guest Config4
927 * @vcpu: Virtual CPU.
929 * Finds the mask of bits which are writable in the guest's Config4 CP0
930 * register, by userland (currently read-only to the guest).
932 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu)
934 /* Config5 is optional */
939 * kvm_mips_config5_wrmask() - Find mask of writable bits in guest Config5
940 * @vcpu: Virtual CPU.
942 * Finds the mask of bits which are writable in the guest's Config5 CP0
943 * register, by the guest itself.
945 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu)
947 unsigned int mask = 0;
949 /* Permit MSAEn changes if MSA supported and enabled */
950 if (kvm_mips_guest_has_msa(&vcpu->arch))
951 mask |= MIPS_CONF5_MSAEN;
954 * Permit guest FPU mode changes if FPU is enabled and the relevant
955 * feature exists according to FIR register.
957 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
959 mask |= MIPS_CONF5_FRE;
960 /* We don't support UFR or UFE */
966 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,
967 uint32_t cause, struct kvm_run *run,
968 struct kvm_vcpu *vcpu)
970 struct mips_coproc *cop0 = vcpu->arch.cop0;
971 enum emulation_result er = EMULATE_DONE;
972 int32_t rt, rd, copz, sel, co_bit, op;
973 uint32_t pc = vcpu->arch.pc;
974 unsigned long curr_pc;
977 * Update PC and hold onto current PC in case there is
978 * an error and we want to rollback the PC
980 curr_pc = vcpu->arch.pc;
981 er = update_pc(vcpu, cause);
982 if (er == EMULATE_FAIL)
985 copz = (inst >> 21) & 0x1f;
986 rt = (inst >> 16) & 0x1f;
987 rd = (inst >> 11) & 0x1f;
989 co_bit = (inst >> 25) & 1;
995 case tlbr_op: /* Read indexed TLB entry */
996 er = kvm_mips_emul_tlbr(vcpu);
998 case tlbwi_op: /* Write indexed */
999 er = kvm_mips_emul_tlbwi(vcpu);
1001 case tlbwr_op: /* Write random */
1002 er = kvm_mips_emul_tlbwr(vcpu);
1004 case tlbp_op: /* TLB Probe */
1005 er = kvm_mips_emul_tlbp(vcpu);
1008 kvm_err("!!!COP0_RFE!!!\n");
1011 er = kvm_mips_emul_eret(vcpu);
1012 goto dont_update_pc;
1015 er = kvm_mips_emul_wait(vcpu);
1021 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1022 cop0->stat[rd][sel]++;
1025 if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1026 vcpu->arch.gprs[rt] = kvm_mips_read_count(vcpu);
1027 } else if ((rd == MIPS_CP0_ERRCTL) && (sel == 0)) {
1028 vcpu->arch.gprs[rt] = 0x0;
1029 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1030 kvm_mips_trans_mfc0(inst, opc, vcpu);
1033 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1035 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1036 kvm_mips_trans_mfc0(inst, opc, vcpu);
1041 ("[%#x] MFCz[%d][%d], vcpu->arch.gprs[%d]: %#lx\n",
1042 pc, rd, sel, rt, vcpu->arch.gprs[rt]);
1047 vcpu->arch.gprs[rt] = cop0->reg[rd][sel];
1051 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
1052 cop0->stat[rd][sel]++;
1054 if ((rd == MIPS_CP0_TLB_INDEX)
1055 && (vcpu->arch.gprs[rt] >=
1056 KVM_MIPS_GUEST_TLB_SIZE)) {
1057 kvm_err("Invalid TLB Index: %ld",
1058 vcpu->arch.gprs[rt]);
1062 #define C0_EBASE_CORE_MASK 0xff
1063 if ((rd == MIPS_CP0_PRID) && (sel == 1)) {
1064 /* Preserve CORE number */
1065 kvm_change_c0_guest_ebase(cop0,
1066 ~(C0_EBASE_CORE_MASK),
1067 vcpu->arch.gprs[rt]);
1068 kvm_err("MTCz, cop0->reg[EBASE]: %#lx\n",
1069 kvm_read_c0_guest_ebase(cop0));
1070 } else if (rd == MIPS_CP0_TLB_HI && sel == 0) {
1072 vcpu->arch.gprs[rt] & ASID_MASK;
1073 if ((KSEGX(vcpu->arch.gprs[rt]) != CKSEG0) &&
1074 ((kvm_read_c0_guest_entryhi(cop0) &
1075 ASID_MASK) != nasid)) {
1076 kvm_debug("MTCz, change ASID from %#lx to %#lx\n",
1077 kvm_read_c0_guest_entryhi(cop0)
1082 /* Blow away the shadow host TLBs */
1083 kvm_mips_flush_host_tlb(1);
1085 kvm_write_c0_guest_entryhi(cop0,
1086 vcpu->arch.gprs[rt]);
1088 /* Are we writing to COUNT */
1089 else if ((rd == MIPS_CP0_COUNT) && (sel == 0)) {
1090 kvm_mips_write_count(vcpu, vcpu->arch.gprs[rt]);
1092 } else if ((rd == MIPS_CP0_COMPARE) && (sel == 0)) {
1093 kvm_debug("[%#x] MTCz, COMPARE %#lx <- %#lx\n",
1094 pc, kvm_read_c0_guest_compare(cop0),
1095 vcpu->arch.gprs[rt]);
1097 /* If we are writing to COMPARE */
1098 /* Clear pending timer interrupt, if any */
1099 kvm_mips_callbacks->dequeue_timer_int(vcpu);
1100 kvm_mips_write_compare(vcpu,
1101 vcpu->arch.gprs[rt]);
1102 } else if ((rd == MIPS_CP0_STATUS) && (sel == 0)) {
1103 unsigned int old_val, val, change;
1105 old_val = kvm_read_c0_guest_status(cop0);
1106 val = vcpu->arch.gprs[rt];
1107 change = val ^ old_val;
1109 /* Make sure that the NMI bit is never set */
1113 * Don't allow CU1 or FR to be set unless FPU
1114 * capability enabled and exists in guest
1117 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1118 val &= ~(ST0_CU1 | ST0_FR);
1121 * Also don't allow FR to be set if host doesn't
1124 if (!(current_cpu_data.fpu_id & MIPS_FPIR_F64))
1128 /* Handle changes in FPU mode */
1132 * FPU and Vector register state is made
1133 * UNPREDICTABLE by a change of FR, so don't
1134 * even bother saving it.
1136 if (change & ST0_FR)
1140 * If MSA state is already live, it is undefined
1141 * how it interacts with FR=0 FPU state, and we
1142 * don't want to hit reserved instruction
1143 * exceptions trying to save the MSA state later
1144 * when CU=1 && FR=1, so play it safe and save
1147 if (change & ST0_CU1 && !(val & ST0_FR) &&
1148 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1152 * Propagate CU1 (FPU enable) changes
1153 * immediately if the FPU context is already
1154 * loaded. When disabling we leave the context
1155 * loaded so it can be quickly enabled again in
1158 if (change & ST0_CU1 &&
1159 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1160 change_c0_status(ST0_CU1, val);
1164 kvm_write_c0_guest_status(cop0, val);
1166 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1168 * If FPU present, we need CU1/FR bits to take
1169 * effect fairly soon.
1171 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
1172 kvm_mips_trans_mtc0(inst, opc, vcpu);
1174 } else if ((rd == MIPS_CP0_CONFIG) && (sel == 5)) {
1175 unsigned int old_val, val, change, wrmask;
1177 old_val = kvm_read_c0_guest_config5(cop0);
1178 val = vcpu->arch.gprs[rt];
1180 /* Only a few bits are writable in Config5 */
1181 wrmask = kvm_mips_config5_wrmask(vcpu);
1182 change = (val ^ old_val) & wrmask;
1183 val = old_val ^ change;
1186 /* Handle changes in FPU/MSA modes */
1190 * Propagate FRE changes immediately if the FPU
1191 * context is already loaded.
1193 if (change & MIPS_CONF5_FRE &&
1194 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1195 change_c0_config5(MIPS_CONF5_FRE, val);
1198 * Propagate MSAEn changes immediately if the
1199 * MSA context is already loaded. When disabling
1200 * we leave the context loaded so it can be
1201 * quickly enabled again in the near future.
1203 if (change & MIPS_CONF5_MSAEN &&
1204 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1205 change_c0_config5(MIPS_CONF5_MSAEN,
1210 kvm_write_c0_guest_config5(cop0, val);
1211 } else if ((rd == MIPS_CP0_CAUSE) && (sel == 0)) {
1212 uint32_t old_cause, new_cause;
1214 old_cause = kvm_read_c0_guest_cause(cop0);
1215 new_cause = vcpu->arch.gprs[rt];
1216 /* Update R/W bits */
1217 kvm_change_c0_guest_cause(cop0, 0x08800300,
1219 /* DC bit enabling/disabling timer? */
1220 if ((old_cause ^ new_cause) & CAUSEF_DC) {
1221 if (new_cause & CAUSEF_DC)
1222 kvm_mips_count_disable_cause(vcpu);
1224 kvm_mips_count_enable_cause(vcpu);
1227 cop0->reg[rd][sel] = vcpu->arch.gprs[rt];
1228 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1229 kvm_mips_trans_mtc0(inst, opc, vcpu);
1233 kvm_debug("[%#x] MTCz, cop0->reg[%d][%d]: %#lx\n", pc,
1234 rd, sel, cop0->reg[rd][sel]);
1238 kvm_err("!!!!!!![%#lx]dmtc_op: rt: %d, rd: %d, sel: %d!!!!!!\n",
1239 vcpu->arch.pc, rt, rd, sel);
1244 #ifdef KVM_MIPS_DEBUG_COP0_COUNTERS
1245 cop0->stat[MIPS_CP0_STATUS][0]++;
1248 vcpu->arch.gprs[rt] =
1249 kvm_read_c0_guest_status(cop0);
1252 kvm_debug("[%#lx] mfmcz_op: EI\n",
1254 kvm_set_c0_guest_status(cop0, ST0_IE);
1256 kvm_debug("[%#lx] mfmcz_op: DI\n",
1258 kvm_clear_c0_guest_status(cop0, ST0_IE);
1266 cop0->reg[MIPS_CP0_STATUS][2] & 0xf;
1268 (cop0->reg[MIPS_CP0_STATUS][2] >> 6) & 0xf;
1270 * We don't support any shadow register sets, so
1271 * SRSCtl[PSS] == SRSCtl[CSS] = 0
1277 kvm_debug("WRPGPR[%d][%d] = %#lx\n", pss, rd,
1278 vcpu->arch.gprs[rt]);
1279 vcpu->arch.gprs[rd] = vcpu->arch.gprs[rt];
1283 kvm_err("[%#lx]MachEmulateCP0: unsupported COP0, copz: 0x%x\n",
1284 vcpu->arch.pc, copz);
1291 /* Rollback PC only if emulation was unsuccessful */
1292 if (er == EMULATE_FAIL)
1293 vcpu->arch.pc = curr_pc;
1297 * This is for special instructions whose emulation
1298 * updates the PC, so do not overwrite the PC under
1305 enum emulation_result kvm_mips_emulate_store(uint32_t inst, uint32_t cause,
1306 struct kvm_run *run,
1307 struct kvm_vcpu *vcpu)
1309 enum emulation_result er = EMULATE_DO_MMIO;
1310 int32_t op, base, rt, offset;
1312 void *data = run->mmio.data;
1313 unsigned long curr_pc;
1316 * Update PC and hold onto current PC in case there is
1317 * an error and we want to rollback the PC
1319 curr_pc = vcpu->arch.pc;
1320 er = update_pc(vcpu, cause);
1321 if (er == EMULATE_FAIL)
1324 rt = (inst >> 16) & 0x1f;
1325 base = (inst >> 21) & 0x1f;
1326 offset = inst & 0xffff;
1327 op = (inst >> 26) & 0x3f;
1332 if (bytes > sizeof(run->mmio.data)) {
1333 kvm_err("%s: bad MMIO length: %d\n", __func__,
1336 run->mmio.phys_addr =
1337 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1339 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1343 run->mmio.len = bytes;
1344 run->mmio.is_write = 1;
1345 vcpu->mmio_needed = 1;
1346 vcpu->mmio_is_write = 1;
1347 *(u8 *) data = vcpu->arch.gprs[rt];
1348 kvm_debug("OP_SB: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1349 vcpu->arch.host_cp0_badvaddr, vcpu->arch.gprs[rt],
1356 if (bytes > sizeof(run->mmio.data)) {
1357 kvm_err("%s: bad MMIO length: %d\n", __func__,
1360 run->mmio.phys_addr =
1361 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1363 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1368 run->mmio.len = bytes;
1369 run->mmio.is_write = 1;
1370 vcpu->mmio_needed = 1;
1371 vcpu->mmio_is_write = 1;
1372 *(uint32_t *) data = vcpu->arch.gprs[rt];
1374 kvm_debug("[%#lx] OP_SW: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1375 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1376 vcpu->arch.gprs[rt], *(uint32_t *) data);
1381 if (bytes > sizeof(run->mmio.data)) {
1382 kvm_err("%s: bad MMIO length: %d\n", __func__,
1385 run->mmio.phys_addr =
1386 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1388 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1393 run->mmio.len = bytes;
1394 run->mmio.is_write = 1;
1395 vcpu->mmio_needed = 1;
1396 vcpu->mmio_is_write = 1;
1397 *(uint16_t *) data = vcpu->arch.gprs[rt];
1399 kvm_debug("[%#lx] OP_SH: eaddr: %#lx, gpr: %#lx, data: %#x\n",
1400 vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr,
1401 vcpu->arch.gprs[rt], *(uint32_t *) data);
1405 kvm_err("Store not yet supported");
1410 /* Rollback PC if emulation was unsuccessful */
1411 if (er == EMULATE_FAIL)
1412 vcpu->arch.pc = curr_pc;
1417 enum emulation_result kvm_mips_emulate_load(uint32_t inst, uint32_t cause,
1418 struct kvm_run *run,
1419 struct kvm_vcpu *vcpu)
1421 enum emulation_result er = EMULATE_DO_MMIO;
1422 int32_t op, base, rt, offset;
1425 rt = (inst >> 16) & 0x1f;
1426 base = (inst >> 21) & 0x1f;
1427 offset = inst & 0xffff;
1428 op = (inst >> 26) & 0x3f;
1430 vcpu->arch.pending_load_cause = cause;
1431 vcpu->arch.io_gpr = rt;
1436 if (bytes > sizeof(run->mmio.data)) {
1437 kvm_err("%s: bad MMIO length: %d\n", __func__,
1442 run->mmio.phys_addr =
1443 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1445 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1450 run->mmio.len = bytes;
1451 run->mmio.is_write = 0;
1452 vcpu->mmio_needed = 1;
1453 vcpu->mmio_is_write = 0;
1459 if (bytes > sizeof(run->mmio.data)) {
1460 kvm_err("%s: bad MMIO length: %d\n", __func__,
1465 run->mmio.phys_addr =
1466 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1468 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1473 run->mmio.len = bytes;
1474 run->mmio.is_write = 0;
1475 vcpu->mmio_needed = 1;
1476 vcpu->mmio_is_write = 0;
1479 vcpu->mmio_needed = 2;
1481 vcpu->mmio_needed = 1;
1488 if (bytes > sizeof(run->mmio.data)) {
1489 kvm_err("%s: bad MMIO length: %d\n", __func__,
1494 run->mmio.phys_addr =
1495 kvm_mips_callbacks->gva_to_gpa(vcpu->arch.
1497 if (run->mmio.phys_addr == KVM_INVALID_ADDR) {
1502 run->mmio.len = bytes;
1503 run->mmio.is_write = 0;
1504 vcpu->mmio_is_write = 0;
1507 vcpu->mmio_needed = 2;
1509 vcpu->mmio_needed = 1;
1514 kvm_err("Load not yet supported");
1522 int kvm_mips_sync_icache(unsigned long va, struct kvm_vcpu *vcpu)
1524 unsigned long offset = (va & ~PAGE_MASK);
1525 struct kvm *kvm = vcpu->kvm;
1530 gfn = va >> PAGE_SHIFT;
1532 if (gfn >= kvm->arch.guest_pmap_npages) {
1533 kvm_err("%s: Invalid gfn: %#llx\n", __func__, gfn);
1534 kvm_mips_dump_host_tlbs();
1535 kvm_arch_vcpu_dump_regs(vcpu);
1538 pfn = kvm->arch.guest_pmap[gfn];
1539 pa = (pfn << PAGE_SHIFT) | offset;
1541 kvm_debug("%s: va: %#lx, unmapped: %#x\n", __func__, va,
1544 local_flush_icache_range(CKSEG0ADDR(pa), 32);
1548 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,
1550 struct kvm_run *run,
1551 struct kvm_vcpu *vcpu)
1553 struct mips_coproc *cop0 = vcpu->arch.cop0;
1554 enum emulation_result er = EMULATE_DONE;
1555 int32_t offset, cache, op_inst, op, base;
1556 struct kvm_vcpu_arch *arch = &vcpu->arch;
1558 unsigned long curr_pc;
1561 * Update PC and hold onto current PC in case there is
1562 * an error and we want to rollback the PC
1564 curr_pc = vcpu->arch.pc;
1565 er = update_pc(vcpu, cause);
1566 if (er == EMULATE_FAIL)
1569 base = (inst >> 21) & 0x1f;
1570 op_inst = (inst >> 16) & 0x1f;
1571 offset = (int16_t)inst;
1572 cache = op_inst & CacheOp_Cache;
1573 op = op_inst & CacheOp_Op;
1575 va = arch->gprs[base] + offset;
1577 kvm_debug("CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1578 cache, op, base, arch->gprs[base], offset);
1581 * Treat INDEX_INV as a nop, basically issued by Linux on startup to
1582 * invalidate the caches entirely by stepping through all the
1585 if (op == Index_Writeback_Inv) {
1586 kvm_debug("@ %#lx/%#lx CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1587 vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
1588 arch->gprs[base], offset);
1590 if (cache == Cache_D)
1592 else if (cache == Cache_I)
1595 kvm_err("%s: unsupported CACHE INDEX operation\n",
1597 return EMULATE_FAIL;
1600 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1601 kvm_mips_trans_cache_index(inst, opc, vcpu);
1607 if (KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG0) {
1608 if (kvm_mips_host_tlb_lookup(vcpu, va) < 0)
1609 kvm_mips_handle_kseg0_tlb_fault(va, vcpu);
1610 } else if ((KVM_GUEST_KSEGX(va) < KVM_GUEST_KSEG0) ||
1611 KVM_GUEST_KSEGX(va) == KVM_GUEST_KSEG23) {
1614 /* If an entry already exists then skip */
1615 if (kvm_mips_host_tlb_lookup(vcpu, va) >= 0)
1619 * If address not in the guest TLB, then give the guest a fault,
1620 * the resulting handler will do the right thing
1622 index = kvm_mips_guest_tlb_lookup(vcpu, (va & VPN2_MASK) |
1623 (kvm_read_c0_guest_entryhi
1624 (cop0) & ASID_MASK));
1627 vcpu->arch.host_cp0_entryhi = (va & VPN2_MASK);
1628 vcpu->arch.host_cp0_badvaddr = va;
1629 er = kvm_mips_emulate_tlbmiss_ld(cause, NULL, run,
1632 goto dont_update_pc;
1634 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
1636 * Check if the entry is valid, if not then setup a TLB
1637 * invalid exception to the guest
1639 if (!TLB_IS_VALID(*tlb, va)) {
1640 er = kvm_mips_emulate_tlbinv_ld(cause, NULL,
1643 goto dont_update_pc;
1646 * We fault an entry from the guest tlb to the
1649 kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb,
1655 kvm_err("INVALID CACHE INDEX/ADDRESS (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1656 cache, op, base, arch->gprs[base], offset);
1659 goto dont_update_pc;
1664 /* XXXKYMA: Only a subset of cache ops are supported, used by Linux */
1665 if (op_inst == Hit_Writeback_Inv_D || op_inst == Hit_Invalidate_D) {
1666 flush_dcache_line(va);
1668 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1670 * Replace the CACHE instruction, with a SYNCI, not the same,
1673 kvm_mips_trans_cache_va(inst, opc, vcpu);
1675 } else if (op_inst == Hit_Invalidate_I) {
1676 flush_dcache_line(va);
1677 flush_icache_line(va);
1679 #ifdef CONFIG_KVM_MIPS_DYN_TRANS
1680 /* Replace the CACHE instruction, with a SYNCI */
1681 kvm_mips_trans_cache_va(inst, opc, vcpu);
1684 kvm_err("NO-OP CACHE (cache: %#x, op: %#x, base[%d]: %#lx, offset: %#x\n",
1685 cache, op, base, arch->gprs[base], offset);
1688 goto dont_update_pc;
1695 vcpu->arch.pc = curr_pc;
1700 enum emulation_result kvm_mips_emulate_inst(unsigned long cause, uint32_t *opc,
1701 struct kvm_run *run,
1702 struct kvm_vcpu *vcpu)
1704 enum emulation_result er = EMULATE_DONE;
1707 /* Fetch the instruction. */
1708 if (cause & CAUSEF_BD)
1711 inst = kvm_get_inst(opc, vcpu);
1713 switch (((union mips_instruction)inst).r_format.opcode) {
1715 er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);
1720 er = kvm_mips_emulate_store(inst, cause, run, vcpu);
1727 er = kvm_mips_emulate_load(inst, cause, run, vcpu);
1731 ++vcpu->stat.cache_exits;
1732 trace_kvm_exit(vcpu, CACHE_EXITS);
1733 er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);
1737 kvm_err("Instruction emulation not supported (%p/%#x)\n", opc,
1739 kvm_arch_vcpu_dump_regs(vcpu);
1747 enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
1749 struct kvm_run *run,
1750 struct kvm_vcpu *vcpu)
1752 struct mips_coproc *cop0 = vcpu->arch.cop0;
1753 struct kvm_vcpu_arch *arch = &vcpu->arch;
1754 enum emulation_result er = EMULATE_DONE;
1756 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1758 kvm_write_c0_guest_epc(cop0, arch->pc);
1759 kvm_set_c0_guest_status(cop0, ST0_EXL);
1761 if (cause & CAUSEF_BD)
1762 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1764 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1766 kvm_debug("Delivering SYSCALL @ pc %#lx\n", arch->pc);
1768 kvm_change_c0_guest_cause(cop0, (0xff),
1769 (EXCCODE_SYS << CAUSEB_EXCCODE));
1771 /* Set PC to the exception entry point */
1772 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1775 kvm_err("Trying to deliver SYSCALL when EXL is already set\n");
1782 enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
1784 struct kvm_run *run,
1785 struct kvm_vcpu *vcpu)
1787 struct mips_coproc *cop0 = vcpu->arch.cop0;
1788 struct kvm_vcpu_arch *arch = &vcpu->arch;
1789 unsigned long entryhi = (vcpu->arch. host_cp0_badvaddr & VPN2_MASK) |
1790 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1792 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1794 kvm_write_c0_guest_epc(cop0, arch->pc);
1795 kvm_set_c0_guest_status(cop0, ST0_EXL);
1797 if (cause & CAUSEF_BD)
1798 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1800 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1802 kvm_debug("[EXL == 0] delivering TLB MISS @ pc %#lx\n",
1805 /* set pc to the exception entry point */
1806 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1809 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1812 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1815 kvm_change_c0_guest_cause(cop0, (0xff),
1816 (EXCCODE_TLBL << CAUSEB_EXCCODE));
1818 /* setup badvaddr, context and entryhi registers for the guest */
1819 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1820 /* XXXKYMA: is the context register used by linux??? */
1821 kvm_write_c0_guest_entryhi(cop0, entryhi);
1822 /* Blow away the shadow host TLBs */
1823 kvm_mips_flush_host_tlb(1);
1825 return EMULATE_DONE;
1828 enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
1830 struct kvm_run *run,
1831 struct kvm_vcpu *vcpu)
1833 struct mips_coproc *cop0 = vcpu->arch.cop0;
1834 struct kvm_vcpu_arch *arch = &vcpu->arch;
1835 unsigned long entryhi =
1836 (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1837 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1839 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1841 kvm_write_c0_guest_epc(cop0, arch->pc);
1842 kvm_set_c0_guest_status(cop0, ST0_EXL);
1844 if (cause & CAUSEF_BD)
1845 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1847 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1849 kvm_debug("[EXL == 0] delivering TLB INV @ pc %#lx\n",
1852 /* set pc to the exception entry point */
1853 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1856 kvm_debug("[EXL == 1] delivering TLB MISS @ pc %#lx\n",
1858 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1861 kvm_change_c0_guest_cause(cop0, (0xff),
1862 (EXCCODE_TLBL << CAUSEB_EXCCODE));
1864 /* setup badvaddr, context and entryhi registers for the guest */
1865 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1866 /* XXXKYMA: is the context register used by linux??? */
1867 kvm_write_c0_guest_entryhi(cop0, entryhi);
1868 /* Blow away the shadow host TLBs */
1869 kvm_mips_flush_host_tlb(1);
1871 return EMULATE_DONE;
1874 enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
1876 struct kvm_run *run,
1877 struct kvm_vcpu *vcpu)
1879 struct mips_coproc *cop0 = vcpu->arch.cop0;
1880 struct kvm_vcpu_arch *arch = &vcpu->arch;
1881 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1882 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1884 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1886 kvm_write_c0_guest_epc(cop0, arch->pc);
1887 kvm_set_c0_guest_status(cop0, ST0_EXL);
1889 if (cause & CAUSEF_BD)
1890 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1892 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1894 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1897 /* Set PC to the exception entry point */
1898 arch->pc = KVM_GUEST_KSEG0 + 0x0;
1900 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1902 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1905 kvm_change_c0_guest_cause(cop0, (0xff),
1906 (EXCCODE_TLBS << CAUSEB_EXCCODE));
1908 /* setup badvaddr, context and entryhi registers for the guest */
1909 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1910 /* XXXKYMA: is the context register used by linux??? */
1911 kvm_write_c0_guest_entryhi(cop0, entryhi);
1912 /* Blow away the shadow host TLBs */
1913 kvm_mips_flush_host_tlb(1);
1915 return EMULATE_DONE;
1918 enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
1920 struct kvm_run *run,
1921 struct kvm_vcpu *vcpu)
1923 struct mips_coproc *cop0 = vcpu->arch.cop0;
1924 struct kvm_vcpu_arch *arch = &vcpu->arch;
1925 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1926 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1928 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
1930 kvm_write_c0_guest_epc(cop0, arch->pc);
1931 kvm_set_c0_guest_status(cop0, ST0_EXL);
1933 if (cause & CAUSEF_BD)
1934 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
1936 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
1938 kvm_debug("[EXL == 0] Delivering TLB MISS @ pc %#lx\n",
1941 /* Set PC to the exception entry point */
1942 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1944 kvm_debug("[EXL == 1] Delivering TLB MISS @ pc %#lx\n",
1946 arch->pc = KVM_GUEST_KSEG0 + 0x180;
1949 kvm_change_c0_guest_cause(cop0, (0xff),
1950 (EXCCODE_TLBS << CAUSEB_EXCCODE));
1952 /* setup badvaddr, context and entryhi registers for the guest */
1953 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
1954 /* XXXKYMA: is the context register used by linux??? */
1955 kvm_write_c0_guest_entryhi(cop0, entryhi);
1956 /* Blow away the shadow host TLBs */
1957 kvm_mips_flush_host_tlb(1);
1959 return EMULATE_DONE;
1962 /* TLBMOD: store into address matching TLB with Dirty bit off */
1963 enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause, uint32_t *opc,
1964 struct kvm_run *run,
1965 struct kvm_vcpu *vcpu)
1967 enum emulation_result er = EMULATE_DONE;
1969 struct mips_coproc *cop0 = vcpu->arch.cop0;
1970 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1971 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1974 /* If address not in the guest TLB, then we are in trouble */
1975 index = kvm_mips_guest_tlb_lookup(vcpu, entryhi);
1977 /* XXXKYMA Invalidate and retry */
1978 kvm_mips_host_tlb_inv(vcpu, vcpu->arch.host_cp0_badvaddr);
1979 kvm_err("%s: host got TLBMOD for %#lx but entry not present in Guest TLB\n",
1981 kvm_mips_dump_guest_tlbs(vcpu);
1982 kvm_mips_dump_host_tlbs();
1983 return EMULATE_FAIL;
1987 er = kvm_mips_emulate_tlbmod(cause, opc, run, vcpu);
1991 enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
1993 struct kvm_run *run,
1994 struct kvm_vcpu *vcpu)
1996 struct mips_coproc *cop0 = vcpu->arch.cop0;
1997 unsigned long entryhi = (vcpu->arch.host_cp0_badvaddr & VPN2_MASK) |
1998 (kvm_read_c0_guest_entryhi(cop0) & ASID_MASK);
1999 struct kvm_vcpu_arch *arch = &vcpu->arch;
2001 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2003 kvm_write_c0_guest_epc(cop0, arch->pc);
2004 kvm_set_c0_guest_status(cop0, ST0_EXL);
2006 if (cause & CAUSEF_BD)
2007 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2009 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2011 kvm_debug("[EXL == 0] Delivering TLB MOD @ pc %#lx\n",
2014 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2016 kvm_debug("[EXL == 1] Delivering TLB MOD @ pc %#lx\n",
2018 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2021 kvm_change_c0_guest_cause(cop0, (0xff),
2022 (EXCCODE_MOD << CAUSEB_EXCCODE));
2024 /* setup badvaddr, context and entryhi registers for the guest */
2025 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2026 /* XXXKYMA: is the context register used by linux??? */
2027 kvm_write_c0_guest_entryhi(cop0, entryhi);
2028 /* Blow away the shadow host TLBs */
2029 kvm_mips_flush_host_tlb(1);
2031 return EMULATE_DONE;
2034 enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
2036 struct kvm_run *run,
2037 struct kvm_vcpu *vcpu)
2039 struct mips_coproc *cop0 = vcpu->arch.cop0;
2040 struct kvm_vcpu_arch *arch = &vcpu->arch;
2042 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2044 kvm_write_c0_guest_epc(cop0, arch->pc);
2045 kvm_set_c0_guest_status(cop0, ST0_EXL);
2047 if (cause & CAUSEF_BD)
2048 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2050 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2054 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2056 kvm_change_c0_guest_cause(cop0, (0xff),
2057 (EXCCODE_CPU << CAUSEB_EXCCODE));
2058 kvm_change_c0_guest_cause(cop0, (CAUSEF_CE), (0x1 << CAUSEB_CE));
2060 return EMULATE_DONE;
2063 enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
2065 struct kvm_run *run,
2066 struct kvm_vcpu *vcpu)
2068 struct mips_coproc *cop0 = vcpu->arch.cop0;
2069 struct kvm_vcpu_arch *arch = &vcpu->arch;
2070 enum emulation_result er = EMULATE_DONE;
2072 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2074 kvm_write_c0_guest_epc(cop0, arch->pc);
2075 kvm_set_c0_guest_status(cop0, ST0_EXL);
2077 if (cause & CAUSEF_BD)
2078 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2080 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2082 kvm_debug("Delivering RI @ pc %#lx\n", arch->pc);
2084 kvm_change_c0_guest_cause(cop0, (0xff),
2085 (EXCCODE_RI << CAUSEB_EXCCODE));
2087 /* Set PC to the exception entry point */
2088 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2091 kvm_err("Trying to deliver RI when EXL is already set\n");
2098 enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
2100 struct kvm_run *run,
2101 struct kvm_vcpu *vcpu)
2103 struct mips_coproc *cop0 = vcpu->arch.cop0;
2104 struct kvm_vcpu_arch *arch = &vcpu->arch;
2105 enum emulation_result er = EMULATE_DONE;
2107 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2109 kvm_write_c0_guest_epc(cop0, arch->pc);
2110 kvm_set_c0_guest_status(cop0, ST0_EXL);
2112 if (cause & CAUSEF_BD)
2113 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2115 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2117 kvm_debug("Delivering BP @ pc %#lx\n", arch->pc);
2119 kvm_change_c0_guest_cause(cop0, (0xff),
2120 (EXCCODE_BP << CAUSEB_EXCCODE));
2122 /* Set PC to the exception entry point */
2123 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2126 kvm_err("Trying to deliver BP when EXL is already set\n");
2133 enum emulation_result kvm_mips_emulate_trap_exc(unsigned long cause,
2135 struct kvm_run *run,
2136 struct kvm_vcpu *vcpu)
2138 struct mips_coproc *cop0 = vcpu->arch.cop0;
2139 struct kvm_vcpu_arch *arch = &vcpu->arch;
2140 enum emulation_result er = EMULATE_DONE;
2142 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2144 kvm_write_c0_guest_epc(cop0, arch->pc);
2145 kvm_set_c0_guest_status(cop0, ST0_EXL);
2147 if (cause & CAUSEF_BD)
2148 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2150 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2152 kvm_debug("Delivering TRAP @ pc %#lx\n", arch->pc);
2154 kvm_change_c0_guest_cause(cop0, (0xff),
2155 (EXCCODE_TR << CAUSEB_EXCCODE));
2157 /* Set PC to the exception entry point */
2158 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2161 kvm_err("Trying to deliver TRAP when EXL is already set\n");
2168 enum emulation_result kvm_mips_emulate_msafpe_exc(unsigned long cause,
2170 struct kvm_run *run,
2171 struct kvm_vcpu *vcpu)
2173 struct mips_coproc *cop0 = vcpu->arch.cop0;
2174 struct kvm_vcpu_arch *arch = &vcpu->arch;
2175 enum emulation_result er = EMULATE_DONE;
2177 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2179 kvm_write_c0_guest_epc(cop0, arch->pc);
2180 kvm_set_c0_guest_status(cop0, ST0_EXL);
2182 if (cause & CAUSEF_BD)
2183 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2185 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2187 kvm_debug("Delivering MSAFPE @ pc %#lx\n", arch->pc);
2189 kvm_change_c0_guest_cause(cop0, (0xff),
2190 (EXCCODE_MSAFPE << CAUSEB_EXCCODE));
2192 /* Set PC to the exception entry point */
2193 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2196 kvm_err("Trying to deliver MSAFPE when EXL is already set\n");
2203 enum emulation_result kvm_mips_emulate_fpe_exc(unsigned long cause,
2205 struct kvm_run *run,
2206 struct kvm_vcpu *vcpu)
2208 struct mips_coproc *cop0 = vcpu->arch.cop0;
2209 struct kvm_vcpu_arch *arch = &vcpu->arch;
2210 enum emulation_result er = EMULATE_DONE;
2212 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2214 kvm_write_c0_guest_epc(cop0, arch->pc);
2215 kvm_set_c0_guest_status(cop0, ST0_EXL);
2217 if (cause & CAUSEF_BD)
2218 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2220 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2222 kvm_debug("Delivering FPE @ pc %#lx\n", arch->pc);
2224 kvm_change_c0_guest_cause(cop0, (0xff),
2225 (EXCCODE_FPE << CAUSEB_EXCCODE));
2227 /* Set PC to the exception entry point */
2228 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2231 kvm_err("Trying to deliver FPE when EXL is already set\n");
2238 enum emulation_result kvm_mips_emulate_msadis_exc(unsigned long cause,
2240 struct kvm_run *run,
2241 struct kvm_vcpu *vcpu)
2243 struct mips_coproc *cop0 = vcpu->arch.cop0;
2244 struct kvm_vcpu_arch *arch = &vcpu->arch;
2245 enum emulation_result er = EMULATE_DONE;
2247 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2249 kvm_write_c0_guest_epc(cop0, arch->pc);
2250 kvm_set_c0_guest_status(cop0, ST0_EXL);
2252 if (cause & CAUSEF_BD)
2253 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2255 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2257 kvm_debug("Delivering MSADIS @ pc %#lx\n", arch->pc);
2259 kvm_change_c0_guest_cause(cop0, (0xff),
2260 (EXCCODE_MSADIS << CAUSEB_EXCCODE));
2262 /* Set PC to the exception entry point */
2263 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2266 kvm_err("Trying to deliver MSADIS when EXL is already set\n");
2273 /* ll/sc, rdhwr, sync emulation */
2275 #define OPCODE 0xfc000000
2276 #define BASE 0x03e00000
2277 #define RT 0x001f0000
2278 #define OFFSET 0x0000ffff
2279 #define LL 0xc0000000
2280 #define SC 0xe0000000
2281 #define SPEC0 0x00000000
2282 #define SPEC3 0x7c000000
2283 #define RD 0x0000f800
2284 #define FUNC 0x0000003f
2285 #define SYNC 0x0000000f
2286 #define RDHWR 0x0000003b
2288 enum emulation_result kvm_mips_handle_ri(unsigned long cause, uint32_t *opc,
2289 struct kvm_run *run,
2290 struct kvm_vcpu *vcpu)
2292 struct mips_coproc *cop0 = vcpu->arch.cop0;
2293 struct kvm_vcpu_arch *arch = &vcpu->arch;
2294 enum emulation_result er = EMULATE_DONE;
2295 unsigned long curr_pc;
2299 * Update PC and hold onto current PC in case there is
2300 * an error and we want to rollback the PC
2302 curr_pc = vcpu->arch.pc;
2303 er = update_pc(vcpu, cause);
2304 if (er == EMULATE_FAIL)
2307 /* Fetch the instruction. */
2308 if (cause & CAUSEF_BD)
2311 inst = kvm_get_inst(opc, vcpu);
2313 if (inst == KVM_INVALID_INST) {
2314 kvm_err("%s: Cannot get inst @ %p\n", __func__, opc);
2315 return EMULATE_FAIL;
2318 if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {
2319 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2320 int rd = (inst & RD) >> 11;
2321 int rt = (inst & RT) >> 16;
2322 /* If usermode, check RDHWR rd is allowed by guest HWREna */
2323 if (usermode && !(kvm_read_c0_guest_hwrena(cop0) & BIT(rd))) {
2324 kvm_debug("RDHWR %#x disallowed by HWREna @ %p\n",
2329 case 0: /* CPU number */
2332 case 1: /* SYNCI length */
2333 arch->gprs[rt] = min(current_cpu_data.dcache.linesz,
2334 current_cpu_data.icache.linesz);
2336 case 2: /* Read count register */
2337 arch->gprs[rt] = kvm_mips_read_count(vcpu);
2339 case 3: /* Count register resolution */
2340 switch (current_cpu_data.cputype) {
2350 arch->gprs[rt] = kvm_read_c0_guest_userlocal(cop0);
2354 kvm_debug("RDHWR %#x not supported @ %p\n", rd, opc);
2358 kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);
2362 return EMULATE_DONE;
2366 * Rollback PC (if in branch delay slot then the PC already points to
2367 * branch target), and pass the RI exception to the guest OS.
2369 vcpu->arch.pc = curr_pc;
2370 return kvm_mips_emulate_ri_exc(cause, opc, run, vcpu);
2373 enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
2374 struct kvm_run *run)
2376 unsigned long *gpr = &vcpu->arch.gprs[vcpu->arch.io_gpr];
2377 enum emulation_result er = EMULATE_DONE;
2379 if (run->mmio.len > sizeof(*gpr)) {
2380 kvm_err("Bad MMIO length: %d", run->mmio.len);
2385 er = update_pc(vcpu, vcpu->arch.pending_load_cause);
2386 if (er == EMULATE_FAIL)
2389 switch (run->mmio.len) {
2391 *gpr = *(int32_t *) run->mmio.data;
2395 if (vcpu->mmio_needed == 2)
2396 *gpr = *(int16_t *) run->mmio.data;
2398 *gpr = *(uint16_t *)run->mmio.data;
2402 if (vcpu->mmio_needed == 2)
2403 *gpr = *(int8_t *) run->mmio.data;
2405 *gpr = *(u8 *) run->mmio.data;
2409 if (vcpu->arch.pending_load_cause & CAUSEF_BD)
2410 kvm_debug("[%#lx] Completing %d byte BD Load to gpr %d (0x%08lx) type %d\n",
2411 vcpu->arch.pc, run->mmio.len, vcpu->arch.io_gpr, *gpr,
2418 static enum emulation_result kvm_mips_emulate_exc(unsigned long cause,
2420 struct kvm_run *run,
2421 struct kvm_vcpu *vcpu)
2423 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2424 struct mips_coproc *cop0 = vcpu->arch.cop0;
2425 struct kvm_vcpu_arch *arch = &vcpu->arch;
2426 enum emulation_result er = EMULATE_DONE;
2428 if ((kvm_read_c0_guest_status(cop0) & ST0_EXL) == 0) {
2430 kvm_write_c0_guest_epc(cop0, arch->pc);
2431 kvm_set_c0_guest_status(cop0, ST0_EXL);
2433 if (cause & CAUSEF_BD)
2434 kvm_set_c0_guest_cause(cop0, CAUSEF_BD);
2436 kvm_clear_c0_guest_cause(cop0, CAUSEF_BD);
2438 kvm_change_c0_guest_cause(cop0, (0xff),
2439 (exccode << CAUSEB_EXCCODE));
2441 /* Set PC to the exception entry point */
2442 arch->pc = KVM_GUEST_KSEG0 + 0x180;
2443 kvm_write_c0_guest_badvaddr(cop0, vcpu->arch.host_cp0_badvaddr);
2445 kvm_debug("Delivering EXC %d @ pc %#lx, badVaddr: %#lx\n",
2446 exccode, kvm_read_c0_guest_epc(cop0),
2447 kvm_read_c0_guest_badvaddr(cop0));
2449 kvm_err("Trying to deliver EXC when EXL is already set\n");
2456 enum emulation_result kvm_mips_check_privilege(unsigned long cause,
2458 struct kvm_run *run,
2459 struct kvm_vcpu *vcpu)
2461 enum emulation_result er = EMULATE_DONE;
2462 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2463 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
2465 int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
2474 case EXCCODE_MSAFPE:
2476 case EXCCODE_MSADIS:
2480 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 0)
2481 er = EMULATE_PRIV_FAIL;
2489 * We we are accessing Guest kernel space, then send an
2490 * address error exception to the guest
2492 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2493 kvm_debug("%s: LD MISS @ %#lx\n", __func__,
2496 cause |= (EXCCODE_ADEL << CAUSEB_EXCCODE);
2497 er = EMULATE_PRIV_FAIL;
2503 * We we are accessing Guest kernel space, then send an
2504 * address error exception to the guest
2506 if (badvaddr >= (unsigned long) KVM_GUEST_KSEG0) {
2507 kvm_debug("%s: ST MISS @ %#lx\n", __func__,
2510 cause |= (EXCCODE_ADES << CAUSEB_EXCCODE);
2511 er = EMULATE_PRIV_FAIL;
2516 kvm_debug("%s: address error ST @ %#lx\n", __func__,
2518 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2520 cause |= (EXCCODE_TLBS << CAUSEB_EXCCODE);
2522 er = EMULATE_PRIV_FAIL;
2525 kvm_debug("%s: address error LD @ %#lx\n", __func__,
2527 if ((badvaddr & PAGE_MASK) == KVM_GUEST_COMMPAGE_ADDR) {
2529 cause |= (EXCCODE_TLBL << CAUSEB_EXCCODE);
2531 er = EMULATE_PRIV_FAIL;
2534 er = EMULATE_PRIV_FAIL;
2539 if (er == EMULATE_PRIV_FAIL)
2540 kvm_mips_emulate_exc(cause, opc, run, vcpu);
2546 * User Address (UA) fault, this could happen if
2547 * (1) TLB entry not present/valid in both Guest and shadow host TLBs, in this
2548 * case we pass on the fault to the guest kernel and let it handle it.
2549 * (2) TLB entry is present in the Guest TLB but not in the shadow, in this
2550 * case we inject the TLB from the Guest TLB into the shadow host TLB
2552 enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
2554 struct kvm_run *run,
2555 struct kvm_vcpu *vcpu)
2557 enum emulation_result er = EMULATE_DONE;
2558 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
2559 unsigned long va = vcpu->arch.host_cp0_badvaddr;
2562 kvm_debug("kvm_mips_handle_tlbmiss: badvaddr: %#lx, entryhi: %#lx\n",
2563 vcpu->arch.host_cp0_badvaddr, vcpu->arch.host_cp0_entryhi);
2566 * KVM would not have got the exception if this entry was valid in the
2567 * shadow host TLB. Check the Guest TLB, if the entry is not there then
2568 * send the guest an exception. The guest exc handler should then inject
2569 * an entry into the guest TLB.
2571 index = kvm_mips_guest_tlb_lookup(vcpu,
2573 (kvm_read_c0_guest_entryhi(vcpu->arch.cop0) & ASID_MASK));
2575 if (exccode == EXCCODE_TLBL) {
2576 er = kvm_mips_emulate_tlbmiss_ld(cause, opc, run, vcpu);
2577 } else if (exccode == EXCCODE_TLBS) {
2578 er = kvm_mips_emulate_tlbmiss_st(cause, opc, run, vcpu);
2580 kvm_err("%s: invalid exc code: %d\n", __func__,
2585 struct kvm_mips_tlb *tlb = &vcpu->arch.guest_tlb[index];
2588 * Check if the entry is valid, if not then setup a TLB invalid
2589 * exception to the guest
2591 if (!TLB_IS_VALID(*tlb, va)) {
2592 if (exccode == EXCCODE_TLBL) {
2593 er = kvm_mips_emulate_tlbinv_ld(cause, opc, run,
2595 } else if (exccode == EXCCODE_TLBS) {
2596 er = kvm_mips_emulate_tlbinv_st(cause, opc, run,
2599 kvm_err("%s: invalid exc code: %d\n", __func__,
2604 kvm_debug("Injecting hi: %#lx, lo0: %#lx, lo1: %#lx into shadow host TLB\n",
2605 tlb->tlb_hi, tlb->tlb_lo0, tlb->tlb_lo1);
2607 * OK we have a Guest TLB entry, now inject it into the
2610 kvm_mips_handle_mapped_seg_tlb_fault(vcpu, tlb, NULL,