2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
36 * Set the FIR feature flags for the FPU emulator.
38 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
43 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
44 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
45 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
46 value |= MIPS_FPIR_D | MIPS_FPIR_S;
47 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
48 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
49 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
53 static int mips_fpu_disabled;
55 static int __init fpu_disable(char *s)
57 boot_cpu_data.options &= ~MIPS_CPU_FPU;
58 cpu_set_nofpu_id(&boot_cpu_data);
59 mips_fpu_disabled = 1;
64 __setup("nofpu", fpu_disable);
66 int mips_dsp_disabled;
68 static int __init dsp_disable(char *s)
70 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
71 mips_dsp_disabled = 1;
76 __setup("nodsp", dsp_disable);
78 static int mips_htw_disabled;
80 static int __init htw_disable(char *s)
82 mips_htw_disabled = 1;
83 cpu_data[0].options &= ~MIPS_CPU_HTW;
84 write_c0_pwctl(read_c0_pwctl() &
85 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
90 __setup("nohtw", htw_disable);
92 static int mips_ftlb_disabled;
93 static int mips_has_ftlb_configured;
95 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
97 static int __init ftlb_disable(char *s)
99 unsigned int config4, mmuextdef;
102 * If the core hasn't done any FTLB configuration, there is nothing
105 if (!mips_has_ftlb_configured)
108 /* Disable it in the boot cpu */
109 set_ftlb_enable(&cpu_data[0], 0);
111 back_to_back_c0_hazard();
113 config4 = read_c0_config4();
115 /* Check that FTLB has been disabled */
116 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
117 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
118 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
119 /* This should never happen */
120 pr_warn("FTLB could not be disabled!\n");
124 mips_ftlb_disabled = 1;
125 mips_has_ftlb_configured = 0;
128 * noftlb is mainly used for debug purposes so print
129 * an informative message instead of using pr_debug()
131 pr_info("FTLB has been disabled\n");
134 * Some of these bits are duplicated in the decode_config4.
135 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
136 * once FTLB has been disabled so undo what decode_config4 did.
138 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
139 cpu_data[0].tlbsizeftlbsets;
140 cpu_data[0].tlbsizeftlbsets = 0;
141 cpu_data[0].tlbsizeftlbways = 0;
146 __setup("noftlb", ftlb_disable);
149 static inline void check_errata(void)
151 struct cpuinfo_mips *c = ¤t_cpu_data;
153 switch (current_cpu_type()) {
156 * Erratum "RPS May Cause Incorrect Instruction Execution"
157 * This code only handles VPE0, any SMP/RTOS code
158 * making use of VPE1 will be responsable for that VPE.
160 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
161 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
168 void __init check_bugs32(void)
174 * Probe whether cpu has config register by trying to play with
175 * alternate cache bit and see whether it matters.
176 * It's used by cpu_probe to distinguish between R3000A and R3081.
178 static inline int cpu_has_confreg(void)
180 #ifdef CONFIG_CPU_R3000
181 extern unsigned long r3k_cache_size(unsigned long);
182 unsigned long size1, size2;
183 unsigned long cfg = read_c0_conf();
185 size1 = r3k_cache_size(ST0_ISC);
186 write_c0_conf(cfg ^ R30XX_CONF_AC);
187 size2 = r3k_cache_size(ST0_ISC);
189 return size1 != size2;
195 static inline void set_elf_platform(int cpu, const char *plat)
198 __elf_platform = plat;
202 * Get the FPU Implementation/Revision.
204 static inline unsigned long cpu_get_fpu_id(void)
206 unsigned long tmp, fpu_id;
208 tmp = read_c0_status();
209 __enable_fpu(FPU_AS_IS);
210 fpu_id = read_32bit_cp1_register(CP1_REVISION);
211 write_c0_status(tmp);
216 * Check if the CPU has an external FPU.
218 static inline int __cpu_has_fpu(void)
220 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
223 static inline unsigned long cpu_get_msa_id(void)
225 unsigned long status, msa_id;
227 status = read_c0_status();
228 __enable_fpu(FPU_64BIT);
230 msa_id = read_msa_ir();
232 write_c0_status(status);
236 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
238 #ifdef __NEED_VMBITS_PROBE
239 write_c0_entryhi(0x3fffffffffffe000ULL);
240 back_to_back_c0_hazard();
241 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
245 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
248 case MIPS_CPU_ISA_M64R2:
249 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
250 case MIPS_CPU_ISA_M64R1:
251 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
253 c->isa_level |= MIPS_CPU_ISA_V;
254 case MIPS_CPU_ISA_IV:
255 c->isa_level |= MIPS_CPU_ISA_IV;
256 case MIPS_CPU_ISA_III:
257 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
260 /* R6 incompatible with everything else */
261 case MIPS_CPU_ISA_M64R6:
262 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
263 case MIPS_CPU_ISA_M32R6:
264 c->isa_level |= MIPS_CPU_ISA_M32R6;
265 /* Break here so we don't add incompatible ISAs */
267 case MIPS_CPU_ISA_M32R2:
268 c->isa_level |= MIPS_CPU_ISA_M32R2;
269 case MIPS_CPU_ISA_M32R1:
270 c->isa_level |= MIPS_CPU_ISA_M32R1;
271 case MIPS_CPU_ISA_II:
272 c->isa_level |= MIPS_CPU_ISA_II;
277 static char unknown_isa[] = KERN_ERR \
278 "Unsupported ISA type, c0.config0: %d.";
280 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
283 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
286 * 0 = All TLBWR instructions go to FTLB
287 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
288 * FTLB and 1 goes to the VTLB.
289 * 2 = 7:1: As above with 7:1 ratio.
290 * 3 = 3:1: As above with 3:1 ratio.
292 * Use the linear midpoint as the probability threshold.
294 if (probability >= 12)
296 else if (probability >= 6)
300 * So FTLB is less than 4 times bigger than VTLB.
301 * A 3:1 ratio can still be useful though.
306 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
308 unsigned int config6;
310 /* It's implementation dependent how the FTLB can be enabled */
311 switch (c->cputype) {
314 /* proAptiv & related cores use Config6 to enable the FTLB */
315 config6 = read_c0_config6();
316 /* Clear the old probability value */
317 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
320 write_c0_config6(config6 |
321 (calculate_ftlb_probability(c)
322 << MIPS_CONF6_FTLBP_SHIFT)
323 | MIPS_CONF6_FTLBEN);
326 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
327 back_to_back_c0_hazard();
332 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
334 unsigned int config0;
337 config0 = read_c0_config();
340 * Look for Standard TLB or Dual VTLB and FTLB
342 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) ||
343 (((config0 & MIPS_CONF_MT) >> 7) == 4))
344 c->options |= MIPS_CPU_TLB;
346 isa = (config0 & MIPS_CONF_AT) >> 13;
349 switch ((config0 & MIPS_CONF_AR) >> 10) {
351 set_isa(c, MIPS_CPU_ISA_M32R1);
354 set_isa(c, MIPS_CPU_ISA_M32R2);
357 set_isa(c, MIPS_CPU_ISA_M32R6);
364 switch ((config0 & MIPS_CONF_AR) >> 10) {
366 set_isa(c, MIPS_CPU_ISA_M64R1);
369 set_isa(c, MIPS_CPU_ISA_M64R2);
372 set_isa(c, MIPS_CPU_ISA_M64R6);
382 return config0 & MIPS_CONF_M;
385 panic(unknown_isa, config0);
388 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
390 unsigned int config1;
392 config1 = read_c0_config1();
394 if (config1 & MIPS_CONF1_MD)
395 c->ases |= MIPS_ASE_MDMX;
396 if (config1 & MIPS_CONF1_WR)
397 c->options |= MIPS_CPU_WATCH;
398 if (config1 & MIPS_CONF1_CA)
399 c->ases |= MIPS_ASE_MIPS16;
400 if (config1 & MIPS_CONF1_EP)
401 c->options |= MIPS_CPU_EJTAG;
402 if (config1 & MIPS_CONF1_FP) {
403 c->options |= MIPS_CPU_FPU;
404 c->options |= MIPS_CPU_32FPR;
407 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
408 c->tlbsizevtlb = c->tlbsize;
409 c->tlbsizeftlbsets = 0;
412 return config1 & MIPS_CONF_M;
415 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
417 unsigned int config2;
419 config2 = read_c0_config2();
421 if (config2 & MIPS_CONF2_SL)
422 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
424 return config2 & MIPS_CONF_M;
427 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
429 unsigned int config3;
431 config3 = read_c0_config3();
433 if (config3 & MIPS_CONF3_SM) {
434 c->ases |= MIPS_ASE_SMARTMIPS;
435 c->options |= MIPS_CPU_RIXI;
437 if (config3 & MIPS_CONF3_RXI)
438 c->options |= MIPS_CPU_RIXI;
439 if (config3 & MIPS_CONF3_DSP)
440 c->ases |= MIPS_ASE_DSP;
441 if (config3 & MIPS_CONF3_DSP2P)
442 c->ases |= MIPS_ASE_DSP2P;
443 if (config3 & MIPS_CONF3_VINT)
444 c->options |= MIPS_CPU_VINT;
445 if (config3 & MIPS_CONF3_VEIC)
446 c->options |= MIPS_CPU_VEIC;
447 if (config3 & MIPS_CONF3_MT)
448 c->ases |= MIPS_ASE_MIPSMT;
449 if (config3 & MIPS_CONF3_ULRI)
450 c->options |= MIPS_CPU_ULRI;
451 if (config3 & MIPS_CONF3_ISA)
452 c->options |= MIPS_CPU_MICROMIPS;
453 if (config3 & MIPS_CONF3_VZ)
454 c->ases |= MIPS_ASE_VZ;
455 if (config3 & MIPS_CONF3_SC)
456 c->options |= MIPS_CPU_SEGMENTS;
457 if (config3 & MIPS_CONF3_MSA)
458 c->ases |= MIPS_ASE_MSA;
459 /* Only tested on 32-bit cores */
460 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
462 c->options |= MIPS_CPU_HTW;
464 if (config3 & MIPS_CONF3_CDMM)
465 c->options |= MIPS_CPU_CDMM;
467 return config3 & MIPS_CONF_M;
470 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
472 unsigned int config4;
474 unsigned int mmuextdef;
475 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
477 config4 = read_c0_config4();
480 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
481 c->options |= MIPS_CPU_TLBINV;
482 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
484 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
485 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
486 c->tlbsizevtlb = c->tlbsize;
488 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
490 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
491 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
492 c->tlbsize = c->tlbsizevtlb;
493 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
495 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
496 if (mips_ftlb_disabled)
498 newcf4 = (config4 & ~ftlb_page) |
499 (page_size_ftlb(mmuextdef) <<
500 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
501 write_c0_config4(newcf4);
502 back_to_back_c0_hazard();
503 config4 = read_c0_config4();
504 if (config4 != newcf4) {
505 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
507 /* Switch FTLB off */
508 set_ftlb_enable(c, 0);
511 c->tlbsizeftlbsets = 1 <<
512 ((config4 & MIPS_CONF4_FTLBSETS) >>
513 MIPS_CONF4_FTLBSETS_SHIFT);
514 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
515 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
516 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
517 mips_has_ftlb_configured = 1;
522 c->kscratch_mask = (config4 >> 16) & 0xff;
524 return config4 & MIPS_CONF_M;
527 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
529 unsigned int config5;
531 config5 = read_c0_config5();
532 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
533 write_c0_config5(config5);
535 if (config5 & MIPS_CONF5_EVA)
536 c->options |= MIPS_CPU_EVA;
537 if (config5 & MIPS_CONF5_MRP)
538 c->options |= MIPS_CPU_MAAR;
539 if (config5 & MIPS_CONF5_LLB)
540 c->options |= MIPS_CPU_RW_LLB;
542 return config5 & MIPS_CONF_M;
545 static void decode_configs(struct cpuinfo_mips *c)
549 /* MIPS32 or MIPS64 compliant CPU. */
550 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
551 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
553 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
555 /* Enable FTLB if present and not disabled */
556 set_ftlb_enable(c, !mips_ftlb_disabled);
558 ok = decode_config0(c); /* Read Config registers. */
559 BUG_ON(!ok); /* Arch spec violation! */
561 ok = decode_config1(c);
563 ok = decode_config2(c);
565 ok = decode_config3(c);
567 ok = decode_config4(c);
569 ok = decode_config5(c);
571 mips_probe_watch_registers(c);
574 /* Enable the RIXI exceptions */
575 set_c0_pagegrain(PG_IEC);
576 back_to_back_c0_hazard();
577 /* Verify the IEC bit is set */
578 if (read_c0_pagegrain() & PG_IEC)
579 c->options |= MIPS_CPU_RIXIEX;
582 #ifndef CONFIG_MIPS_CPS
583 if (cpu_has_mips_r2_r6) {
584 c->core = get_ebase_cpunum();
586 c->core >>= fls(core_nvpes()) - 1;
591 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
594 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
596 switch (c->processor_id & PRID_IMP_MASK) {
598 c->cputype = CPU_R2000;
599 __cpu_name[cpu] = "R2000";
600 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
603 c->options |= MIPS_CPU_FPU;
607 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
608 if (cpu_has_confreg()) {
609 c->cputype = CPU_R3081E;
610 __cpu_name[cpu] = "R3081";
612 c->cputype = CPU_R3000A;
613 __cpu_name[cpu] = "R3000A";
616 c->cputype = CPU_R3000;
617 __cpu_name[cpu] = "R3000";
619 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
622 c->options |= MIPS_CPU_FPU;
626 if (read_c0_config() & CONF_SC) {
627 if ((c->processor_id & PRID_REV_MASK) >=
629 c->cputype = CPU_R4400PC;
630 __cpu_name[cpu] = "R4400PC";
632 c->cputype = CPU_R4000PC;
633 __cpu_name[cpu] = "R4000PC";
636 int cca = read_c0_config() & CONF_CM_CMASK;
640 * SC and MC versions can't be reliably told apart,
641 * but only the latter support coherent caching
642 * modes so assume the firmware has set the KSEG0
643 * coherency attribute reasonably (if uncached, we
647 case CONF_CM_CACHABLE_CE:
648 case CONF_CM_CACHABLE_COW:
649 case CONF_CM_CACHABLE_CUW:
656 if ((c->processor_id & PRID_REV_MASK) >=
658 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
659 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
661 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
662 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
666 set_isa(c, MIPS_CPU_ISA_III);
667 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
668 MIPS_CPU_WATCH | MIPS_CPU_VCE |
672 case PRID_IMP_VR41XX:
673 set_isa(c, MIPS_CPU_ISA_III);
674 c->options = R4K_OPTS;
676 switch (c->processor_id & 0xf0) {
677 case PRID_REV_VR4111:
678 c->cputype = CPU_VR4111;
679 __cpu_name[cpu] = "NEC VR4111";
681 case PRID_REV_VR4121:
682 c->cputype = CPU_VR4121;
683 __cpu_name[cpu] = "NEC VR4121";
685 case PRID_REV_VR4122:
686 if ((c->processor_id & 0xf) < 0x3) {
687 c->cputype = CPU_VR4122;
688 __cpu_name[cpu] = "NEC VR4122";
690 c->cputype = CPU_VR4181A;
691 __cpu_name[cpu] = "NEC VR4181A";
694 case PRID_REV_VR4130:
695 if ((c->processor_id & 0xf) < 0x4) {
696 c->cputype = CPU_VR4131;
697 __cpu_name[cpu] = "NEC VR4131";
699 c->cputype = CPU_VR4133;
700 c->options |= MIPS_CPU_LLSC;
701 __cpu_name[cpu] = "NEC VR4133";
705 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
706 c->cputype = CPU_VR41XX;
707 __cpu_name[cpu] = "NEC Vr41xx";
712 c->cputype = CPU_R4300;
713 __cpu_name[cpu] = "R4300";
714 set_isa(c, MIPS_CPU_ISA_III);
715 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
720 c->cputype = CPU_R4600;
721 __cpu_name[cpu] = "R4600";
722 set_isa(c, MIPS_CPU_ISA_III);
723 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
730 * This processor doesn't have an MMU, so it's not
731 * "real easy" to run Linux on it. It is left purely
732 * for documentation. Commented out because it shares
733 * it's c0_prid id number with the TX3900.
735 c->cputype = CPU_R4650;
736 __cpu_name[cpu] = "R4650";
737 set_isa(c, MIPS_CPU_ISA_III);
738 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
743 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
745 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
746 c->cputype = CPU_TX3927;
747 __cpu_name[cpu] = "TX3927";
750 switch (c->processor_id & PRID_REV_MASK) {
751 case PRID_REV_TX3912:
752 c->cputype = CPU_TX3912;
753 __cpu_name[cpu] = "TX3912";
756 case PRID_REV_TX3922:
757 c->cputype = CPU_TX3922;
758 __cpu_name[cpu] = "TX3922";
765 c->cputype = CPU_R4700;
766 __cpu_name[cpu] = "R4700";
767 set_isa(c, MIPS_CPU_ISA_III);
768 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
773 c->cputype = CPU_TX49XX;
774 __cpu_name[cpu] = "R49XX";
775 set_isa(c, MIPS_CPU_ISA_III);
776 c->options = R4K_OPTS | MIPS_CPU_LLSC;
777 if (!(c->processor_id & 0x08))
778 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
782 c->cputype = CPU_R5000;
783 __cpu_name[cpu] = "R5000";
784 set_isa(c, MIPS_CPU_ISA_IV);
785 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
790 c->cputype = CPU_R5432;
791 __cpu_name[cpu] = "R5432";
792 set_isa(c, MIPS_CPU_ISA_IV);
793 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
794 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
798 c->cputype = CPU_R5500;
799 __cpu_name[cpu] = "R5500";
800 set_isa(c, MIPS_CPU_ISA_IV);
801 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
802 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
805 case PRID_IMP_NEVADA:
806 c->cputype = CPU_NEVADA;
807 __cpu_name[cpu] = "Nevada";
808 set_isa(c, MIPS_CPU_ISA_IV);
809 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
810 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
814 c->cputype = CPU_R6000;
815 __cpu_name[cpu] = "R6000";
816 set_isa(c, MIPS_CPU_ISA_II);
817 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
821 case PRID_IMP_R6000A:
822 c->cputype = CPU_R6000A;
823 __cpu_name[cpu] = "R6000A";
824 set_isa(c, MIPS_CPU_ISA_II);
825 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
829 case PRID_IMP_RM7000:
830 c->cputype = CPU_RM7000;
831 __cpu_name[cpu] = "RM7000";
832 set_isa(c, MIPS_CPU_ISA_IV);
833 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
836 * Undocumented RM7000: Bit 29 in the info register of
837 * the RM7000 v2.0 indicates if the TLB has 48 or 64
840 * 29 1 => 64 entry JTLB
843 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
846 c->cputype = CPU_R8000;
847 __cpu_name[cpu] = "RM8000";
848 set_isa(c, MIPS_CPU_ISA_IV);
849 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
850 MIPS_CPU_FPU | MIPS_CPU_32FPR |
852 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
854 case PRID_IMP_R10000:
855 c->cputype = CPU_R10000;
856 __cpu_name[cpu] = "R10000";
857 set_isa(c, MIPS_CPU_ISA_IV);
858 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
859 MIPS_CPU_FPU | MIPS_CPU_32FPR |
860 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
864 case PRID_IMP_R12000:
865 c->cputype = CPU_R12000;
866 __cpu_name[cpu] = "R12000";
867 set_isa(c, MIPS_CPU_ISA_IV);
868 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
869 MIPS_CPU_FPU | MIPS_CPU_32FPR |
870 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
874 case PRID_IMP_R14000:
875 if (((c->processor_id >> 4) & 0x0f) > 2) {
876 c->cputype = CPU_R16000;
877 __cpu_name[cpu] = "R16000";
879 c->cputype = CPU_R14000;
880 __cpu_name[cpu] = "R14000";
882 set_isa(c, MIPS_CPU_ISA_IV);
883 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
884 MIPS_CPU_FPU | MIPS_CPU_32FPR |
885 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
889 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
890 switch (c->processor_id & PRID_REV_MASK) {
891 case PRID_REV_LOONGSON2E:
892 c->cputype = CPU_LOONGSON2;
893 __cpu_name[cpu] = "ICT Loongson-2";
894 set_elf_platform(cpu, "loongson2e");
895 set_isa(c, MIPS_CPU_ISA_III);
897 case PRID_REV_LOONGSON2F:
898 c->cputype = CPU_LOONGSON2;
899 __cpu_name[cpu] = "ICT Loongson-2";
900 set_elf_platform(cpu, "loongson2f");
901 set_isa(c, MIPS_CPU_ISA_III);
903 case PRID_REV_LOONGSON3A:
904 c->cputype = CPU_LOONGSON3;
905 __cpu_name[cpu] = "ICT Loongson-3";
906 set_elf_platform(cpu, "loongson3a");
907 set_isa(c, MIPS_CPU_ISA_M64R1);
909 case PRID_REV_LOONGSON3B_R1:
910 case PRID_REV_LOONGSON3B_R2:
911 c->cputype = CPU_LOONGSON3;
912 __cpu_name[cpu] = "ICT Loongson-3";
913 set_elf_platform(cpu, "loongson3b");
914 set_isa(c, MIPS_CPU_ISA_M64R1);
918 c->options = R4K_OPTS |
919 MIPS_CPU_FPU | MIPS_CPU_LLSC |
922 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
924 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
927 c->cputype = CPU_LOONGSON1;
929 switch (c->processor_id & PRID_REV_MASK) {
930 case PRID_REV_LOONGSON1B:
931 __cpu_name[cpu] = "Loongson 1B";
939 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
941 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
942 switch (c->processor_id & PRID_IMP_MASK) {
943 case PRID_IMP_QEMU_GENERIC:
944 c->writecombine = _CACHE_UNCACHED;
945 c->cputype = CPU_QEMU_GENERIC;
946 __cpu_name[cpu] = "MIPS GENERIC QEMU";
949 c->cputype = CPU_4KC;
950 c->writecombine = _CACHE_UNCACHED;
951 __cpu_name[cpu] = "MIPS 4Kc";
954 case PRID_IMP_4KECR2:
955 c->cputype = CPU_4KEC;
956 c->writecombine = _CACHE_UNCACHED;
957 __cpu_name[cpu] = "MIPS 4KEc";
961 c->cputype = CPU_4KSC;
962 c->writecombine = _CACHE_UNCACHED;
963 __cpu_name[cpu] = "MIPS 4KSc";
966 c->cputype = CPU_5KC;
967 c->writecombine = _CACHE_UNCACHED;
968 __cpu_name[cpu] = "MIPS 5Kc";
971 c->cputype = CPU_5KE;
972 c->writecombine = _CACHE_UNCACHED;
973 __cpu_name[cpu] = "MIPS 5KE";
976 c->cputype = CPU_20KC;
977 c->writecombine = _CACHE_UNCACHED;
978 __cpu_name[cpu] = "MIPS 20Kc";
981 c->cputype = CPU_24K;
982 c->writecombine = _CACHE_UNCACHED;
983 __cpu_name[cpu] = "MIPS 24Kc";
986 c->cputype = CPU_24K;
987 c->writecombine = _CACHE_UNCACHED;
988 __cpu_name[cpu] = "MIPS 24KEc";
991 c->cputype = CPU_25KF;
992 c->writecombine = _CACHE_UNCACHED;
993 __cpu_name[cpu] = "MIPS 25Kc";
996 c->cputype = CPU_34K;
997 c->writecombine = _CACHE_UNCACHED;
998 __cpu_name[cpu] = "MIPS 34Kc";
1001 c->cputype = CPU_74K;
1002 c->writecombine = _CACHE_UNCACHED;
1003 __cpu_name[cpu] = "MIPS 74Kc";
1005 case PRID_IMP_M14KC:
1006 c->cputype = CPU_M14KC;
1007 c->writecombine = _CACHE_UNCACHED;
1008 __cpu_name[cpu] = "MIPS M14Kc";
1010 case PRID_IMP_M14KEC:
1011 c->cputype = CPU_M14KEC;
1012 c->writecombine = _CACHE_UNCACHED;
1013 __cpu_name[cpu] = "MIPS M14KEc";
1015 case PRID_IMP_1004K:
1016 c->cputype = CPU_1004K;
1017 c->writecombine = _CACHE_UNCACHED;
1018 __cpu_name[cpu] = "MIPS 1004Kc";
1020 case PRID_IMP_1074K:
1021 c->cputype = CPU_1074K;
1022 c->writecombine = _CACHE_UNCACHED;
1023 __cpu_name[cpu] = "MIPS 1074Kc";
1025 case PRID_IMP_INTERAPTIV_UP:
1026 c->cputype = CPU_INTERAPTIV;
1027 __cpu_name[cpu] = "MIPS interAptiv";
1029 case PRID_IMP_INTERAPTIV_MP:
1030 c->cputype = CPU_INTERAPTIV;
1031 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1033 case PRID_IMP_PROAPTIV_UP:
1034 c->cputype = CPU_PROAPTIV;
1035 __cpu_name[cpu] = "MIPS proAptiv";
1037 case PRID_IMP_PROAPTIV_MP:
1038 c->cputype = CPU_PROAPTIV;
1039 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1041 case PRID_IMP_P5600:
1042 c->cputype = CPU_P5600;
1043 __cpu_name[cpu] = "MIPS P5600";
1045 case PRID_IMP_M5150:
1046 c->cputype = CPU_M5150;
1047 __cpu_name[cpu] = "MIPS M5150";
1056 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1059 switch (c->processor_id & PRID_IMP_MASK) {
1060 case PRID_IMP_AU1_REV1:
1061 case PRID_IMP_AU1_REV2:
1062 c->cputype = CPU_ALCHEMY;
1063 switch ((c->processor_id >> 24) & 0xff) {
1065 __cpu_name[cpu] = "Au1000";
1068 __cpu_name[cpu] = "Au1500";
1071 __cpu_name[cpu] = "Au1100";
1074 __cpu_name[cpu] = "Au1550";
1077 __cpu_name[cpu] = "Au1200";
1078 if ((c->processor_id & PRID_REV_MASK) == 2)
1079 __cpu_name[cpu] = "Au1250";
1082 __cpu_name[cpu] = "Au1210";
1085 __cpu_name[cpu] = "Au1xxx";
1092 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1096 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1097 switch (c->processor_id & PRID_IMP_MASK) {
1099 c->cputype = CPU_SB1;
1100 __cpu_name[cpu] = "SiByte SB1";
1101 /* FPU in pass1 is known to have issues. */
1102 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1103 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1106 c->cputype = CPU_SB1A;
1107 __cpu_name[cpu] = "SiByte SB1A";
1112 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1115 switch (c->processor_id & PRID_IMP_MASK) {
1116 case PRID_IMP_SR71000:
1117 c->cputype = CPU_SR71000;
1118 __cpu_name[cpu] = "Sandcraft SR71000";
1125 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1128 switch (c->processor_id & PRID_IMP_MASK) {
1129 case PRID_IMP_PR4450:
1130 c->cputype = CPU_PR4450;
1131 __cpu_name[cpu] = "Philips PR4450";
1132 set_isa(c, MIPS_CPU_ISA_M32R1);
1137 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1140 switch (c->processor_id & PRID_IMP_MASK) {
1141 case PRID_IMP_BMIPS32_REV4:
1142 case PRID_IMP_BMIPS32_REV8:
1143 c->cputype = CPU_BMIPS32;
1144 __cpu_name[cpu] = "Broadcom BMIPS32";
1145 set_elf_platform(cpu, "bmips32");
1147 case PRID_IMP_BMIPS3300:
1148 case PRID_IMP_BMIPS3300_ALT:
1149 case PRID_IMP_BMIPS3300_BUG:
1150 c->cputype = CPU_BMIPS3300;
1151 __cpu_name[cpu] = "Broadcom BMIPS3300";
1152 set_elf_platform(cpu, "bmips3300");
1154 case PRID_IMP_BMIPS43XX: {
1155 int rev = c->processor_id & PRID_REV_MASK;
1157 if (rev >= PRID_REV_BMIPS4380_LO &&
1158 rev <= PRID_REV_BMIPS4380_HI) {
1159 c->cputype = CPU_BMIPS4380;
1160 __cpu_name[cpu] = "Broadcom BMIPS4380";
1161 set_elf_platform(cpu, "bmips4380");
1163 c->cputype = CPU_BMIPS4350;
1164 __cpu_name[cpu] = "Broadcom BMIPS4350";
1165 set_elf_platform(cpu, "bmips4350");
1169 case PRID_IMP_BMIPS5000:
1170 case PRID_IMP_BMIPS5200:
1171 c->cputype = CPU_BMIPS5000;
1172 __cpu_name[cpu] = "Broadcom BMIPS5000";
1173 set_elf_platform(cpu, "bmips5000");
1174 c->options |= MIPS_CPU_ULRI;
1179 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1182 switch (c->processor_id & PRID_IMP_MASK) {
1183 case PRID_IMP_CAVIUM_CN38XX:
1184 case PRID_IMP_CAVIUM_CN31XX:
1185 case PRID_IMP_CAVIUM_CN30XX:
1186 c->cputype = CPU_CAVIUM_OCTEON;
1187 __cpu_name[cpu] = "Cavium Octeon";
1189 case PRID_IMP_CAVIUM_CN58XX:
1190 case PRID_IMP_CAVIUM_CN56XX:
1191 case PRID_IMP_CAVIUM_CN50XX:
1192 case PRID_IMP_CAVIUM_CN52XX:
1193 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1194 __cpu_name[cpu] = "Cavium Octeon+";
1196 set_elf_platform(cpu, "octeon");
1198 case PRID_IMP_CAVIUM_CN61XX:
1199 case PRID_IMP_CAVIUM_CN63XX:
1200 case PRID_IMP_CAVIUM_CN66XX:
1201 case PRID_IMP_CAVIUM_CN68XX:
1202 case PRID_IMP_CAVIUM_CNF71XX:
1203 c->cputype = CPU_CAVIUM_OCTEON2;
1204 __cpu_name[cpu] = "Cavium Octeon II";
1205 set_elf_platform(cpu, "octeon2");
1207 case PRID_IMP_CAVIUM_CN70XX:
1208 case PRID_IMP_CAVIUM_CN78XX:
1209 c->cputype = CPU_CAVIUM_OCTEON3;
1210 __cpu_name[cpu] = "Cavium Octeon III";
1211 set_elf_platform(cpu, "octeon3");
1214 printk(KERN_INFO "Unknown Octeon chip!\n");
1215 c->cputype = CPU_UNKNOWN;
1220 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1223 /* JZRISC does not implement the CP0 counter. */
1224 c->options &= ~MIPS_CPU_COUNTER;
1225 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1226 switch (c->processor_id & PRID_IMP_MASK) {
1227 case PRID_IMP_JZRISC:
1228 c->cputype = CPU_JZRISC;
1229 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1230 __cpu_name[cpu] = "Ingenic JZRISC";
1233 panic("Unknown Ingenic Processor ID!");
1238 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1242 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1243 c->cputype = CPU_ALCHEMY;
1244 __cpu_name[cpu] = "Au1300";
1245 /* following stuff is not for Alchemy */
1249 c->options = (MIPS_CPU_TLB |
1257 switch (c->processor_id & PRID_IMP_MASK) {
1258 case PRID_IMP_NETLOGIC_XLP2XX:
1259 case PRID_IMP_NETLOGIC_XLP9XX:
1260 case PRID_IMP_NETLOGIC_XLP5XX:
1261 c->cputype = CPU_XLP;
1262 __cpu_name[cpu] = "Broadcom XLPII";
1265 case PRID_IMP_NETLOGIC_XLP8XX:
1266 case PRID_IMP_NETLOGIC_XLP3XX:
1267 c->cputype = CPU_XLP;
1268 __cpu_name[cpu] = "Netlogic XLP";
1271 case PRID_IMP_NETLOGIC_XLR732:
1272 case PRID_IMP_NETLOGIC_XLR716:
1273 case PRID_IMP_NETLOGIC_XLR532:
1274 case PRID_IMP_NETLOGIC_XLR308:
1275 case PRID_IMP_NETLOGIC_XLR532C:
1276 case PRID_IMP_NETLOGIC_XLR516C:
1277 case PRID_IMP_NETLOGIC_XLR508C:
1278 case PRID_IMP_NETLOGIC_XLR308C:
1279 c->cputype = CPU_XLR;
1280 __cpu_name[cpu] = "Netlogic XLR";
1283 case PRID_IMP_NETLOGIC_XLS608:
1284 case PRID_IMP_NETLOGIC_XLS408:
1285 case PRID_IMP_NETLOGIC_XLS404:
1286 case PRID_IMP_NETLOGIC_XLS208:
1287 case PRID_IMP_NETLOGIC_XLS204:
1288 case PRID_IMP_NETLOGIC_XLS108:
1289 case PRID_IMP_NETLOGIC_XLS104:
1290 case PRID_IMP_NETLOGIC_XLS616B:
1291 case PRID_IMP_NETLOGIC_XLS608B:
1292 case PRID_IMP_NETLOGIC_XLS416B:
1293 case PRID_IMP_NETLOGIC_XLS412B:
1294 case PRID_IMP_NETLOGIC_XLS408B:
1295 case PRID_IMP_NETLOGIC_XLS404B:
1296 c->cputype = CPU_XLR;
1297 __cpu_name[cpu] = "Netlogic XLS";
1301 pr_info("Unknown Netlogic chip id [%02x]!\n",
1303 c->cputype = CPU_XLR;
1307 if (c->cputype == CPU_XLP) {
1308 set_isa(c, MIPS_CPU_ISA_M64R2);
1309 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1310 /* This will be updated again after all threads are woken up */
1311 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1313 set_isa(c, MIPS_CPU_ISA_M64R1);
1314 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1316 c->kscratch_mask = 0xf;
1320 /* For use by uaccess.h */
1322 EXPORT_SYMBOL(__ua_limit);
1325 const char *__cpu_name[NR_CPUS];
1326 const char *__elf_platform;
1328 void cpu_probe(void)
1330 struct cpuinfo_mips *c = ¤t_cpu_data;
1331 unsigned int cpu = smp_processor_id();
1333 c->processor_id = PRID_IMP_UNKNOWN;
1334 c->fpu_id = FPIR_IMP_NONE;
1335 c->cputype = CPU_UNKNOWN;
1336 c->writecombine = _CACHE_UNCACHED;
1338 c->processor_id = read_c0_prid();
1339 switch (c->processor_id & PRID_COMP_MASK) {
1340 case PRID_COMP_LEGACY:
1341 cpu_probe_legacy(c, cpu);
1343 case PRID_COMP_MIPS:
1344 cpu_probe_mips(c, cpu);
1346 case PRID_COMP_ALCHEMY:
1347 cpu_probe_alchemy(c, cpu);
1349 case PRID_COMP_SIBYTE:
1350 cpu_probe_sibyte(c, cpu);
1352 case PRID_COMP_BROADCOM:
1353 cpu_probe_broadcom(c, cpu);
1355 case PRID_COMP_SANDCRAFT:
1356 cpu_probe_sandcraft(c, cpu);
1359 cpu_probe_nxp(c, cpu);
1361 case PRID_COMP_CAVIUM:
1362 cpu_probe_cavium(c, cpu);
1364 case PRID_COMP_INGENIC:
1365 cpu_probe_ingenic(c, cpu);
1367 case PRID_COMP_NETLOGIC:
1368 cpu_probe_netlogic(c, cpu);
1372 BUG_ON(!__cpu_name[cpu]);
1373 BUG_ON(c->cputype == CPU_UNKNOWN);
1376 * Platform code can force the cpu type to optimize code
1377 * generation. In that case be sure the cpu type is correctly
1378 * manually setup otherwise it could trigger some nasty bugs.
1380 BUG_ON(current_cpu_type() != c->cputype);
1382 if (mips_fpu_disabled)
1383 c->options &= ~MIPS_CPU_FPU;
1385 if (mips_dsp_disabled)
1386 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1388 if (mips_htw_disabled) {
1389 c->options &= ~MIPS_CPU_HTW;
1390 write_c0_pwctl(read_c0_pwctl() &
1391 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1394 if (c->options & MIPS_CPU_FPU) {
1395 c->fpu_id = cpu_get_fpu_id();
1397 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
1398 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
1399 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
1400 if (c->fpu_id & MIPS_FPIR_3D)
1401 c->ases |= MIPS_ASE_MIPS3D;
1402 if (c->fpu_id & MIPS_FPIR_FREP)
1403 c->options |= MIPS_CPU_FRE;
1406 cpu_set_nofpu_id(c);
1408 if (cpu_has_mips_r2_r6) {
1409 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1410 /* R2 has Performance Counter Interrupt indicator */
1411 c->options |= MIPS_CPU_PCI;
1417 c->msa_id = cpu_get_msa_id();
1418 WARN(c->msa_id & MSA_IR_WRPF,
1419 "Vector register partitioning unimplemented!");
1422 cpu_probe_vmbits(c);
1426 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1430 void cpu_report(void)
1432 struct cpuinfo_mips *c = ¤t_cpu_data;
1434 pr_info("CPU%d revision is: %08x (%s)\n",
1435 smp_processor_id(), c->processor_id, cpu_name_string());
1436 if (c->options & MIPS_CPU_FPU)
1437 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1439 pr_info("MSA revision is: %08x\n", c->msa_id);