arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <asm/uaccess.h>
  34
  35 /* Hardware capabilities */
  36 unsigned int elf_hwcap __read_mostly;
  37
  38 /*
  39  * Get the FPU Implementation/Revision.
  40  */
  41 static inline unsigned long cpu_get_fpu_id(void)
  42 {
  43         unsigned long tmp, fpu_id;
  44
  45         tmp = read_c0_status();
  46         __enable_fpu(FPU_AS_IS);
  47         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  48         write_c0_status(tmp);
  49         return fpu_id;
  50 }
  51
  52 /*
  53  * Check if the CPU has an external FPU.
  54  */
  55 static inline int __cpu_has_fpu(void)
  56 {
  57         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  58 }
  59
  60 static inline unsigned long cpu_get_msa_id(void)
  61 {
  62         unsigned long status, msa_id;
  63
  64         status = read_c0_status();
  65         __enable_fpu(FPU_64BIT);
  66         enable_msa();
  67         msa_id = read_msa_ir();
  68         disable_msa();
  69         write_c0_status(status);
  70         return msa_id;
  71 }
  72
  73 /*
  74  * Determine the FCSR mask for FPU hardware.
  75  */
  76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  77 {
  78         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  79
  80         fcsr = c->fpu_csr31;
  81         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  82
  83         sr = read_c0_status();
  84         __enable_fpu(FPU_AS_IS);
  85
  86         fcsr0 = fcsr & mask;
  87         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  88         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  89
  90         fcsr1 = fcsr | ~mask;
  91         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  92         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  93
  94         write_32bit_cp1_register(CP1_STATUS, fcsr);
  95
  96         write_c0_status(sr);
  97
  98         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  99 }
 100
 101 /*
 102  * Set the FIR feature flags for the FPU emulator.
 103  */
 104 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 105 {
 106         u32 value;
 107
 108         value = 0;
 109         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 110                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 111                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 112                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 113         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 114                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 115                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 116         c->fpu_id = value;
 117 }
 118
 119 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 120 static unsigned int mips_nofpu_msk31;
 121
 122 /*
 123  * Set options for FPU hardware.
 124  */
 125 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 126 {
 127         c->fpu_id = cpu_get_fpu_id();
 128         mips_nofpu_msk31 = c->fpu_msk31;
 129
 130         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 131                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 132                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 133                 if (c->fpu_id & MIPS_FPIR_3D)
 134                         c->ases |= MIPS_ASE_MIPS3D;
 135                 if (c->fpu_id & MIPS_FPIR_FREP)
 136                         c->options |= MIPS_CPU_FRE;
 137         }
 138
 139         cpu_set_fpu_fcsr_mask(c);
 140 }
 141
 142 /*
 143  * Set options for the FPU emulator.
 144  */
 145 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 146 {
 147         c->options &= ~MIPS_CPU_FPU;
 148         c->fpu_msk31 = mips_nofpu_msk31;
 149
 150         cpu_set_nofpu_id(c);
 151 }
 152
 153 static int mips_fpu_disabled;
 154
 155 static int __init fpu_disable(char *s)
 156 {
 157         cpu_set_nofpu_opts(&boot_cpu_data);
 158         mips_fpu_disabled = 1;
 159
 160         return 1;
 161 }
 162
 163 __setup("nofpu", fpu_disable);
 164
 165 int mips_dsp_disabled;
 166
 167 static int __init dsp_disable(char *s)
 168 {
 169         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 170         mips_dsp_disabled = 1;
 171
 172         return 1;
 173 }
 174
 175 __setup("nodsp", dsp_disable);
 176
 177 static int mips_htw_disabled;
 178
 179 static int __init htw_disable(char *s)
 180 {
 181         mips_htw_disabled = 1;
 182         cpu_data[0].options &= ~MIPS_CPU_HTW;
 183         write_c0_pwctl(read_c0_pwctl() &
 184                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 185
 186         return 1;
 187 }
 188
 189 __setup("nohtw", htw_disable);
 190
 191 static int mips_ftlb_disabled;
 192 static int mips_has_ftlb_configured;
 193
 194 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable);
 195
 196 static int __init ftlb_disable(char *s)
 197 {
 198         unsigned int config4, mmuextdef;
 199
 200         /*
 201          * If the core hasn't done any FTLB configuration, there is nothing
 202          * for us to do here.
 203          */
 204         if (!mips_has_ftlb_configured)
 205                 return 1;
 206
 207         /* Disable it in the boot cpu */
 208         if (set_ftlb_enable(&cpu_data[0], 0)) {
 209                 pr_warn("Can't turn FTLB off\n");
 210                 return 1;
 211         }
 212
 213         back_to_back_c0_hazard();
 214
 215         config4 = read_c0_config4();
 216
 217         /* Check that FTLB has been disabled */
 218         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 219         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 220         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 221                 /* This should never happen */
 222                 pr_warn("FTLB could not be disabled!\n");
 223                 return 1;
 224         }
 225
 226         mips_ftlb_disabled = 1;
 227         mips_has_ftlb_configured = 0;
 228
 229         /*
 230          * noftlb is mainly used for debug purposes so print
 231          * an informative message instead of using pr_debug()
 232          */
 233         pr_info("FTLB has been disabled\n");
 234
 235         /*
 236          * Some of these bits are duplicated in the decode_config4.
 237          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 238          * once FTLB has been disabled so undo what decode_config4 did.
 239          */
 240         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 241                                cpu_data[0].tlbsizeftlbsets;
 242         cpu_data[0].tlbsizeftlbsets = 0;
 243         cpu_data[0].tlbsizeftlbways = 0;
 244
 245         return 1;
 246 }
 247
 248 __setup("noftlb", ftlb_disable);
 249
 250
 251 static inline void check_errata(void)
 252 {
 253         struct cpuinfo_mips *c = &current_cpu_data;
 254
 255         switch (current_cpu_type()) {
 256         case CPU_34K:
 257                 /*
 258                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 259                  * This code only handles VPE0, any SMP/RTOS code
 260                  * making use of VPE1 will be responsable for that VPE.
 261                  */
 262                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 263                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 264                 break;
 265         default:
 266                 break;
 267         }
 268 }
 269
 270 void __init check_bugs32(void)
 271 {
 272         check_errata();
 273 }
 274
 275 /*
 276  * Probe whether cpu has config register by trying to play with
 277  * alternate cache bit and see whether it matters.
 278  * It's used by cpu_probe to distinguish between R3000A and R3081.
 279  */
 280 static inline int cpu_has_confreg(void)
 281 {
 282 #ifdef CONFIG_CPU_R3000
 283         extern unsigned long r3k_cache_size(unsigned long);
 284         unsigned long size1, size2;
 285         unsigned long cfg = read_c0_conf();
 286
 287         size1 = r3k_cache_size(ST0_ISC);
 288         write_c0_conf(cfg ^ R30XX_CONF_AC);
 289         size2 = r3k_cache_size(ST0_ISC);
 290         write_c0_conf(cfg);
 291         return size1 != size2;
 292 #else
 293         return 0;
 294 #endif
 295 }
 296
 297 static inline void set_elf_platform(int cpu, const char *plat)
 298 {
 299         if (cpu == 0)
 300                 __elf_platform = plat;
 301 }
 302
 303 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 304 {
 305 #ifdef __NEED_VMBITS_PROBE
 306         write_c0_entryhi(0x3fffffffffffe000ULL);
 307         back_to_back_c0_hazard();
 308         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 309 #endif
 310 }
 311
 312 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 313 {
 314         switch (isa) {
 315         case MIPS_CPU_ISA_M64R2:
 316                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 317         case MIPS_CPU_ISA_M64R1:
 318                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 319         case MIPS_CPU_ISA_V:
 320                 c->isa_level |= MIPS_CPU_ISA_V;
 321         case MIPS_CPU_ISA_IV:
 322                 c->isa_level |= MIPS_CPU_ISA_IV;
 323         case MIPS_CPU_ISA_III:
 324                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 325                 break;
 326
 327         /* R6 incompatible with everything else */
 328         case MIPS_CPU_ISA_M64R6:
 329                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 330         case MIPS_CPU_ISA_M32R6:
 331                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 332                 /* Break here so we don't add incompatible ISAs */
 333                 break;
 334         case MIPS_CPU_ISA_M32R2:
 335                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 336         case MIPS_CPU_ISA_M32R1:
 337                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 338         case MIPS_CPU_ISA_II:
 339                 c->isa_level |= MIPS_CPU_ISA_II;
 340                 break;
 341         }
 342 }
 343
 344 static char unknown_isa[] = KERN_ERR \
 345         "Unsupported ISA type, c0.config0: %d.";
 346
 347 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 348 {
 349
 350         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 351
 352         /*
 353          * 0 = All TLBWR instructions go to FTLB
 354          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 355          * FTLB and 1 goes to the VTLB.
 356          * 2 = 7:1: As above with 7:1 ratio.
 357          * 3 = 3:1: As above with 3:1 ratio.
 358          *
 359          * Use the linear midpoint as the probability threshold.
 360          */
 361         if (probability >= 12)
 362                 return 1;
 363         else if (probability >= 6)
 364                 return 2;
 365         else
 366                 /*
 367                  * So FTLB is less than 4 times bigger than VTLB.
 368                  * A 3:1 ratio can still be useful though.
 369                  */
 370                 return 3;
 371 }
 372
 373 static int set_ftlb_enable(struct cpuinfo_mips *c, int enable)
 374 {
 375         unsigned int config;
 376
 377         /* It's implementation dependent how the FTLB can be enabled */
 378         switch (c->cputype) {
 379         case CPU_PROAPTIV:
 380         case CPU_P5600:
 381                 /* proAptiv & related cores use Config6 to enable the FTLB */
 382                 config = read_c0_config6();
 383                 /* Clear the old probability value */
 384                 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 385                 if (enable)
 386                         /* Enable FTLB */
 387                         write_c0_config6(config |
 388                                          (calculate_ftlb_probability(c)
 389                                           << MIPS_CONF6_FTLBP_SHIFT)
 390                                          | MIPS_CONF6_FTLBEN);
 391                 else
 392                         /* Disable FTLB */
 393                         write_c0_config6(config &  ~MIPS_CONF6_FTLBEN);
 394                 break;
 395         case CPU_I6400:
 396                 /* I6400 & related cores use Config7 to configure FTLB */
 397                 config = read_c0_config7();
 398                 /* Clear the old probability value */
 399                 config &= ~(3 << MIPS_CONF7_FTLBP_SHIFT);
 400                 write_c0_config7(config | (calculate_ftlb_probability(c)
 401                                            << MIPS_CONF7_FTLBP_SHIFT));
 402                 break;
 403         default:
 404                 return 1;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 411 {
 412         unsigned int config0;
 413         int isa, mt;
 414
 415         config0 = read_c0_config();
 416
 417         /*
 418          * Look for Standard TLB or Dual VTLB and FTLB
 419          */
 420         mt = config0 & MIPS_CONF_MT;
 421         if (mt == MIPS_CONF_MT_TLB)
 422                 c->options |= MIPS_CPU_TLB;
 423         else if (mt == MIPS_CONF_MT_FTLB)
 424                 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
 425
 426         isa = (config0 & MIPS_CONF_AT) >> 13;
 427         switch (isa) {
 428         case 0:
 429                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 430                 case 0:
 431                         set_isa(c, MIPS_CPU_ISA_M32R1);
 432                         break;
 433                 case 1:
 434                         set_isa(c, MIPS_CPU_ISA_M32R2);
 435                         break;
 436                 case 2:
 437                         set_isa(c, MIPS_CPU_ISA_M32R6);
 438                         break;
 439                 default:
 440                         goto unknown;
 441                 }
 442                 break;
 443         case 2:
 444                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 445                 case 0:
 446                         set_isa(c, MIPS_CPU_ISA_M64R1);
 447                         break;
 448                 case 1:
 449                         set_isa(c, MIPS_CPU_ISA_M64R2);
 450                         break;
 451                 case 2:
 452                         set_isa(c, MIPS_CPU_ISA_M64R6);
 453                         break;
 454                 default:
 455                         goto unknown;
 456                 }
 457                 break;
 458         default:
 459                 goto unknown;
 460         }
 461
 462         return config0 & MIPS_CONF_M;
 463
 464 unknown:
 465         panic(unknown_isa, config0);
 466 }
 467
 468 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 469 {
 470         unsigned int config1;
 471
 472         config1 = read_c0_config1();
 473
 474         if (config1 & MIPS_CONF1_MD)
 475                 c->ases |= MIPS_ASE_MDMX;
 476         if (config1 & MIPS_CONF1_WR)
 477                 c->options |= MIPS_CPU_WATCH;
 478         if (config1 & MIPS_CONF1_CA)
 479                 c->ases |= MIPS_ASE_MIPS16;
 480         if (config1 & MIPS_CONF1_EP)
 481                 c->options |= MIPS_CPU_EJTAG;
 482         if (config1 & MIPS_CONF1_FP) {
 483                 c->options |= MIPS_CPU_FPU;
 484                 c->options |= MIPS_CPU_32FPR;
 485         }
 486         if (cpu_has_tlb) {
 487                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 488                 c->tlbsizevtlb = c->tlbsize;
 489                 c->tlbsizeftlbsets = 0;
 490         }
 491
 492         return config1 & MIPS_CONF_M;
 493 }
 494
 495 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 496 {
 497         unsigned int config2;
 498
 499         config2 = read_c0_config2();
 500
 501         if (config2 & MIPS_CONF2_SL)
 502                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 503
 504         return config2 & MIPS_CONF_M;
 505 }
 506
 507 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 508 {
 509         unsigned int config3;
 510
 511         config3 = read_c0_config3();
 512
 513         if (config3 & MIPS_CONF3_SM) {
 514                 c->ases |= MIPS_ASE_SMARTMIPS;
 515                 c->options |= MIPS_CPU_RIXI;
 516         }
 517         if (config3 & MIPS_CONF3_RXI)
 518                 c->options |= MIPS_CPU_RIXI;
 519         if (config3 & MIPS_CONF3_DSP)
 520                 c->ases |= MIPS_ASE_DSP;
 521         if (config3 & MIPS_CONF3_DSP2P)
 522                 c->ases |= MIPS_ASE_DSP2P;
 523         if (config3 & MIPS_CONF3_VINT)
 524                 c->options |= MIPS_CPU_VINT;
 525         if (config3 & MIPS_CONF3_VEIC)
 526                 c->options |= MIPS_CPU_VEIC;
 527         if (config3 & MIPS_CONF3_MT)
 528                 c->ases |= MIPS_ASE_MIPSMT;
 529         if (config3 & MIPS_CONF3_ULRI)
 530                 c->options |= MIPS_CPU_ULRI;
 531         if (config3 & MIPS_CONF3_ISA)
 532                 c->options |= MIPS_CPU_MICROMIPS;
 533         if (config3 & MIPS_CONF3_VZ)
 534                 c->ases |= MIPS_ASE_VZ;
 535         if (config3 & MIPS_CONF3_SC)
 536                 c->options |= MIPS_CPU_SEGMENTS;
 537         if (config3 & MIPS_CONF3_MSA)
 538                 c->ases |= MIPS_ASE_MSA;
 539         /* Only tested on 32-bit cores */
 540         if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
 541                 c->htw_seq = 0;
 542                 c->options |= MIPS_CPU_HTW;
 543         }
 544         if (config3 & MIPS_CONF3_CDMM)
 545                 c->options |= MIPS_CPU_CDMM;
 546         if (config3 & MIPS_CONF3_SP)
 547                 c->options |= MIPS_CPU_SP;
 548
 549         return config3 & MIPS_CONF_M;
 550 }
 551
 552 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 553 {
 554         unsigned int config4;
 555         unsigned int newcf4;
 556         unsigned int mmuextdef;
 557         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 558
 559         config4 = read_c0_config4();
 560
 561         if (cpu_has_tlb) {
 562                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 563                         c->options |= MIPS_CPU_TLBINV;
 564                 /*
 565                  * This is a bit ugly. R6 has dropped that field from
 566                  * config4 and the only valid configuration is VTLB+FTLB so
 567                  * set a good value for mmuextdef for that case.
 568                  */
 569                 if (cpu_has_mips_r6)
 570                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 571                 else
 572                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 573
 574                 switch (mmuextdef) {
 575                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 576                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 577                         c->tlbsizevtlb = c->tlbsize;
 578                         break;
 579                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 580                         c->tlbsizevtlb +=
 581                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 582                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 583                         c->tlbsize = c->tlbsizevtlb;
 584                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 585                         /* fall through */
 586                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 587                         if (mips_ftlb_disabled)
 588                                 break;
 589                         newcf4 = (config4 & ~ftlb_page) |
 590                                 (page_size_ftlb(mmuextdef) <<
 591                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 592                         write_c0_config4(newcf4);
 593                         back_to_back_c0_hazard();
 594                         config4 = read_c0_config4();
 595                         if (config4 != newcf4) {
 596                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 597                                        PAGE_SIZE, config4);
 598                                 /* Switch FTLB off */
 599                                 set_ftlb_enable(c, 0);
 600                                 break;
 601                         }
 602                         c->tlbsizeftlbsets = 1 <<
 603                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 604                                  MIPS_CONF4_FTLBSETS_SHIFT);
 605                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 606                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 607                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 608                         mips_has_ftlb_configured = 1;
 609                         break;
 610                 }
 611         }
 612
 613         c->kscratch_mask = (config4 >> 16) & 0xff;
 614
 615         return config4 & MIPS_CONF_M;
 616 }
 617
 618 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 619 {
 620         unsigned int config5;
 621
 622         config5 = read_c0_config5();
 623         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 624         write_c0_config5(config5);
 625
 626         if (config5 & MIPS_CONF5_EVA)
 627                 c->options |= MIPS_CPU_EVA;
 628         if (config5 & MIPS_CONF5_MRP)
 629                 c->options |= MIPS_CPU_MAAR;
 630         if (config5 & MIPS_CONF5_LLB)
 631                 c->options |= MIPS_CPU_RW_LLB;
 632 #ifdef CONFIG_XPA
 633         if (config5 & MIPS_CONF5_MVH)
 634                 c->options |= MIPS_CPU_XPA;
 635 #endif
 636
 637         return config5 & MIPS_CONF_M;
 638 }
 639
 640 static void decode_configs(struct cpuinfo_mips *c)
 641 {
 642         int ok;
 643
 644         /* MIPS32 or MIPS64 compliant CPU.  */
 645         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 646                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 647
 648         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 649
 650         /* Enable FTLB if present and not disabled */
 651         set_ftlb_enable(c, !mips_ftlb_disabled);
 652
 653         ok = decode_config0(c);                 /* Read Config registers.  */
 654         BUG_ON(!ok);                            /* Arch spec violation!  */
 655         if (ok)
 656                 ok = decode_config1(c);
 657         if (ok)
 658                 ok = decode_config2(c);
 659         if (ok)
 660                 ok = decode_config3(c);
 661         if (ok)
 662                 ok = decode_config4(c);
 663         if (ok)
 664                 ok = decode_config5(c);
 665
 666         mips_probe_watch_registers(c);
 667
 668         if (cpu_has_rixi) {
 669                 /* Enable the RIXI exceptions */
 670                 set_c0_pagegrain(PG_IEC);
 671                 back_to_back_c0_hazard();
 672                 /* Verify the IEC bit is set */
 673                 if (read_c0_pagegrain() & PG_IEC)
 674                         c->options |= MIPS_CPU_RIXIEX;
 675         }
 676
 677 #ifndef CONFIG_MIPS_CPS
 678         if (cpu_has_mips_r2_r6) {
 679                 c->core = get_ebase_cpunum();
 680                 if (cpu_has_mipsmt)
 681                         c->core >>= fls(core_nvpes()) - 1;
 682         }
 683 #endif
 684 }
 685
 686 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 687                 | MIPS_CPU_COUNTER)
 688
 689 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 690 {
 691         switch (c->processor_id & PRID_IMP_MASK) {
 692         case PRID_IMP_R2000:
 693                 c->cputype = CPU_R2000;
 694                 __cpu_name[cpu] = "R2000";
 695                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 696                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 697                              MIPS_CPU_NOFPUEX;
 698                 if (__cpu_has_fpu())
 699                         c->options |= MIPS_CPU_FPU;
 700                 c->tlbsize = 64;
 701                 break;
 702         case PRID_IMP_R3000:
 703                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 704                         if (cpu_has_confreg()) {
 705                                 c->cputype = CPU_R3081E;
 706                                 __cpu_name[cpu] = "R3081";
 707                         } else {
 708                                 c->cputype = CPU_R3000A;
 709                                 __cpu_name[cpu] = "R3000A";
 710                         }
 711                 } else {
 712                         c->cputype = CPU_R3000;
 713                         __cpu_name[cpu] = "R3000";
 714                 }
 715                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 716                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 717                              MIPS_CPU_NOFPUEX;
 718                 if (__cpu_has_fpu())
 719                         c->options |= MIPS_CPU_FPU;
 720                 c->tlbsize = 64;
 721                 break;
 722         case PRID_IMP_R4000:
 723                 if (read_c0_config() & CONF_SC) {
 724                         if ((c->processor_id & PRID_REV_MASK) >=
 725                             PRID_REV_R4400) {
 726                                 c->cputype = CPU_R4400PC;
 727                                 __cpu_name[cpu] = "R4400PC";
 728                         } else {
 729                                 c->cputype = CPU_R4000PC;
 730                                 __cpu_name[cpu] = "R4000PC";
 731                         }
 732                 } else {
 733                         int cca = read_c0_config() & CONF_CM_CMASK;
 734                         int mc;
 735
 736                         /*
 737                          * SC and MC versions can't be reliably told apart,
 738                          * but only the latter support coherent caching
 739                          * modes so assume the firmware has set the KSEG0
 740                          * coherency attribute reasonably (if uncached, we
 741                          * assume SC).
 742                          */
 743                         switch (cca) {
 744                         case CONF_CM_CACHABLE_CE:
 745                         case CONF_CM_CACHABLE_COW:
 746                         case CONF_CM_CACHABLE_CUW:
 747                                 mc = 1;
 748                                 break;
 749                         default:
 750                                 mc = 0;
 751                                 break;
 752                         }
 753                         if ((c->processor_id & PRID_REV_MASK) >=
 754                             PRID_REV_R4400) {
 755                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
 756                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
 757                         } else {
 758                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
 759                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
 760                         }
 761                 }
 762
 763                 set_isa(c, MIPS_CPU_ISA_III);
 764                 c->fpu_msk31 |= FPU_CSR_CONDX;
 765                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 766                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 767                              MIPS_CPU_LLSC;
 768                 c->tlbsize = 48;
 769                 break;
 770         case PRID_IMP_VR41XX:
 771                 set_isa(c, MIPS_CPU_ISA_III);
 772                 c->fpu_msk31 |= FPU_CSR_CONDX;
 773                 c->options = R4K_OPTS;
 774                 c->tlbsize = 32;
 775                 switch (c->processor_id & 0xf0) {
 776                 case PRID_REV_VR4111:
 777                         c->cputype = CPU_VR4111;
 778                         __cpu_name[cpu] = "NEC VR4111";
 779                         break;
 780                 case PRID_REV_VR4121:
 781                         c->cputype = CPU_VR4121;
 782                         __cpu_name[cpu] = "NEC VR4121";
 783                         break;
 784                 case PRID_REV_VR4122:
 785                         if ((c->processor_id & 0xf) < 0x3) {
 786                                 c->cputype = CPU_VR4122;
 787                                 __cpu_name[cpu] = "NEC VR4122";
 788                         } else {
 789                                 c->cputype = CPU_VR4181A;
 790                                 __cpu_name[cpu] = "NEC VR4181A";
 791                         }
 792                         break;
 793                 case PRID_REV_VR4130:
 794                         if ((c->processor_id & 0xf) < 0x4) {
 795                                 c->cputype = CPU_VR4131;
 796                                 __cpu_name[cpu] = "NEC VR4131";
 797                         } else {
 798                                 c->cputype = CPU_VR4133;
 799                                 c->options |= MIPS_CPU_LLSC;
 800                                 __cpu_name[cpu] = "NEC VR4133";
 801                         }
 802                         break;
 803                 default:
 804                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 805                         c->cputype = CPU_VR41XX;
 806                         __cpu_name[cpu] = "NEC Vr41xx";
 807                         break;
 808                 }
 809                 break;
 810         case PRID_IMP_R4300:
 811                 c->cputype = CPU_R4300;
 812                 __cpu_name[cpu] = "R4300";
 813                 set_isa(c, MIPS_CPU_ISA_III);
 814                 c->fpu_msk31 |= FPU_CSR_CONDX;
 815                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 816                              MIPS_CPU_LLSC;
 817                 c->tlbsize = 32;
 818                 break;
 819         case PRID_IMP_R4600:
 820                 c->cputype = CPU_R4600;
 821                 __cpu_name[cpu] = "R4600";
 822                 set_isa(c, MIPS_CPU_ISA_III);
 823                 c->fpu_msk31 |= FPU_CSR_CONDX;
 824                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 825                              MIPS_CPU_LLSC;
 826                 c->tlbsize = 48;
 827                 break;
 828         #if 0
 829         case PRID_IMP_R4650:
 830                 /*
 831                  * This processor doesn't have an MMU, so it's not
 832                  * "real easy" to run Linux on it. It is left purely
 833                  * for documentation.  Commented out because it shares
 834                  * it's c0_prid id number with the TX3900.
 835                  */
 836                 c->cputype = CPU_R4650;
 837                 __cpu_name[cpu] = "R4650";
 838                 set_isa(c, MIPS_CPU_ISA_III);
 839                 c->fpu_msk31 |= FPU_CSR_CONDX;
 840                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 841                 c->tlbsize = 48;
 842                 break;
 843         #endif
 844         case PRID_IMP_TX39:
 845                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 846                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 847
 848                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 849                         c->cputype = CPU_TX3927;
 850                         __cpu_name[cpu] = "TX3927";
 851                         c->tlbsize = 64;
 852                 } else {
 853                         switch (c->processor_id & PRID_REV_MASK) {
 854                         case PRID_REV_TX3912:
 855                                 c->cputype = CPU_TX3912;
 856                                 __cpu_name[cpu] = "TX3912";
 857                                 c->tlbsize = 32;
 858                                 break;
 859                         case PRID_REV_TX3922:
 860                                 c->cputype = CPU_TX3922;
 861                                 __cpu_name[cpu] = "TX3922";
 862                                 c->tlbsize = 64;
 863                                 break;
 864                         }
 865                 }
 866                 break;
 867         case PRID_IMP_R4700:
 868                 c->cputype = CPU_R4700;
 869                 __cpu_name[cpu] = "R4700";
 870                 set_isa(c, MIPS_CPU_ISA_III);
 871                 c->fpu_msk31 |= FPU_CSR_CONDX;
 872                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 873                              MIPS_CPU_LLSC;
 874                 c->tlbsize = 48;
 875                 break;
 876         case PRID_IMP_TX49:
 877                 c->cputype = CPU_TX49XX;
 878                 __cpu_name[cpu] = "R49XX";
 879                 set_isa(c, MIPS_CPU_ISA_III);
 880                 c->fpu_msk31 |= FPU_CSR_CONDX;
 881                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 882                 if (!(c->processor_id & 0x08))
 883                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 884                 c->tlbsize = 48;
 885                 break;
 886         case PRID_IMP_R5000:
 887                 c->cputype = CPU_R5000;
 888                 __cpu_name[cpu] = "R5000";
 889                 set_isa(c, MIPS_CPU_ISA_IV);
 890                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 891                              MIPS_CPU_LLSC;
 892                 c->tlbsize = 48;
 893                 break;
 894         case PRID_IMP_R5432:
 895                 c->cputype = CPU_R5432;
 896                 __cpu_name[cpu] = "R5432";
 897                 set_isa(c, MIPS_CPU_ISA_IV);
 898                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 899                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 900                 c->tlbsize = 48;
 901                 break;
 902         case PRID_IMP_R5500:
 903                 c->cputype = CPU_R5500;
 904                 __cpu_name[cpu] = "R5500";
 905                 set_isa(c, MIPS_CPU_ISA_IV);
 906                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 907                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 908                 c->tlbsize = 48;
 909                 break;
 910         case PRID_IMP_NEVADA:
 911                 c->cputype = CPU_NEVADA;
 912                 __cpu_name[cpu] = "Nevada";
 913                 set_isa(c, MIPS_CPU_ISA_IV);
 914                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 915                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 916                 c->tlbsize = 48;
 917                 break;
 918         case PRID_IMP_R6000:
 919                 c->cputype = CPU_R6000;
 920                 __cpu_name[cpu] = "R6000";
 921                 set_isa(c, MIPS_CPU_ISA_II);
 922                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 923                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 924                              MIPS_CPU_LLSC;
 925                 c->tlbsize = 32;
 926                 break;
 927         case PRID_IMP_R6000A:
 928                 c->cputype = CPU_R6000A;
 929                 __cpu_name[cpu] = "R6000A";
 930                 set_isa(c, MIPS_CPU_ISA_II);
 931                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
 932                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 933                              MIPS_CPU_LLSC;
 934                 c->tlbsize = 32;
 935                 break;
 936         case PRID_IMP_RM7000:
 937                 c->cputype = CPU_RM7000;
 938                 __cpu_name[cpu] = "RM7000";
 939                 set_isa(c, MIPS_CPU_ISA_IV);
 940                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 941                              MIPS_CPU_LLSC;
 942                 /*
 943                  * Undocumented RM7000:  Bit 29 in the info register of
 944                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 945                  * entries.
 946                  *
 947                  * 29      1 =>    64 entry JTLB
 948                  *         0 =>    48 entry JTLB
 949                  */
 950                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 951                 break;
 952         case PRID_IMP_R8000:
 953                 c->cputype = CPU_R8000;
 954                 __cpu_name[cpu] = "RM8000";
 955                 set_isa(c, MIPS_CPU_ISA_IV);
 956                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 957                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 958                              MIPS_CPU_LLSC;
 959                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 960                 break;
 961         case PRID_IMP_R10000:
 962                 c->cputype = CPU_R10000;
 963                 __cpu_name[cpu] = "R10000";
 964                 set_isa(c, MIPS_CPU_ISA_IV);
 965                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 966                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 967                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 968                              MIPS_CPU_LLSC;
 969                 c->tlbsize = 64;
 970                 break;
 971         case PRID_IMP_R12000:
 972                 c->cputype = CPU_R12000;
 973                 __cpu_name[cpu] = "R12000";
 974                 set_isa(c, MIPS_CPU_ISA_IV);
 975                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 976                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 977                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 978                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
 979                 c->tlbsize = 64;
 980                 break;
 981         case PRID_IMP_R14000:
 982                 if (((c->processor_id >> 4) & 0x0f) > 2) {
 983                         c->cputype = CPU_R16000;
 984                         __cpu_name[cpu] = "R16000";
 985                 } else {
 986                         c->cputype = CPU_R14000;
 987                         __cpu_name[cpu] = "R14000";
 988                 }
 989                 set_isa(c, MIPS_CPU_ISA_IV);
 990                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 991                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 992                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 993                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
 994                 c->tlbsize = 64;
 995                 break;
 996         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
 997                 switch (c->processor_id & PRID_REV_MASK) {
 998                 case PRID_REV_LOONGSON2E:
 999                         c->cputype = CPU_LOONGSON2;
1000                         __cpu_name[cpu] = "ICT Loongson-2";
1001                         set_elf_platform(cpu, "loongson2e");
1002                         set_isa(c, MIPS_CPU_ISA_III);
1003                         c->fpu_msk31 |= FPU_CSR_CONDX;
1004                         break;
1005                 case PRID_REV_LOONGSON2F:
1006                         c->cputype = CPU_LOONGSON2;
1007                         __cpu_name[cpu] = "ICT Loongson-2";
1008                         set_elf_platform(cpu, "loongson2f");
1009                         set_isa(c, MIPS_CPU_ISA_III);
1010                         c->fpu_msk31 |= FPU_CSR_CONDX;
1011                         break;
1012                 case PRID_REV_LOONGSON3A:
1013                         c->cputype = CPU_LOONGSON3;
1014                         __cpu_name[cpu] = "ICT Loongson-3";
1015                         set_elf_platform(cpu, "loongson3a");
1016                         set_isa(c, MIPS_CPU_ISA_M64R1);
1017                         break;
1018                 case PRID_REV_LOONGSON3B_R1:
1019                 case PRID_REV_LOONGSON3B_R2:
1020                         c->cputype = CPU_LOONGSON3;
1021                         __cpu_name[cpu] = "ICT Loongson-3";
1022                         set_elf_platform(cpu, "loongson3b");
1023                         set_isa(c, MIPS_CPU_ISA_M64R1);
1024                         break;
1025                 }
1026
1027                 c->options = R4K_OPTS |
1028                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1029                              MIPS_CPU_32FPR;
1030                 c->tlbsize = 64;
1031                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1032                 break;
1033         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1034                 decode_configs(c);
1035
1036                 c->cputype = CPU_LOONGSON1;
1037
1038                 switch (c->processor_id & PRID_REV_MASK) {
1039                 case PRID_REV_LOONGSON1B:
1040                         __cpu_name[cpu] = "Loongson 1B";
1041                         break;
1042                 }
1043
1044                 break;
1045         }
1046 }
1047
1048 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1049 {
1050         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1051         switch (c->processor_id & PRID_IMP_MASK) {
1052         case PRID_IMP_QEMU_GENERIC:
1053                 c->writecombine = _CACHE_UNCACHED;
1054                 c->cputype = CPU_QEMU_GENERIC;
1055                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1056                 break;
1057         case PRID_IMP_4KC:
1058                 c->cputype = CPU_4KC;
1059                 c->writecombine = _CACHE_UNCACHED;
1060                 __cpu_name[cpu] = "MIPS 4Kc";
1061                 break;
1062         case PRID_IMP_4KEC:
1063         case PRID_IMP_4KECR2:
1064                 c->cputype = CPU_4KEC;
1065                 c->writecombine = _CACHE_UNCACHED;
1066                 __cpu_name[cpu] = "MIPS 4KEc";
1067                 break;
1068         case PRID_IMP_4KSC:
1069         case PRID_IMP_4KSD:
1070                 c->cputype = CPU_4KSC;
1071                 c->writecombine = _CACHE_UNCACHED;
1072                 __cpu_name[cpu] = "MIPS 4KSc";
1073                 break;
1074         case PRID_IMP_5KC:
1075                 c->cputype = CPU_5KC;
1076                 c->writecombine = _CACHE_UNCACHED;
1077                 __cpu_name[cpu] = "MIPS 5Kc";
1078                 break;
1079         case PRID_IMP_5KE:
1080                 c->cputype = CPU_5KE;
1081                 c->writecombine = _CACHE_UNCACHED;
1082                 __cpu_name[cpu] = "MIPS 5KE";
1083                 break;
1084         case PRID_IMP_20KC:
1085                 c->cputype = CPU_20KC;
1086                 c->writecombine = _CACHE_UNCACHED;
1087                 __cpu_name[cpu] = "MIPS 20Kc";
1088                 break;
1089         case PRID_IMP_24K:
1090                 c->cputype = CPU_24K;
1091                 c->writecombine = _CACHE_UNCACHED;
1092                 __cpu_name[cpu] = "MIPS 24Kc";
1093                 break;
1094         case PRID_IMP_24KE:
1095                 c->cputype = CPU_24K;
1096                 c->writecombine = _CACHE_UNCACHED;
1097                 __cpu_name[cpu] = "MIPS 24KEc";
1098                 break;
1099         case PRID_IMP_25KF:
1100                 c->cputype = CPU_25KF;
1101                 c->writecombine = _CACHE_UNCACHED;
1102                 __cpu_name[cpu] = "MIPS 25Kc";
1103                 break;
1104         case PRID_IMP_34K:
1105                 c->cputype = CPU_34K;
1106                 c->writecombine = _CACHE_UNCACHED;
1107                 __cpu_name[cpu] = "MIPS 34Kc";
1108                 break;
1109         case PRID_IMP_74K:
1110                 c->cputype = CPU_74K;
1111                 c->writecombine = _CACHE_UNCACHED;
1112                 __cpu_name[cpu] = "MIPS 74Kc";
1113                 break;
1114         case PRID_IMP_M14KC:
1115                 c->cputype = CPU_M14KC;
1116                 c->writecombine = _CACHE_UNCACHED;
1117                 __cpu_name[cpu] = "MIPS M14Kc";
1118                 break;
1119         case PRID_IMP_M14KEC:
1120                 c->cputype = CPU_M14KEC;
1121                 c->writecombine = _CACHE_UNCACHED;
1122                 __cpu_name[cpu] = "MIPS M14KEc";
1123                 break;
1124         case PRID_IMP_1004K:
1125                 c->cputype = CPU_1004K;
1126                 c->writecombine = _CACHE_UNCACHED;
1127                 __cpu_name[cpu] = "MIPS 1004Kc";
1128                 break;
1129         case PRID_IMP_1074K:
1130                 c->cputype = CPU_1074K;
1131                 c->writecombine = _CACHE_UNCACHED;
1132                 __cpu_name[cpu] = "MIPS 1074Kc";
1133                 break;
1134         case PRID_IMP_INTERAPTIV_UP:
1135                 c->cputype = CPU_INTERAPTIV;
1136                 __cpu_name[cpu] = "MIPS interAptiv";
1137                 break;
1138         case PRID_IMP_INTERAPTIV_MP:
1139                 c->cputype = CPU_INTERAPTIV;
1140                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1141                 break;
1142         case PRID_IMP_PROAPTIV_UP:
1143                 c->cputype = CPU_PROAPTIV;
1144                 __cpu_name[cpu] = "MIPS proAptiv";
1145                 break;
1146         case PRID_IMP_PROAPTIV_MP:
1147                 c->cputype = CPU_PROAPTIV;
1148                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1149                 break;
1150         case PRID_IMP_P5600:
1151                 c->cputype = CPU_P5600;
1152                 __cpu_name[cpu] = "MIPS P5600";
1153                 break;
1154         case PRID_IMP_I6400:
1155                 c->cputype = CPU_I6400;
1156                 __cpu_name[cpu] = "MIPS I6400";
1157                 break;
1158         case PRID_IMP_M5150:
1159                 c->cputype = CPU_M5150;
1160                 __cpu_name[cpu] = "MIPS M5150";
1161                 break;
1162         }
1163
1164         decode_configs(c);
1165
1166         spram_config();
1167 }
1168
1169 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1170 {
1171         decode_configs(c);
1172         switch (c->processor_id & PRID_IMP_MASK) {
1173         case PRID_IMP_AU1_REV1:
1174         case PRID_IMP_AU1_REV2:
1175                 c->cputype = CPU_ALCHEMY;
1176                 switch ((c->processor_id >> 24) & 0xff) {
1177                 case 0:
1178                         __cpu_name[cpu] = "Au1000";
1179                         break;
1180                 case 1:
1181                         __cpu_name[cpu] = "Au1500";
1182                         break;
1183                 case 2:
1184                         __cpu_name[cpu] = "Au1100";
1185                         break;
1186                 case 3:
1187                         __cpu_name[cpu] = "Au1550";
1188                         break;
1189                 case 4:
1190                         __cpu_name[cpu] = "Au1200";
1191                         if ((c->processor_id & PRID_REV_MASK) == 2)
1192                                 __cpu_name[cpu] = "Au1250";
1193                         break;
1194                 case 5:
1195                         __cpu_name[cpu] = "Au1210";
1196                         break;
1197                 default:
1198                         __cpu_name[cpu] = "Au1xxx";
1199                         break;
1200                 }
1201                 break;
1202         }
1203 }
1204
1205 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1206 {
1207         decode_configs(c);
1208
1209         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1210         switch (c->processor_id & PRID_IMP_MASK) {
1211         case PRID_IMP_SB1:
1212                 c->cputype = CPU_SB1;
1213                 __cpu_name[cpu] = "SiByte SB1";
1214                 /* FPU in pass1 is known to have issues. */
1215                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1216                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1217                 break;
1218         case PRID_IMP_SB1A:
1219                 c->cputype = CPU_SB1A;
1220                 __cpu_name[cpu] = "SiByte SB1A";
1221                 break;
1222         }
1223 }
1224
1225 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1226 {
1227         decode_configs(c);
1228         switch (c->processor_id & PRID_IMP_MASK) {
1229         case PRID_IMP_SR71000:
1230                 c->cputype = CPU_SR71000;
1231                 __cpu_name[cpu] = "Sandcraft SR71000";
1232                 c->scache.ways = 8;
1233                 c->tlbsize = 64;
1234                 break;
1235         }
1236 }
1237
1238 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1239 {
1240         decode_configs(c);
1241         switch (c->processor_id & PRID_IMP_MASK) {
1242         case PRID_IMP_PR4450:
1243                 c->cputype = CPU_PR4450;
1244                 __cpu_name[cpu] = "Philips PR4450";
1245                 set_isa(c, MIPS_CPU_ISA_M32R1);
1246                 break;
1247         }
1248 }
1249
1250 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1251 {
1252         decode_configs(c);
1253         switch (c->processor_id & PRID_IMP_MASK) {
1254         case PRID_IMP_BMIPS32_REV4:
1255         case PRID_IMP_BMIPS32_REV8:
1256                 c->cputype = CPU_BMIPS32;
1257                 __cpu_name[cpu] = "Broadcom BMIPS32";
1258                 set_elf_platform(cpu, "bmips32");
1259                 break;
1260         case PRID_IMP_BMIPS3300:
1261         case PRID_IMP_BMIPS3300_ALT:
1262         case PRID_IMP_BMIPS3300_BUG:
1263                 c->cputype = CPU_BMIPS3300;
1264                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1265                 set_elf_platform(cpu, "bmips3300");
1266                 break;
1267         case PRID_IMP_BMIPS43XX: {
1268                 int rev = c->processor_id & PRID_REV_MASK;
1269
1270                 if (rev >= PRID_REV_BMIPS4380_LO &&
1271                                 rev <= PRID_REV_BMIPS4380_HI) {
1272                         c->cputype = CPU_BMIPS4380;
1273                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1274                         set_elf_platform(cpu, "bmips4380");
1275                 } else {
1276                         c->cputype = CPU_BMIPS4350;
1277                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1278                         set_elf_platform(cpu, "bmips4350");
1279                 }
1280                 break;
1281         }
1282         case PRID_IMP_BMIPS5000:
1283         case PRID_IMP_BMIPS5200:
1284                 c->cputype = CPU_BMIPS5000;
1285                 __cpu_name[cpu] = "Broadcom BMIPS5000";
1286                 set_elf_platform(cpu, "bmips5000");
1287                 c->options |= MIPS_CPU_ULRI;
1288                 break;
1289         }
1290 }
1291
1292 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1293 {
1294         decode_configs(c);
1295         switch (c->processor_id & PRID_IMP_MASK) {
1296         case PRID_IMP_CAVIUM_CN38XX:
1297         case PRID_IMP_CAVIUM_CN31XX:
1298         case PRID_IMP_CAVIUM_CN30XX:
1299                 c->cputype = CPU_CAVIUM_OCTEON;
1300                 __cpu_name[cpu] = "Cavium Octeon";
1301                 goto platform;
1302         case PRID_IMP_CAVIUM_CN58XX:
1303         case PRID_IMP_CAVIUM_CN56XX:
1304         case PRID_IMP_CAVIUM_CN50XX:
1305         case PRID_IMP_CAVIUM_CN52XX:
1306                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1307                 __cpu_name[cpu] = "Cavium Octeon+";
1308 platform:
1309                 set_elf_platform(cpu, "octeon");
1310                 break;
1311         case PRID_IMP_CAVIUM_CN61XX:
1312         case PRID_IMP_CAVIUM_CN63XX:
1313         case PRID_IMP_CAVIUM_CN66XX:
1314         case PRID_IMP_CAVIUM_CN68XX:
1315         case PRID_IMP_CAVIUM_CNF71XX:
1316                 c->cputype = CPU_CAVIUM_OCTEON2;
1317                 __cpu_name[cpu] = "Cavium Octeon II";
1318                 set_elf_platform(cpu, "octeon2");
1319                 break;
1320         case PRID_IMP_CAVIUM_CN70XX:
1321         case PRID_IMP_CAVIUM_CN78XX:
1322                 c->cputype = CPU_CAVIUM_OCTEON3;
1323                 __cpu_name[cpu] = "Cavium Octeon III";
1324                 set_elf_platform(cpu, "octeon3");
1325                 break;
1326         default:
1327                 printk(KERN_INFO "Unknown Octeon chip!\n");
1328                 c->cputype = CPU_UNKNOWN;
1329                 break;
1330         }
1331 }
1332
1333 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1334 {
1335         decode_configs(c);
1336         /* JZRISC does not implement the CP0 counter. */
1337         c->options &= ~MIPS_CPU_COUNTER;
1338         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1339         switch (c->processor_id & PRID_IMP_MASK) {
1340         case PRID_IMP_JZRISC:
1341                 c->cputype = CPU_JZRISC;
1342                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1343                 __cpu_name[cpu] = "Ingenic JZRISC";
1344                 break;
1345         default:
1346                 panic("Unknown Ingenic Processor ID!");
1347                 break;
1348         }
1349 }
1350
1351 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1352 {
1353         decode_configs(c);
1354
1355         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1356                 c->cputype = CPU_ALCHEMY;
1357                 __cpu_name[cpu] = "Au1300";
1358                 /* following stuff is not for Alchemy */
1359                 return;
1360         }
1361
1362         c->options = (MIPS_CPU_TLB       |
1363                         MIPS_CPU_4KEX    |
1364                         MIPS_CPU_COUNTER |
1365                         MIPS_CPU_DIVEC   |
1366                         MIPS_CPU_WATCH   |
1367                         MIPS_CPU_EJTAG   |
1368                         MIPS_CPU_LLSC);
1369
1370         switch (c->processor_id & PRID_IMP_MASK) {
1371         case PRID_IMP_NETLOGIC_XLP2XX:
1372         case PRID_IMP_NETLOGIC_XLP9XX:
1373         case PRID_IMP_NETLOGIC_XLP5XX:
1374                 c->cputype = CPU_XLP;
1375                 __cpu_name[cpu] = "Broadcom XLPII";
1376                 break;
1377
1378         case PRID_IMP_NETLOGIC_XLP8XX:
1379         case PRID_IMP_NETLOGIC_XLP3XX:
1380                 c->cputype = CPU_XLP;
1381                 __cpu_name[cpu] = "Netlogic XLP";
1382                 break;
1383
1384         case PRID_IMP_NETLOGIC_XLR732:
1385         case PRID_IMP_NETLOGIC_XLR716:
1386         case PRID_IMP_NETLOGIC_XLR532:
1387         case PRID_IMP_NETLOGIC_XLR308:
1388         case PRID_IMP_NETLOGIC_XLR532C:
1389         case PRID_IMP_NETLOGIC_XLR516C:
1390         case PRID_IMP_NETLOGIC_XLR508C:
1391         case PRID_IMP_NETLOGIC_XLR308C:
1392                 c->cputype = CPU_XLR;
1393                 __cpu_name[cpu] = "Netlogic XLR";
1394                 break;
1395
1396         case PRID_IMP_NETLOGIC_XLS608:
1397         case PRID_IMP_NETLOGIC_XLS408:
1398         case PRID_IMP_NETLOGIC_XLS404:
1399         case PRID_IMP_NETLOGIC_XLS208:
1400         case PRID_IMP_NETLOGIC_XLS204:
1401         case PRID_IMP_NETLOGIC_XLS108:
1402         case PRID_IMP_NETLOGIC_XLS104:
1403         case PRID_IMP_NETLOGIC_XLS616B:
1404         case PRID_IMP_NETLOGIC_XLS608B:
1405         case PRID_IMP_NETLOGIC_XLS416B:
1406         case PRID_IMP_NETLOGIC_XLS412B:
1407         case PRID_IMP_NETLOGIC_XLS408B:
1408         case PRID_IMP_NETLOGIC_XLS404B:
1409                 c->cputype = CPU_XLR;
1410                 __cpu_name[cpu] = "Netlogic XLS";
1411                 break;
1412
1413         default:
1414                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1415                        c->processor_id);
1416                 c->cputype = CPU_XLR;
1417                 break;
1418         }
1419
1420         if (c->cputype == CPU_XLP) {
1421                 set_isa(c, MIPS_CPU_ISA_M64R2);
1422                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1423                 /* This will be updated again after all threads are woken up */
1424                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1425         } else {
1426                 set_isa(c, MIPS_CPU_ISA_M64R1);
1427                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1428         }
1429         c->kscratch_mask = 0xf;
1430 }
1431
1432 #ifdef CONFIG_64BIT
1433 /* For use by uaccess.h */
1434 u64 __ua_limit;
1435 EXPORT_SYMBOL(__ua_limit);
1436 #endif
1437
1438 const char *__cpu_name[NR_CPUS];
1439 const char *__elf_platform;
1440
1441 void cpu_probe(void)
1442 {
1443         struct cpuinfo_mips *c = &current_cpu_data;
1444         unsigned int cpu = smp_processor_id();
1445
1446         c->processor_id = PRID_IMP_UNKNOWN;
1447         c->fpu_id       = FPIR_IMP_NONE;
1448         c->cputype      = CPU_UNKNOWN;
1449         c->writecombine = _CACHE_UNCACHED;
1450
1451         c->fpu_csr31    = FPU_CSR_RN;
1452         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1453
1454         c->processor_id = read_c0_prid();
1455         switch (c->processor_id & PRID_COMP_MASK) {
1456         case PRID_COMP_LEGACY:
1457                 cpu_probe_legacy(c, cpu);
1458                 break;
1459         case PRID_COMP_MIPS:
1460                 cpu_probe_mips(c, cpu);
1461                 break;
1462         case PRID_COMP_ALCHEMY:
1463                 cpu_probe_alchemy(c, cpu);
1464                 break;
1465         case PRID_COMP_SIBYTE:
1466                 cpu_probe_sibyte(c, cpu);
1467                 break;
1468         case PRID_COMP_BROADCOM:
1469                 cpu_probe_broadcom(c, cpu);
1470                 break;
1471         case PRID_COMP_SANDCRAFT:
1472                 cpu_probe_sandcraft(c, cpu);
1473                 break;
1474         case PRID_COMP_NXP:
1475                 cpu_probe_nxp(c, cpu);
1476                 break;
1477         case PRID_COMP_CAVIUM:
1478                 cpu_probe_cavium(c, cpu);
1479                 break;
1480         case PRID_COMP_INGENIC_D0:
1481         case PRID_COMP_INGENIC_D1:
1482         case PRID_COMP_INGENIC_E1:
1483                 cpu_probe_ingenic(c, cpu);
1484                 break;
1485         case PRID_COMP_NETLOGIC:
1486                 cpu_probe_netlogic(c, cpu);
1487                 break;
1488         }
1489
1490         BUG_ON(!__cpu_name[cpu]);
1491         BUG_ON(c->cputype == CPU_UNKNOWN);
1492
1493         /*
1494          * Platform code can force the cpu type to optimize code
1495          * generation. In that case be sure the cpu type is correctly
1496          * manually setup otherwise it could trigger some nasty bugs.
1497          */
1498         BUG_ON(current_cpu_type() != c->cputype);
1499
1500         if (mips_fpu_disabled)
1501                 c->options &= ~MIPS_CPU_FPU;
1502
1503         if (mips_dsp_disabled)
1504                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1505
1506         if (mips_htw_disabled) {
1507                 c->options &= ~MIPS_CPU_HTW;
1508                 write_c0_pwctl(read_c0_pwctl() &
1509                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1510         }
1511
1512         if (c->options & MIPS_CPU_FPU)
1513                 cpu_set_fpu_opts(c);
1514         else
1515                 cpu_set_nofpu_opts(c);
1516
1517         if (cpu_has_bp_ghist)
1518                 write_c0_r10k_diag(read_c0_r10k_diag() |
1519                                    R10K_DIAG_E_GHIST);
1520
1521         if (cpu_has_mips_r2_r6) {
1522                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1523                 /* R2 has Performance Counter Interrupt indicator */
1524                 c->options |= MIPS_CPU_PCI;
1525         }
1526         else
1527                 c->srsets = 1;
1528
1529         if (cpu_has_mips_r6)
1530                 elf_hwcap |= HWCAP_MIPS_R6;
1531
1532         if (cpu_has_msa) {
1533                 c->msa_id = cpu_get_msa_id();
1534                 WARN(c->msa_id & MSA_IR_WRPF,
1535                      "Vector register partitioning unimplemented!");
1536                 elf_hwcap |= HWCAP_MIPS_MSA;
1537         }
1538
1539         cpu_probe_vmbits(c);
1540
1541 #ifdef CONFIG_64BIT
1542         if (cpu == 0)
1543                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1544 #endif
1545 }
1546
1547 void cpu_report(void)
1548 {
1549         struct cpuinfo_mips *c = &current_cpu_data;
1550
1551         pr_info("CPU%d revision is: %08x (%s)\n",
1552                 smp_processor_id(), c->processor_id, cpu_name_string());
1553         if (c->options & MIPS_CPU_FPU)
1554                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1555         if (cpu_has_msa)
1556                 pr_info("MSA revision is: %08x\n", c->msa_id);
1557 }