2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
8 * Reset/NMI/re-entry vectors for BMIPS processors
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
17 #include <asm/regdef.h>
18 #include <asm/mipsregs.h>
19 #include <asm/stackframe.h>
20 #include <asm/addrspace.h>
21 #include <asm/hazards.h>
22 #include <asm/bmips.h>
32 /***********************************************************************
33 * Alternate CPU1 startup vector for BMIPS4350
35 * On some systems the bootloader has already started CPU1 and configured
36 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
37 * triggered by the SW1 interrupt. If that is the case we try to move
38 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
39 ***********************************************************************/
41 LEAF(bmips_smp_movevec)
48 /* clear IV, pending IPIs */
51 /* re-enable IRQs to wait for SW1 */
52 li k0, ST0_IE | ST0_BEV | STATUSF_IP1
55 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
58 /* set up relocation vector address based on thread ID */
62 or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
67 /* wait here for SW1 interrupt from bmips_boot_secondary() */
70 la k0, bmips_reset_nmi_vec
74 END(bmips_smp_movevec)
76 /***********************************************************************
78 * For BMIPS processors that can relocate their exception vectors, this
79 * entire function gets copied to 0x8000_0000.
80 ***********************************************************************/
82 NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
88 /* if the NMI bit is clear, assume this is a CPU1 reset instead */
92 beqz k0, bmips_smp_entry
94 #if defined(CONFIG_CPU_BMIPS5000)
96 li k1, PRID_IMP_BMIPS5000
100 /* if we're not on core 0, this must be the SMP boot signal */
104 bnez k0, bmips_smp_entry
106 #endif /* CONFIG_CPU_BMIPS5000 */
107 #endif /* CONFIG_SMP */
109 /* nope, it's just a regular NMI */
113 /* clear EXL, ERL, BEV so that TLB refills still work */
115 li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
121 /* jump to the NMI handler function */
129 /***********************************************************************
130 * CPU1 reset vector (used for the initial boot only)
131 * This is still part of bmips_reset_nmi_vec().
132 ***********************************************************************/
138 /* set up CP0 STATUS; enable FPU */
143 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
151 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
152 li k1, PRID_IMP_BMIPS43XX
155 /* initialize CPU1's local I-cache */
162 1: cache Index_Store_Tag_I, 0(k0)
168 #endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
169 #if defined(CONFIG_CPU_BMIPS5000)
170 /* set exception vector base */
171 li k1, PRID_IMP_BMIPS5000
178 #endif /* CONFIG_CPU_BMIPS5000 */
180 /* jump back to kseg0 in case we need to remap the kseg1 area */
184 la k0, bmips_enable_xks01
187 /* use temporary stack to set up upper memory TLB */
188 li sp, BMIPS_WARM_RESTART_VEC
189 la k0, plat_wired_tlb_setup
192 /* switch to permanent stack and continue booting */
194 .global bmips_secondary_reentry
195 bmips_secondary_reentry:
196 la k0, bmips_smp_boot_sp
198 la k0, bmips_smp_boot_gp
200 la k0, start_secondary
203 #endif /* CONFIG_SMP */
206 .global bmips_reset_nmi_vec_end
207 bmips_reset_nmi_vec_end:
209 END(bmips_reset_nmi_vec)
214 /***********************************************************************
215 * CPU1 warm restart vector (used for second and subsequent boots).
216 * Also used for S2 standby recovery (PM).
217 * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
218 ***********************************************************************/
220 LEAF(bmips_smp_int_vec)
230 .global bmips_smp_int_vec_end
231 bmips_smp_int_vec_end:
233 END(bmips_smp_int_vec)
235 /***********************************************************************
237 * Certain CPUs support extending kseg0 to 1024MB.
238 ***********************************************************************/
240 LEAF(bmips_enable_xks01)
242 #if defined(CONFIG_XKS01)
245 #if defined(CONFIG_CPU_BMIPS4380)
246 li t1, PRID_IMP_BMIPS43XX
250 addiu t1, t0, -PRID_REV_BMIPS4380_HI
252 addiu t0, -PRID_REV_BMIPS4380_LO
257 li t2, (1 << 12) | (1 << 9)
265 #endif /* CONFIG_CPU_BMIPS4380 */
266 #if defined(CONFIG_CPU_BMIPS5000)
267 li t1, PRID_IMP_BMIPS5000
272 li t2, (1 << 8) | (1 << 5)
278 #endif /* CONFIG_CPU_BMIPS5000 */
280 #endif /* defined(CONFIG_XKS01) */
284 END(bmips_enable_xks01)