2 * Format of an instruction in memory.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2014 Imagination Technologies Ltd.
13 #ifndef _UAPI_ASM_INST_H
14 #define _UAPI_ASM_INST_H
16 #include <asm/bitfield.h>
19 * Major opcodes; before MIPS IV cop1x was called cop3.
22 spec_op, bcond_op, j_op, jal_op,
23 beq_op, bne_op, blez_op, bgtz_op,
24 addi_op, cbcond0_op = addi_op, addiu_op, slti_op, sltiu_op,
25 andi_op, ori_op, xori_op, lui_op,
26 cop0_op, cop1_op, cop2_op, cop1x_op,
27 beql_op, bnel_op, blezl_op, bgtzl_op,
28 daddi_op, cbcond1_op = daddi_op, daddiu_op, ldl_op, ldr_op,
29 spec2_op, jalx_op, mdmx_op, msa_op = mdmx_op, spec3_op,
30 lb_op, lh_op, lwl_op, lw_op,
31 lbu_op, lhu_op, lwr_op, lwu_op,
32 sb_op, sh_op, swl_op, sw_op,
33 sdl_op, sdr_op, swr_op, cache_op,
34 ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
35 lld_op, ldc1_op, ldc2_op, beqzcjic_op = ldc2_op, ld_op,
36 sc_op, swc1_op, swc2_op, balc6_op = swc2_op, major_3b_op,
37 scd_op, sdc1_op, sdc2_op, bnezcjialc_op = sdc2_op, sd_op
41 * func field of spec opcode.
44 sll_op, movc_op, srl_op, sra_op,
45 sllv_op, pmon_op, srlv_op, srav_op,
46 jr_op, jalr_op, movz_op, movn_op,
47 syscall_op, break_op, spim_op, sync_op,
48 mfhi_op, mthi_op, mflo_op, mtlo_op,
49 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
50 mult_op, multu_op, div_op, divu_op,
51 dmult_op, dmultu_op, ddiv_op, ddivu_op,
52 add_op, addu_op, sub_op, subu_op,
53 and_op, or_op, xor_op, nor_op,
54 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
55 dadd_op, daddu_op, dsub_op, dsubu_op,
56 tge_op, tgeu_op, tlt_op, tltu_op,
57 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
58 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
59 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
63 * func field of spec2 opcode.
66 madd_op, maddu_op, mul_op, spec2_3_unused_op,
67 msub_op, msubu_op, /* more unused ops */
68 clz_op = 0x20, clo_op,
69 dclz_op = 0x24, dclo_op,
74 * func field of spec3 opcode.
77 ext_op, dextm_op, dextu_op, dext_op,
78 ins_op, dinsm_op, dinsu_op, dins_op,
79 yield_op = 0x09, lx_op = 0x0a,
80 lwle_op = 0x19, lwre_op = 0x1a,
81 cachee_op = 0x1b, sbe_op = 0x1c,
82 she_op = 0x1d, sce_op = 0x1e,
83 swe_op = 0x1f, bshfl_op = 0x20,
84 swle_op = 0x21, swre_op = 0x22,
85 prefe_op = 0x23, dbshfl_op = 0x24,
86 cache6_op = 0x25, sc6_op = 0x26,
87 scd6_op = 0x27, lbue_op = 0x28,
88 lhue_op = 0x29, lbe_op = 0x2c,
89 lhe_op = 0x2d, lle_op = 0x2e,
90 lwe_op = 0x2f, pref6_op = 0x35,
91 ll6_op = 0x36, lld6_op = 0x37,
96 * rt field of bcond opcodes.
99 bltz_op, bgez_op, bltzl_op, bgezl_op,
100 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
101 tgei_op, tgeiu_op, tlti_op, tltiu_op,
102 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
103 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
104 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
105 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
106 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
110 * rs field of cop opcodes.
113 mfc_op = 0x00, dmfc_op = 0x01,
114 cfc_op = 0x02, mfhc0_op = 0x02,
115 mfhc_op = 0x03, mtc_op = 0x04,
116 dmtc_op = 0x05, ctc_op = 0x06,
117 mthc0_op = 0x06, mthc_op = 0x07,
118 bc_op = 0x08, bc1eqz_op = 0x09,
119 mfmc0_op = 0x0b, bc1nez_op = 0x0d,
120 wrpgpr_op = 0x0e, cop_op = 0x10,
125 * rt field of cop.bc_op opcodes
128 bcf_op, bct_op, bcfl_op, bctl_op
132 * func field of cop0 coi opcodes.
135 tlbr_op = 0x01, tlbwi_op = 0x02,
136 tlbwr_op = 0x06, tlbp_op = 0x08,
137 rfe_op = 0x10, eret_op = 0x18,
142 * func field of cop0 com opcodes.
145 tlbr1_op = 0x01, tlbw_op = 0x02,
146 tlbp1_op = 0x08, dctr_op = 0x09,
151 * fmt field of cop1 opcodes.
154 s_fmt, d_fmt, e_fmt, q_fmt,
159 * func field of cop1 instructions using d, s or w format.
162 fadd_op = 0x00, fsub_op = 0x01,
163 fmul_op = 0x02, fdiv_op = 0x03,
164 fsqrt_op = 0x04, fabs_op = 0x05,
165 fmov_op = 0x06, fneg_op = 0x07,
166 froundl_op = 0x08, ftruncl_op = 0x09,
167 fceill_op = 0x0a, ffloorl_op = 0x0b,
168 fround_op = 0x0c, ftrunc_op = 0x0d,
169 fceil_op = 0x0e, ffloor_op = 0x0f,
170 fmovc_op = 0x11, fmovz_op = 0x12,
171 fmovn_op = 0x13, fseleqz_op = 0x14,
172 frecip_op = 0x15, frsqrt_op = 0x16,
173 fselnez_op = 0x17, fmaddf_op = 0x18,
174 fmsubf_op = 0x19, frint_op = 0x1a,
175 fclass_op = 0x1b, fmin_op = 0x1c,
176 fmina_op = 0x1d, fmax_op = 0x1e,
177 fmaxa_op = 0x1f, fcvts_op = 0x20,
178 fcvtd_op = 0x21, fcvte_op = 0x22,
179 fcvtw_op = 0x24, fcvtl_op = 0x25,
184 * func field of cop1x opcodes (MIPS IV).
187 lwxc1_op = 0x00, ldxc1_op = 0x01,
188 swxc1_op = 0x08, sdxc1_op = 0x09,
189 pfetch_op = 0x0f, madd_s_op = 0x20,
190 madd_d_op = 0x21, madd_e_op = 0x22,
191 msub_s_op = 0x28, msub_d_op = 0x29,
192 msub_e_op = 0x2a, nmadd_s_op = 0x30,
193 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
194 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
199 * func field for mad opcodes (MIPS IV).
202 madd_fp_op = 0x08, msub_fp_op = 0x0a,
203 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
207 * func field for special3 lx opcodes (Cavium Octeon).
230 * func field for MSA MI10 format.
238 * MSA 2 bit format fields.
248 * (microMIPS) Major opcodes.
251 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
252 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
253 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
254 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
255 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
256 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
257 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
258 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
259 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
260 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
261 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
262 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
263 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
264 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
265 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
266 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
270 * (microMIPS) POOL32I minor opcodes.
272 enum mm_32i_minor_op {
273 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
274 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
275 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
276 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
277 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
278 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
279 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
280 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
281 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
285 * (microMIPS) POOL32A minor opcodes.
287 enum mm_32a_minor_op {
290 mm_sllv32_op = 0x010,
292 mm_pool32axf_op = 0x03c,
295 mm_srlv32_op = 0x090,
298 mm_addu32_op = 0x150,
299 mm_subu32_op = 0x1d0,
310 * (microMIPS) POOL32B functions.
329 * (microMIPS) POOL32C functions.
340 * (microMIPS) POOL32AXF minor opcodes.
342 enum mm_32axf_minor_op {
346 mm_mfhi32_op = 0x035,
349 mm_mflo32_op = 0x075,
350 mm_jalrhb_op = 0x07c,
354 mm_jalrshb_op = 0x17c,
356 mm_syscall_op = 0x22d,
363 * (microMIPS) POOL32F minor opcodes.
365 enum mm_32f_minor_op {
387 * (microMIPS) POOL32F secondary minor opcodes.
389 enum mm_32f_10_minor_op {
399 mm_lwxc1_func = 0x048,
400 mm_swxc1_func = 0x088,
401 mm_ldxc1_func = 0x0c8,
402 mm_sdxc1_func = 0x108,
406 * (microMIPS) POOL32F secondary minor opcodes.
408 enum mm_32f_40_minor_op {
414 * (microMIPS) POOL32F secondary minor opcodes.
416 enum mm_32f_60_minor_op {
424 * (microMIPS) POOL32F secondary minor opcodes.
426 enum mm_32f_70_minor_op {
432 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
434 enum mm_32f_73_minor_op {
439 mm_ffloorl_op = 0x0c,
444 mm_ffloorw_op = 0x2c,
456 mm_ftruncl_op = 0x8c,
460 mm_ftruncw_op = 0xac,
463 mm_froundl_op = 0xcc,
466 mm_froundw_op = 0xec,
471 * (microMIPS) POOL16C minor opcodes.
473 enum mm_16c_minor_op {
479 mm_jalrs16_op = 0x0f,
480 mm_jraddiusp_op = 0x18,
484 * (microMIPS) POOL16D minor opcodes.
486 enum mm_16d_minor_op {
495 MIPS16e_jal_op = 003,
501 MIPS16e_lwsp_op = 022,
503 MIPS16e_lbu_op = 024,
504 MIPS16e_lhu_op = 025,
505 MIPS16e_lwpc_op = 026,
506 MIPS16e_lwu_op = 027,
509 MIPS16e_swsp_op = 032,
512 MIPS16e_extend_op = 036,
513 MIPS16e_i64_op = 037,
516 enum MIPS16e_i64_func {
524 enum MIPS16e_rr_func {
528 enum MIPS6e_i8_func {
529 MIPS16e_swrasp_func = 02,
533 * (microMIPS) NOP instruction.
535 #define MM_NOP16 0x0c00
538 __BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
539 __BITFIELD_FIELD(unsigned int target : 26,
543 struct i_format { /* signed immediate format */
544 __BITFIELD_FIELD(unsigned int opcode : 6,
545 __BITFIELD_FIELD(unsigned int rs : 5,
546 __BITFIELD_FIELD(unsigned int rt : 5,
547 __BITFIELD_FIELD(signed int simmediate : 16,
551 struct u_format { /* unsigned immediate format */
552 __BITFIELD_FIELD(unsigned int opcode : 6,
553 __BITFIELD_FIELD(unsigned int rs : 5,
554 __BITFIELD_FIELD(unsigned int rt : 5,
555 __BITFIELD_FIELD(unsigned int uimmediate : 16,
559 struct c_format { /* Cache (>= R6000) format */
560 __BITFIELD_FIELD(unsigned int opcode : 6,
561 __BITFIELD_FIELD(unsigned int rs : 5,
562 __BITFIELD_FIELD(unsigned int c_op : 3,
563 __BITFIELD_FIELD(unsigned int cache : 2,
564 __BITFIELD_FIELD(unsigned int simmediate : 16,
568 struct r_format { /* Register format */
569 __BITFIELD_FIELD(unsigned int opcode : 6,
570 __BITFIELD_FIELD(unsigned int rs : 5,
571 __BITFIELD_FIELD(unsigned int rt : 5,
572 __BITFIELD_FIELD(unsigned int rd : 5,
573 __BITFIELD_FIELD(unsigned int re : 5,
574 __BITFIELD_FIELD(unsigned int func : 6,
578 struct p_format { /* Performance counter format (R10000) */
579 __BITFIELD_FIELD(unsigned int opcode : 6,
580 __BITFIELD_FIELD(unsigned int rs : 5,
581 __BITFIELD_FIELD(unsigned int rt : 5,
582 __BITFIELD_FIELD(unsigned int rd : 5,
583 __BITFIELD_FIELD(unsigned int re : 5,
584 __BITFIELD_FIELD(unsigned int func : 6,
588 struct f_format { /* FPU register format */
589 __BITFIELD_FIELD(unsigned int opcode : 6,
590 __BITFIELD_FIELD(unsigned int : 1,
591 __BITFIELD_FIELD(unsigned int fmt : 4,
592 __BITFIELD_FIELD(unsigned int rt : 5,
593 __BITFIELD_FIELD(unsigned int rd : 5,
594 __BITFIELD_FIELD(unsigned int re : 5,
595 __BITFIELD_FIELD(unsigned int func : 6,
599 struct ma_format { /* FPU multiply and add format (MIPS IV) */
600 __BITFIELD_FIELD(unsigned int opcode : 6,
601 __BITFIELD_FIELD(unsigned int fr : 5,
602 __BITFIELD_FIELD(unsigned int ft : 5,
603 __BITFIELD_FIELD(unsigned int fs : 5,
604 __BITFIELD_FIELD(unsigned int fd : 5,
605 __BITFIELD_FIELD(unsigned int func : 4,
606 __BITFIELD_FIELD(unsigned int fmt : 2,
610 struct b_format { /* BREAK and SYSCALL */
611 __BITFIELD_FIELD(unsigned int opcode : 6,
612 __BITFIELD_FIELD(unsigned int code : 20,
613 __BITFIELD_FIELD(unsigned int func : 6,
617 struct ps_format { /* MIPS-3D / paired single format */
618 __BITFIELD_FIELD(unsigned int opcode : 6,
619 __BITFIELD_FIELD(unsigned int rs : 5,
620 __BITFIELD_FIELD(unsigned int ft : 5,
621 __BITFIELD_FIELD(unsigned int fs : 5,
622 __BITFIELD_FIELD(unsigned int fd : 5,
623 __BITFIELD_FIELD(unsigned int func : 6,
627 struct v_format { /* MDMX vector format */
628 __BITFIELD_FIELD(unsigned int opcode : 6,
629 __BITFIELD_FIELD(unsigned int sel : 4,
630 __BITFIELD_FIELD(unsigned int fmt : 1,
631 __BITFIELD_FIELD(unsigned int vt : 5,
632 __BITFIELD_FIELD(unsigned int vs : 5,
633 __BITFIELD_FIELD(unsigned int vd : 5,
634 __BITFIELD_FIELD(unsigned int func : 6,
638 struct msa_mi10_format { /* MSA MI10 */
639 __BITFIELD_FIELD(unsigned int opcode : 6,
640 __BITFIELD_FIELD(signed int s10 : 10,
641 __BITFIELD_FIELD(unsigned int rs : 5,
642 __BITFIELD_FIELD(unsigned int wd : 5,
643 __BITFIELD_FIELD(unsigned int func : 4,
644 __BITFIELD_FIELD(unsigned int df : 2,
648 struct spec3_format { /* SPEC3 */
649 __BITFIELD_FIELD(unsigned int opcode:6,
650 __BITFIELD_FIELD(unsigned int rs:5,
651 __BITFIELD_FIELD(unsigned int rt:5,
652 __BITFIELD_FIELD(signed int simmediate:9,
653 __BITFIELD_FIELD(unsigned int func:7,
658 * microMIPS instruction formats (32-bit length)
661 * Parenthesis denote whether the format is a microMIPS instruction or
662 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
664 struct fb_format { /* FPU branch format (MIPS32) */
665 __BITFIELD_FIELD(unsigned int opcode : 6,
666 __BITFIELD_FIELD(unsigned int bc : 5,
667 __BITFIELD_FIELD(unsigned int cc : 3,
668 __BITFIELD_FIELD(unsigned int flag : 2,
669 __BITFIELD_FIELD(signed int simmediate : 16,
673 struct fp0_format { /* FPU multiply and add format (MIPS32) */
674 __BITFIELD_FIELD(unsigned int opcode : 6,
675 __BITFIELD_FIELD(unsigned int fmt : 5,
676 __BITFIELD_FIELD(unsigned int ft : 5,
677 __BITFIELD_FIELD(unsigned int fs : 5,
678 __BITFIELD_FIELD(unsigned int fd : 5,
679 __BITFIELD_FIELD(unsigned int func : 6,
683 struct mm_fp0_format { /* FPU multiply and add format (microMIPS) */
684 __BITFIELD_FIELD(unsigned int opcode : 6,
685 __BITFIELD_FIELD(unsigned int ft : 5,
686 __BITFIELD_FIELD(unsigned int fs : 5,
687 __BITFIELD_FIELD(unsigned int fd : 5,
688 __BITFIELD_FIELD(unsigned int fmt : 3,
689 __BITFIELD_FIELD(unsigned int op : 2,
690 __BITFIELD_FIELD(unsigned int func : 6,
694 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
695 __BITFIELD_FIELD(unsigned int opcode : 6,
696 __BITFIELD_FIELD(unsigned int op : 5,
697 __BITFIELD_FIELD(unsigned int rt : 5,
698 __BITFIELD_FIELD(unsigned int fs : 5,
699 __BITFIELD_FIELD(unsigned int fd : 5,
700 __BITFIELD_FIELD(unsigned int func : 6,
704 struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
705 __BITFIELD_FIELD(unsigned int opcode : 6,
706 __BITFIELD_FIELD(unsigned int rt : 5,
707 __BITFIELD_FIELD(unsigned int fs : 5,
708 __BITFIELD_FIELD(unsigned int fmt : 2,
709 __BITFIELD_FIELD(unsigned int op : 8,
710 __BITFIELD_FIELD(unsigned int func : 6,
714 struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
715 __BITFIELD_FIELD(unsigned int opcode : 6,
716 __BITFIELD_FIELD(unsigned int fd : 5,
717 __BITFIELD_FIELD(unsigned int fs : 5,
718 __BITFIELD_FIELD(unsigned int cc : 3,
719 __BITFIELD_FIELD(unsigned int zero : 2,
720 __BITFIELD_FIELD(unsigned int fmt : 2,
721 __BITFIELD_FIELD(unsigned int op : 3,
722 __BITFIELD_FIELD(unsigned int func : 6,
726 struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
727 __BITFIELD_FIELD(unsigned int opcode : 6,
728 __BITFIELD_FIELD(unsigned int rt : 5,
729 __BITFIELD_FIELD(unsigned int fs : 5,
730 __BITFIELD_FIELD(unsigned int fmt : 3,
731 __BITFIELD_FIELD(unsigned int op : 7,
732 __BITFIELD_FIELD(unsigned int func : 6,
736 struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
737 __BITFIELD_FIELD(unsigned int opcode : 6,
738 __BITFIELD_FIELD(unsigned int rt : 5,
739 __BITFIELD_FIELD(unsigned int fs : 5,
740 __BITFIELD_FIELD(unsigned int cc : 3,
741 __BITFIELD_FIELD(unsigned int fmt : 3,
742 __BITFIELD_FIELD(unsigned int cond : 4,
743 __BITFIELD_FIELD(unsigned int func : 6,
747 struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
748 __BITFIELD_FIELD(unsigned int opcode : 6,
749 __BITFIELD_FIELD(unsigned int index : 5,
750 __BITFIELD_FIELD(unsigned int base : 5,
751 __BITFIELD_FIELD(unsigned int fd : 5,
752 __BITFIELD_FIELD(unsigned int op : 5,
753 __BITFIELD_FIELD(unsigned int func : 6,
757 struct fp6_format { /* FPU madd and msub format (MIPS IV) */
758 __BITFIELD_FIELD(unsigned int opcode : 6,
759 __BITFIELD_FIELD(unsigned int fr : 5,
760 __BITFIELD_FIELD(unsigned int ft : 5,
761 __BITFIELD_FIELD(unsigned int fs : 5,
762 __BITFIELD_FIELD(unsigned int fd : 5,
763 __BITFIELD_FIELD(unsigned int func : 6,
767 struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
768 __BITFIELD_FIELD(unsigned int opcode : 6,
769 __BITFIELD_FIELD(unsigned int ft : 5,
770 __BITFIELD_FIELD(unsigned int fs : 5,
771 __BITFIELD_FIELD(unsigned int fd : 5,
772 __BITFIELD_FIELD(unsigned int fr : 5,
773 __BITFIELD_FIELD(unsigned int func : 6,
777 struct mm_i_format { /* Immediate format (microMIPS) */
778 __BITFIELD_FIELD(unsigned int opcode : 6,
779 __BITFIELD_FIELD(unsigned int rt : 5,
780 __BITFIELD_FIELD(unsigned int rs : 5,
781 __BITFIELD_FIELD(signed int simmediate : 16,
785 struct mm_m_format { /* Multi-word load/store format (microMIPS) */
786 __BITFIELD_FIELD(unsigned int opcode : 6,
787 __BITFIELD_FIELD(unsigned int rd : 5,
788 __BITFIELD_FIELD(unsigned int base : 5,
789 __BITFIELD_FIELD(unsigned int func : 4,
790 __BITFIELD_FIELD(signed int simmediate : 12,
794 struct mm_x_format { /* Scaled indexed load format (microMIPS) */
795 __BITFIELD_FIELD(unsigned int opcode : 6,
796 __BITFIELD_FIELD(unsigned int index : 5,
797 __BITFIELD_FIELD(unsigned int base : 5,
798 __BITFIELD_FIELD(unsigned int rd : 5,
799 __BITFIELD_FIELD(unsigned int func : 11,
803 struct mm_a_format { /* ADDIUPC format (microMIPS) */
804 __BITFIELD_FIELD(unsigned int opcode : 6,
805 __BITFIELD_FIELD(unsigned int rs : 3,
806 __BITFIELD_FIELD(signed int simmediate : 23,
811 * microMIPS instruction formats (16-bit length)
813 struct mm_b0_format { /* Unconditional branch format (microMIPS) */
814 __BITFIELD_FIELD(unsigned int opcode : 6,
815 __BITFIELD_FIELD(signed int simmediate : 10,
816 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
820 struct mm_b1_format { /* Conditional branch format (microMIPS) */
821 __BITFIELD_FIELD(unsigned int opcode : 6,
822 __BITFIELD_FIELD(unsigned int rs : 3,
823 __BITFIELD_FIELD(signed int simmediate : 7,
824 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
828 struct mm16_m_format { /* Multi-word load/store format */
829 __BITFIELD_FIELD(unsigned int opcode : 6,
830 __BITFIELD_FIELD(unsigned int func : 4,
831 __BITFIELD_FIELD(unsigned int rlist : 2,
832 __BITFIELD_FIELD(unsigned int imm : 4,
833 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
837 struct mm16_rb_format { /* Signed immediate format */
838 __BITFIELD_FIELD(unsigned int opcode : 6,
839 __BITFIELD_FIELD(unsigned int rt : 3,
840 __BITFIELD_FIELD(unsigned int base : 3,
841 __BITFIELD_FIELD(signed int simmediate : 4,
842 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
846 struct mm16_r3_format { /* Load from global pointer format */
847 __BITFIELD_FIELD(unsigned int opcode : 6,
848 __BITFIELD_FIELD(unsigned int rt : 3,
849 __BITFIELD_FIELD(signed int simmediate : 7,
850 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
854 struct mm16_r5_format { /* Load/store from stack pointer format */
855 __BITFIELD_FIELD(unsigned int opcode : 6,
856 __BITFIELD_FIELD(unsigned int rt : 5,
857 __BITFIELD_FIELD(signed int simmediate : 5,
858 __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
863 * MIPS16e instruction formats (16-bit length)
866 __BITFIELD_FIELD(unsigned int opcode : 5,
867 __BITFIELD_FIELD(unsigned int rx : 3,
868 __BITFIELD_FIELD(unsigned int nd : 1,
869 __BITFIELD_FIELD(unsigned int l : 1,
870 __BITFIELD_FIELD(unsigned int ra : 1,
871 __BITFIELD_FIELD(unsigned int func : 5,
876 __BITFIELD_FIELD(unsigned int opcode : 5,
877 __BITFIELD_FIELD(unsigned int x : 1,
878 __BITFIELD_FIELD(unsigned int imm20_16 : 5,
879 __BITFIELD_FIELD(signed int imm25_21 : 5,
884 __BITFIELD_FIELD(unsigned int opcode : 5,
885 __BITFIELD_FIELD(unsigned int func : 3,
886 __BITFIELD_FIELD(unsigned int imm : 8,
891 __BITFIELD_FIELD(unsigned int opcode : 5,
892 __BITFIELD_FIELD(unsigned int func : 3,
893 __BITFIELD_FIELD(unsigned int ry : 3,
894 __BITFIELD_FIELD(unsigned int imm : 5,
899 __BITFIELD_FIELD(unsigned int opcode : 5,
900 __BITFIELD_FIELD(unsigned int rx : 3,
901 __BITFIELD_FIELD(unsigned int imm : 8,
906 __BITFIELD_FIELD(unsigned int opcode : 5,
907 __BITFIELD_FIELD(unsigned int rx : 3,
908 __BITFIELD_FIELD(unsigned int ry : 3,
909 __BITFIELD_FIELD(unsigned int imm : 5,
914 __BITFIELD_FIELD(unsigned int opcode : 5,
915 __BITFIELD_FIELD(unsigned int func : 3,
916 __BITFIELD_FIELD(unsigned int imm : 8,
920 union mips_instruction {
922 unsigned short halfword[2];
923 unsigned char byte[4];
924 struct j_format j_format;
925 struct i_format i_format;
926 struct u_format u_format;
927 struct c_format c_format;
928 struct r_format r_format;
929 struct p_format p_format;
930 struct f_format f_format;
931 struct ma_format ma_format;
932 struct msa_mi10_format msa_mi10_format;
933 struct b_format b_format;
934 struct ps_format ps_format;
935 struct v_format v_format;
936 struct spec3_format spec3_format;
937 struct fb_format fb_format;
938 struct fp0_format fp0_format;
939 struct mm_fp0_format mm_fp0_format;
940 struct fp1_format fp1_format;
941 struct mm_fp1_format mm_fp1_format;
942 struct mm_fp2_format mm_fp2_format;
943 struct mm_fp3_format mm_fp3_format;
944 struct mm_fp4_format mm_fp4_format;
945 struct mm_fp5_format mm_fp5_format;
946 struct fp6_format fp6_format;
947 struct mm_fp6_format mm_fp6_format;
948 struct mm_i_format mm_i_format;
949 struct mm_m_format mm_m_format;
950 struct mm_x_format mm_x_format;
951 struct mm_a_format mm_a_format;
952 struct mm_b0_format mm_b0_format;
953 struct mm_b1_format mm_b1_format;
954 struct mm16_m_format mm16_m_format ;
955 struct mm16_rb_format mm16_rb_format;
956 struct mm16_r3_format mm16_r3_format;
957 struct mm16_r5_format mm16_r5_format;
960 union mips16e_instruction {
961 unsigned int full : 16;
965 struct m16e_ri64 ri64;
971 #endif /* _UAPI_ASM_INST_H */