2 * Atheros AR71XX/AR724X/AR913X SoC register definitions
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
15 #ifndef __ASM_MACH_AR71XX_REGS_H
16 #define __ASM_MACH_AR71XX_REGS_H
18 #include <linux/types.h>
19 #include <linux/init.h>
21 #include <linux/bitops.h>
23 #define AR71XX_APB_BASE 0x18000000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
29 #define AR71XX_SPI_SIZE 0x01000000
31 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
32 #define AR71XX_DDR_CTRL_SIZE 0x100
33 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
34 #define AR71XX_UART_SIZE 0x100
35 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
36 #define AR71XX_USB_CTRL_SIZE 0x100
37 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
38 #define AR71XX_GPIO_SIZE 0x100
39 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
40 #define AR71XX_PLL_SIZE 0x100
41 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
42 #define AR71XX_RESET_SIZE 0x100
44 #define AR71XX_PCI_MEM_BASE 0x10000000
45 #define AR71XX_PCI_MEM_SIZE 0x07000000
47 #define AR71XX_PCI_WIN0_OFFS 0x10000000
48 #define AR71XX_PCI_WIN1_OFFS 0x11000000
49 #define AR71XX_PCI_WIN2_OFFS 0x12000000
50 #define AR71XX_PCI_WIN3_OFFS 0x13000000
51 #define AR71XX_PCI_WIN4_OFFS 0x14000000
52 #define AR71XX_PCI_WIN5_OFFS 0x15000000
53 #define AR71XX_PCI_WIN6_OFFS 0x16000000
54 #define AR71XX_PCI_WIN7_OFFS 0x07000000
56 #define AR71XX_PCI_CFG_BASE \
57 (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
58 #define AR71XX_PCI_CFG_SIZE 0x100
60 #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
61 #define AR7240_USB_CTRL_SIZE 0x100
62 #define AR7240_OHCI_BASE 0x1b000000
63 #define AR7240_OHCI_SIZE 0x1000
65 #define AR724X_PCI_MEM_BASE 0x10000000
66 #define AR724X_PCI_MEM_SIZE 0x04000000
68 #define AR724X_PCI_CFG_BASE 0x14000000
69 #define AR724X_PCI_CFG_SIZE 0x1000
70 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
71 #define AR724X_PCI_CRP_SIZE 0x1000
72 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
73 #define AR724X_PCI_CTRL_SIZE 0x100
75 #define AR724X_EHCI_BASE 0x1b000000
76 #define AR724X_EHCI_SIZE 0x1000
78 #define AR913X_EHCI_BASE 0x1b000000
79 #define AR913X_EHCI_SIZE 0x1000
80 #define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
81 #define AR913X_WMAC_SIZE 0x30000
83 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
84 #define AR933X_UART_SIZE 0x14
85 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
86 #define AR933X_WMAC_SIZE 0x20000
87 #define AR933X_EHCI_BASE 0x1b000000
88 #define AR933X_EHCI_SIZE 0x1000
90 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
91 #define AR934X_WMAC_SIZE 0x20000
92 #define AR934X_EHCI_BASE 0x1b000000
93 #define AR934X_EHCI_SIZE 0x200
94 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
95 #define AR934X_SRIF_SIZE 0x1000
97 #define QCA955X_PCI_MEM_BASE0 0x10000000
98 #define QCA955X_PCI_MEM_BASE1 0x12000000
99 #define QCA955X_PCI_MEM_SIZE 0x02000000
100 #define QCA955X_PCI_CFG_BASE0 0x14000000
101 #define QCA955X_PCI_CFG_BASE1 0x16000000
102 #define QCA955X_PCI_CFG_SIZE 0x1000
103 #define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
104 #define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
105 #define QCA955X_PCI_CRP_SIZE 0x1000
106 #define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
107 #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
108 #define QCA955X_PCI_CTRL_SIZE 0x100
110 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
111 #define QCA955X_WMAC_SIZE 0x20000
112 #define QCA955X_EHCI0_BASE 0x1b000000
113 #define QCA955X_EHCI1_BASE 0x1b400000
114 #define QCA955X_EHCI_SIZE 0x1000
119 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
120 #define AR71XX_DDR_REG_PCI_WIN1 0x80
121 #define AR71XX_DDR_REG_PCI_WIN2 0x84
122 #define AR71XX_DDR_REG_PCI_WIN3 0x88
123 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
124 #define AR71XX_DDR_REG_PCI_WIN5 0x90
125 #define AR71XX_DDR_REG_PCI_WIN6 0x94
126 #define AR71XX_DDR_REG_PCI_WIN7 0x98
127 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
128 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
129 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
130 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
132 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
133 #define AR724X_DDR_REG_FLUSH_GE1 0x80
134 #define AR724X_DDR_REG_FLUSH_USB 0x84
135 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
137 #define AR913X_DDR_REG_FLUSH_GE0 0x7c
138 #define AR913X_DDR_REG_FLUSH_GE1 0x80
139 #define AR913X_DDR_REG_FLUSH_USB 0x84
140 #define AR913X_DDR_REG_FLUSH_WMAC 0x88
142 #define AR933X_DDR_REG_FLUSH_GE0 0x7c
143 #define AR933X_DDR_REG_FLUSH_GE1 0x80
144 #define AR933X_DDR_REG_FLUSH_USB 0x84
145 #define AR933X_DDR_REG_FLUSH_WMAC 0x88
147 #define AR934X_DDR_REG_FLUSH_GE0 0x9c
148 #define AR934X_DDR_REG_FLUSH_GE1 0xa0
149 #define AR934X_DDR_REG_FLUSH_USB 0xa4
150 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
151 #define AR934X_DDR_REG_FLUSH_WMAC 0xac
156 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
157 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
158 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
159 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
161 #define AR71XX_PLL_DIV_SHIFT 3
162 #define AR71XX_PLL_DIV_MASK 0x1f
163 #define AR71XX_CPU_DIV_SHIFT 16
164 #define AR71XX_CPU_DIV_MASK 0x3
165 #define AR71XX_DDR_DIV_SHIFT 18
166 #define AR71XX_DDR_DIV_MASK 0x3
167 #define AR71XX_AHB_DIV_SHIFT 20
168 #define AR71XX_AHB_DIV_MASK 0x7
170 #define AR724X_PLL_REG_CPU_CONFIG 0x00
171 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
173 #define AR724X_PLL_DIV_SHIFT 0
174 #define AR724X_PLL_DIV_MASK 0x3ff
175 #define AR724X_PLL_REF_DIV_SHIFT 10
176 #define AR724X_PLL_REF_DIV_MASK 0xf
177 #define AR724X_AHB_DIV_SHIFT 19
178 #define AR724X_AHB_DIV_MASK 0x1
179 #define AR724X_DDR_DIV_SHIFT 22
180 #define AR724X_DDR_DIV_MASK 0x3
182 #define AR913X_PLL_REG_CPU_CONFIG 0x00
183 #define AR913X_PLL_REG_ETH_CONFIG 0x04
184 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
185 #define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18
187 #define AR913X_PLL_DIV_SHIFT 0
188 #define AR913X_PLL_DIV_MASK 0x3ff
189 #define AR913X_DDR_DIV_SHIFT 22
190 #define AR913X_DDR_DIV_MASK 0x3
191 #define AR913X_AHB_DIV_SHIFT 19
192 #define AR913X_AHB_DIV_MASK 0x1
194 #define AR933X_PLL_CPU_CONFIG_REG 0x00
195 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
197 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
198 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
199 #define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
200 #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
201 #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
202 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
204 #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
205 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
206 #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
207 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
208 #define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
209 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
210 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
212 #define AR934X_PLL_CPU_CONFIG_REG 0x00
213 #define AR934X_PLL_DDR_CONFIG_REG 0x04
214 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
216 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
217 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
218 #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
219 #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
220 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
221 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
222 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
223 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
225 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
226 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
227 #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
228 #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
229 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
230 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
231 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
232 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
234 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
235 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
236 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
237 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
238 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
239 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
240 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
241 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
242 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
243 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
244 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
245 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
247 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
248 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
249 #define QCA955X_PLL_CLK_CTRL_REG 0x08
251 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
252 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
253 #define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
254 #define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
255 #define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
256 #define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
257 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
258 #define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
260 #define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
261 #define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
262 #define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
263 #define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
264 #define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
265 #define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
266 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
267 #define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
269 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
270 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
271 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
272 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
273 #define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
274 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
275 #define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
276 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
277 #define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
278 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
279 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
280 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
285 #define AR71XX_USB_CTRL_REG_FLADJ 0x00
286 #define AR71XX_USB_CTRL_REG_CONFIG 0x04
291 #define AR71XX_RESET_REG_TIMER 0x00
292 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
293 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
294 #define AR71XX_RESET_REG_WDOG 0x0c
295 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
296 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
297 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
298 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
299 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
300 #define AR71XX_RESET_REG_RESET_MODULE 0x24
301 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
302 #define AR71XX_RESET_REG_PERFC0 0x30
303 #define AR71XX_RESET_REG_PERFC1 0x34
304 #define AR71XX_RESET_REG_REV_ID 0x90
306 #define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18
307 #define AR913X_RESET_REG_RESET_MODULE 0x1c
308 #define AR913X_RESET_REG_PERF_CTRL 0x20
309 #define AR913X_RESET_REG_PERFC0 0x24
310 #define AR913X_RESET_REG_PERFC1 0x28
312 #define AR724X_RESET_REG_RESET_MODULE 0x1c
314 #define AR933X_RESET_REG_RESET_MODULE 0x1c
315 #define AR933X_RESET_REG_BOOTSTRAP 0xac
317 #define AR934X_RESET_REG_RESET_MODULE 0x1c
318 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
319 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
321 #define QCA955X_RESET_REG_RESET_MODULE 0x1c
322 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
323 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
325 #define MISC_INT_ETHSW BIT(12)
326 #define MISC_INT_TIMER4 BIT(10)
327 #define MISC_INT_TIMER3 BIT(9)
328 #define MISC_INT_TIMER2 BIT(8)
329 #define MISC_INT_DMA BIT(7)
330 #define MISC_INT_OHCI BIT(6)
331 #define MISC_INT_PERFC BIT(5)
332 #define MISC_INT_WDOG BIT(4)
333 #define MISC_INT_UART BIT(3)
334 #define MISC_INT_GPIO BIT(2)
335 #define MISC_INT_ERROR BIT(1)
336 #define MISC_INT_TIMER BIT(0)
338 #define AR71XX_RESET_EXTERNAL BIT(28)
339 #define AR71XX_RESET_FULL_CHIP BIT(24)
340 #define AR71XX_RESET_CPU_NMI BIT(21)
341 #define AR71XX_RESET_CPU_COLD BIT(20)
342 #define AR71XX_RESET_DMA BIT(19)
343 #define AR71XX_RESET_SLIC BIT(18)
344 #define AR71XX_RESET_STEREO BIT(17)
345 #define AR71XX_RESET_DDR BIT(16)
346 #define AR71XX_RESET_GE1_MAC BIT(13)
347 #define AR71XX_RESET_GE1_PHY BIT(12)
348 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
349 #define AR71XX_RESET_GE0_MAC BIT(9)
350 #define AR71XX_RESET_GE0_PHY BIT(8)
351 #define AR71XX_RESET_USB_OHCI_DLL BIT(6)
352 #define AR71XX_RESET_USB_HOST BIT(5)
353 #define AR71XX_RESET_USB_PHY BIT(4)
354 #define AR71XX_RESET_PCI_BUS BIT(1)
355 #define AR71XX_RESET_PCI_CORE BIT(0)
357 #define AR7240_RESET_USB_HOST BIT(5)
358 #define AR7240_RESET_OHCI_DLL BIT(3)
360 #define AR724X_RESET_GE1_MDIO BIT(23)
361 #define AR724X_RESET_GE0_MDIO BIT(22)
362 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
363 #define AR724X_RESET_PCIE_PHY BIT(7)
364 #define AR724X_RESET_PCIE BIT(6)
365 #define AR724X_RESET_USB_HOST BIT(5)
366 #define AR724X_RESET_USB_PHY BIT(4)
367 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
369 #define AR913X_RESET_AMBA2WMAC BIT(22)
370 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
371 #define AR913X_RESET_USB_HOST BIT(5)
372 #define AR913X_RESET_USB_PHY BIT(4)
374 #define AR933X_RESET_WMAC BIT(11)
375 #define AR933X_RESET_USB_HOST BIT(5)
376 #define AR933X_RESET_USB_PHY BIT(4)
377 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
379 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
380 #define AR934X_RESET_USB_HOST BIT(5)
381 #define AR934X_RESET_USB_PHY BIT(4)
382 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
384 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
386 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
387 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
388 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
389 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
390 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
391 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
392 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
393 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
394 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
395 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
396 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
397 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
398 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
399 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
400 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
402 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
404 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
405 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
406 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
407 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
408 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
409 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
410 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
411 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
412 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
413 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \
414 (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
415 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
417 #define AR934X_PCIE_WMAC_INT_PCIE_ALL \
418 (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
419 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
420 AR934X_PCIE_WMAC_INT_PCIE_RC3)
422 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
423 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
424 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
425 #define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
426 #define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
427 #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
428 #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
429 #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
430 #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
431 #define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
432 #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
433 #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
434 #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
435 #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
436 #define QCA955X_EXT_INT_USB1 BIT(24)
437 #define QCA955X_EXT_INT_USB2 BIT(28)
439 #define QCA955X_EXT_INT_WMAC_ALL \
440 (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
441 QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
443 #define QCA955X_EXT_INT_PCIE_RC1_ALL \
444 (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
445 QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
446 QCA955X_EXT_INT_PCIE_RC1_INT3)
448 #define QCA955X_EXT_INT_PCIE_RC2_ALL \
449 (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
450 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
451 QCA955X_EXT_INT_PCIE_RC2_INT3)
453 #define REV_ID_MAJOR_MASK 0xfff0
454 #define REV_ID_MAJOR_AR71XX 0x00a0
455 #define REV_ID_MAJOR_AR913X 0x00b0
456 #define REV_ID_MAJOR_AR7240 0x00c0
457 #define REV_ID_MAJOR_AR7241 0x0100
458 #define REV_ID_MAJOR_AR7242 0x1100
459 #define REV_ID_MAJOR_AR9330 0x0110
460 #define REV_ID_MAJOR_AR9331 0x1110
461 #define REV_ID_MAJOR_AR9341 0x0120
462 #define REV_ID_MAJOR_AR9342 0x1120
463 #define REV_ID_MAJOR_AR9344 0x2120
464 #define REV_ID_MAJOR_QCA9556 0x0130
465 #define REV_ID_MAJOR_QCA9558 0x1130
467 #define AR71XX_REV_ID_MINOR_MASK 0x3
468 #define AR71XX_REV_ID_MINOR_AR7130 0x0
469 #define AR71XX_REV_ID_MINOR_AR7141 0x1
470 #define AR71XX_REV_ID_MINOR_AR7161 0x2
471 #define AR71XX_REV_ID_REVISION_MASK 0x3
472 #define AR71XX_REV_ID_REVISION_SHIFT 2
474 #define AR913X_REV_ID_MINOR_MASK 0x3
475 #define AR913X_REV_ID_MINOR_AR9130 0x0
476 #define AR913X_REV_ID_MINOR_AR9132 0x1
477 #define AR913X_REV_ID_REVISION_MASK 0x3
478 #define AR913X_REV_ID_REVISION_SHIFT 2
480 #define AR933X_REV_ID_REVISION_MASK 0x3
482 #define AR724X_REV_ID_REVISION_MASK 0x3
484 #define AR934X_REV_ID_REVISION_MASK 0xf
486 #define QCA955X_REV_ID_REVISION_MASK 0xf
491 #define AR71XX_SPI_REG_FS 0x00 /* Function Select */
492 #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
493 #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
494 #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
496 #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
498 #define AR71XX_SPI_CTRL_RD BIT(6) /* Remap Disable */
499 #define AR71XX_SPI_CTRL_DIV_MASK 0x3f
501 #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
502 #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
503 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
504 #define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0)
505 #define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1)
506 #define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2)
507 #define AR71XX_SPI_IOC_CS_ALL (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
513 #define AR71XX_GPIO_REG_OE 0x00
514 #define AR71XX_GPIO_REG_IN 0x04
515 #define AR71XX_GPIO_REG_OUT 0x08
516 #define AR71XX_GPIO_REG_SET 0x0c
517 #define AR71XX_GPIO_REG_CLEAR 0x10
518 #define AR71XX_GPIO_REG_INT_MODE 0x14
519 #define AR71XX_GPIO_REG_INT_TYPE 0x18
520 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c
521 #define AR71XX_GPIO_REG_INT_PENDING 0x20
522 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
523 #define AR71XX_GPIO_REG_FUNC 0x28
525 #define AR934X_GPIO_REG_FUNC 0x6c
527 #define AR71XX_GPIO_COUNT 16
528 #define AR7240_GPIO_COUNT 18
529 #define AR7241_GPIO_COUNT 20
530 #define AR913X_GPIO_COUNT 22
531 #define AR933X_GPIO_COUNT 30
532 #define AR934X_GPIO_COUNT 23
533 #define QCA955X_GPIO_COUNT 24
538 #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
539 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
540 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
542 #define AR934X_SRIF_DDR_DPLL1_REG 0x240
543 #define AR934X_SRIF_DDR_DPLL2_REG 0x244
544 #define AR934X_SRIF_DDR_DPLL3_REG 0x248
546 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
547 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
548 #define AR934X_SRIF_DPLL1_NINT_SHIFT 18
549 #define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
550 #define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
552 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
553 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
554 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
556 #endif /* __ASM_MACH_AR71XX_REGS_H */