arch/mips/cavium-octeon/octeon_68xx.dts

   1 /dts-v1/;
   2 /*
   3  * OCTEON 68XX device tree skeleton.
   4  *
   5  * This device tree is pruned and patched by early boot code before
   6  * use.  Because of this, it contains a super-set of the available
   7  * devices and properties.
   8  */
   9 / {
  10         compatible = "cavium,octeon-6880";
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13         interrupt-parent = <&ciu2>;
  14
  15         soc@0 {
  16                 compatible = "simple-bus";
  17                 #address-cells = <2>;
  18                 #size-cells = <2>;
  19                 ranges; /* Direct mapping */
  20
  21                 ciu2: interrupt-controller@1070100000000 {
  22                         compatible = "cavium,octeon-6880-ciu2";
  23                         interrupt-controller;
  24                         /* Interrupts are specified by two parts:
  25                          * 1) Controller register (0 or 7)
  26                          * 2) Bit within the register (0..63)
  27                          */
  28                         #address-cells = <0>;
  29                         #interrupt-cells = <2>;
  30                         reg = <0x10701 0x00000000 0x0 0x4000000>;
  31                 };
  32
  33                 gpio: gpio-controller@1070000000800 {
  34                         #gpio-cells = <2>;
  35                         compatible = "cavium,octeon-3860-gpio";
  36                         reg = <0x10700 0x00000800 0x0 0x100>;
  37                         gpio-controller;
  38                         /* Interrupts are specified by two parts:
  39                          * 1) GPIO pin number (0..15)
  40                          * 2) Triggering (1 - edge rising
  41                          *                2 - edge falling
  42                          *                4 - level active high
  43                          *                8 - level active low)
  44                          */
  45                         interrupt-controller;
  46                         #interrupt-cells = <2>;
  47                         /* The GPIO pins connect to 16 consecutive CUI bits */
  48                         interrupts = <7 0>,  <7 1>,  <7 2>,  <7 3>,
  49                                      <7 4>,  <7 5>,  <7 6>,  <7 7>,
  50                                      <7 8>,  <7 9>,  <7 10>, <7 11>,
  51                                      <7 12>, <7 13>, <7 14>, <7 15>;
  52                 };
  53
  54                 smi0: mdio@1180000003800 {
  55                         compatible = "cavium,octeon-3860-mdio";
  56                         #address-cells = <1>;
  57                         #size-cells = <0>;
  58                         reg = <0x11800 0x00003800 0x0 0x40>;
  59
  60                         phy0: ethernet-phy@6 {
  61                                 compatible = "marvell,88e1118";
  62                                 marvell,reg-init =
  63                                         /* Fix rx and tx clock transition timing */
  64                                         <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
  65                                         /* Adjust LED drive. */
  66                                         <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
  67                                         /* irq, blink-activity, blink-link */
  68                                         <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
  69                                 reg = <6>;
  70                         };
  71
  72                         phy1: ethernet-phy@1 {
  73                                 cavium,qlm-trim = "4,sgmii";
  74                                 reg = <1>;
  75                                 compatible = "marvell,88e1149r";
  76                                 marvell,reg-init = <3 0x10 0 0x5777>,
  77                                         <3 0x11 0 0x00aa>,
  78                                         <3 0x12 0 0x4105>,
  79                                         <3 0x13 0 0x0a60>;
  80                         };
  81                         phy2: ethernet-phy@2 {
  82                                 cavium,qlm-trim = "4,sgmii";
  83                                 reg = <2>;
  84                                 compatible = "marvell,88e1149r";
  85                                 marvell,reg-init = <3 0x10 0 0x5777>,
  86                                         <3 0x11 0 0x00aa>,
  87                                         <3 0x12 0 0x4105>,
  88                                         <3 0x13 0 0x0a60>;
  89                         };
  90                         phy3: ethernet-phy@3 {
  91                                 cavium,qlm-trim = "4,sgmii";
  92                                 reg = <3>;
  93                                 compatible = "marvell,88e1149r";
  94                                 marvell,reg-init = <3 0x10 0 0x5777>,
  95                                         <3 0x11 0 0x00aa>,
  96                                         <3 0x12 0 0x4105>,
  97                                         <3 0x13 0 0x0a60>;
  98                         };
  99                         phy4: ethernet-phy@4 {
 100                                 cavium,qlm-trim = "4,sgmii";
 101                                 reg = <4>;
 102                                 compatible = "marvell,88e1149r";
 103                                 marvell,reg-init = <3 0x10 0 0x5777>,
 104                                         <3 0x11 0 0x00aa>,
 105                                         <3 0x12 0 0x4105>,
 106                                         <3 0x13 0 0x0a60>;
 107                         };
 108                 };
 109
 110                 smi1: mdio@1180000003880 {
 111                         compatible = "cavium,octeon-3860-mdio";
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114                         reg = <0x11800 0x00003880 0x0 0x40>;
 115
 116                         phy41: ethernet-phy@1 {
 117                                 cavium,qlm-trim = "0,sgmii";
 118                                 reg = <1>;
 119                                 compatible = "marvell,88e1149r";
 120                                 marvell,reg-init = <3 0x10 0 0x5777>,
 121                                         <3 0x11 0 0x00aa>,
 122                                         <3 0x12 0 0x4105>,
 123                                         <3 0x13 0 0x0a60>;
 124                         };
 125                         phy42: ethernet-phy@2 {
 126                                 cavium,qlm-trim = "0,sgmii";
 127                                 reg = <2>;
 128                                 compatible = "marvell,88e1149r";
 129                                 marvell,reg-init = <3 0x10 0 0x5777>,
 130                                         <3 0x11 0 0x00aa>,
 131                                         <3 0x12 0 0x4105>,
 132                                         <3 0x13 0 0x0a60>;
 133                         };
 134                         phy43: ethernet-phy@3 {
 135                                 cavium,qlm-trim = "0,sgmii";
 136                                 reg = <3>;
 137                                 compatible = "marvell,88e1149r";
 138                                 marvell,reg-init = <3 0x10 0 0x5777>,
 139                                         <3 0x11 0 0x00aa>,
 140                                         <3 0x12 0 0x4105>,
 141                                         <3 0x13 0 0x0a60>;
 142                         };
 143                         phy44: ethernet-phy@4 {
 144                                 cavium,qlm-trim = "0,sgmii";
 145                                 reg = <4>;
 146                                 compatible = "marvell,88e1149r";
 147                                 marvell,reg-init = <3 0x10 0 0x5777>,
 148                                         <3 0x11 0 0x00aa>,
 149                                         <3 0x12 0 0x4105>,
 150                                         <3 0x13 0 0x0a60>;
 151                         };
 152                 };
 153
 154                 smi2: mdio@1180000003900 {
 155                         compatible = "cavium,octeon-3860-mdio";
 156                         #address-cells = <1>;
 157                         #size-cells = <0>;
 158                         reg = <0x11800 0x00003900 0x0 0x40>;
 159
 160                         phy21: ethernet-phy@1 {
 161                                 cavium,qlm-trim = "2,sgmii";
 162                                 reg = <1>;
 163                                 compatible = "marvell,88e1149r";
 164                                 marvell,reg-init = <3 0x10 0 0x5777>,
 165                                         <3 0x11 0 0x00aa>,
 166                                         <3 0x12 0 0x4105>,
 167                                         <3 0x13 0 0x0a60>;
 168                         };
 169                         phy22: ethernet-phy@2 {
 170                                 cavium,qlm-trim = "2,sgmii";
 171                                 reg = <2>;
 172                                 compatible = "marvell,88e1149r";
 173                                 marvell,reg-init = <3 0x10 0 0x5777>,
 174                                         <3 0x11 0 0x00aa>,
 175                                         <3 0x12 0 0x4105>,
 176                                         <3 0x13 0 0x0a60>;
 177                         };
 178                         phy23: ethernet-phy@3 {
 179                                 cavium,qlm-trim = "2,sgmii";
 180                                 reg = <3>;
 181                                 compatible = "marvell,88e1149r";
 182                                 marvell,reg-init = <3 0x10 0 0x5777>,
 183                                         <3 0x11 0 0x00aa>,
 184                                         <3 0x12 0 0x4105>,
 185                                         <3 0x13 0 0x0a60>;
 186                         };
 187                         phy24: ethernet-phy@4 {
 188                                 cavium,qlm-trim = "2,sgmii";
 189                                 reg = <4>;
 190                                 compatible = "marvell,88e1149r";
 191                                 marvell,reg-init = <3 0x10 0 0x5777>,
 192                                         <3 0x11 0 0x00aa>,
 193                                         <3 0x12 0 0x4105>,
 194                                         <3 0x13 0 0x0a60>;
 195                         };
 196                 };
 197
 198                 smi3: mdio@1180000003980 {
 199                         compatible = "cavium,octeon-3860-mdio";
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         reg = <0x11800 0x00003980 0x0 0x40>;
 203
 204                         phy11: ethernet-phy@1 {
 205                                 cavium,qlm-trim = "3,sgmii";
 206                                 reg = <1>;
 207                                 compatible = "marvell,88e1149r";
 208                                 marvell,reg-init = <3 0x10 0 0x5777>,
 209                                         <3 0x11 0 0x00aa>,
 210                                         <3 0x12 0 0x4105>,
 211                                         <3 0x13 0 0x0a60>;
 212                         };
 213                         phy12: ethernet-phy@2 {
 214                                 cavium,qlm-trim = "3,sgmii";
 215                                 reg = <2>;
 216                                 compatible = "marvell,88e1149r";
 217                                 marvell,reg-init = <3 0x10 0 0x5777>,
 218                                         <3 0x11 0 0x00aa>,
 219                                         <3 0x12 0 0x4105>,
 220                                         <3 0x13 0 0x0a60>;
 221                         };
 222                         phy13: ethernet-phy@3 {
 223                                 cavium,qlm-trim = "3,sgmii";
 224                                 reg = <3>;
 225                                 compatible = "marvell,88e1149r";
 226                                 marvell,reg-init = <3 0x10 0 0x5777>,
 227                                         <3 0x11 0 0x00aa>,
 228                                         <3 0x12 0 0x4105>,
 229                                         <3 0x13 0 0x0a60>;
 230                         };
 231                         phy14: ethernet-phy@4 {
 232                                 cavium,qlm-trim = "3,sgmii";
 233                                 reg = <4>;
 234                                 compatible = "marvell,88e1149r";
 235                                 marvell,reg-init = <3 0x10 0 0x5777>,
 236                                         <3 0x11 0 0x00aa>,
 237                                         <3 0x12 0 0x4105>,
 238                                         <3 0x13 0 0x0a60>;
 239                         };
 240                 };
 241
 242                 mix0: ethernet@1070000100000 {
 243                         compatible = "cavium,octeon-5750-mix";
 244                         reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
 245                               <0x11800 0xE0000000 0x0 0x300>, /* AGL */
 246                               <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
 247                               <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
 248                         cell-index = <0>;
 249                         interrupts = <6 40>, <6 32>;
 250                         local-mac-address = [ 00 00 00 00 00 00 ];
 251                         phy-handle = <&phy0>;
 252                 };
 253
 254                 pip: pip@11800a0000000 {
 255                         compatible = "cavium,octeon-3860-pip";
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         reg = <0x11800 0xa0000000 0x0 0x2000>;
 259
 260                         interface@4 {
 261                                 compatible = "cavium,octeon-3860-pip-interface";
 262                                 #address-cells = <1>;
 263                                 #size-cells = <0>;
 264                                 reg = <0x4>; /* interface */
 265
 266                                 ethernet@0 {
 267                                         compatible = "cavium,octeon-3860-pip-port";
 268                                         reg = <0x0>; /* Port */
 269                                         local-mac-address = [ 00 00 00 00 00 00 ];
 270                                         phy-handle = <&phy1>;
 271                                 };
 272                                 ethernet@1 {
 273                                         compatible = "cavium,octeon-3860-pip-port";
 274                                         reg = <0x1>; /* Port */
 275                                         local-mac-address = [ 00 00 00 00 00 00 ];
 276                                         phy-handle = <&phy2>;
 277                                 };
 278                                 ethernet@2 {
 279                                         compatible = "cavium,octeon-3860-pip-port";
 280                                         reg = <0x2>; /* Port */
 281                                         local-mac-address = [ 00 00 00 00 00 00 ];
 282                                         phy-handle = <&phy3>;
 283                                 };
 284                                 ethernet@3 {
 285                                         compatible = "cavium,octeon-3860-pip-port";
 286                                         reg = <0x3>; /* Port */
 287                                         local-mac-address = [ 00 00 00 00 00 00 ];
 288                                         phy-handle = <&phy4>;
 289                                 };
 290                         };
 291
 292                         interface@3 {
 293                                 compatible = "cavium,octeon-3860-pip-interface";
 294                                 #address-cells = <1>;
 295                                 #size-cells = <0>;
 296                                 reg = <0x3>; /* interface */
 297
 298                                 ethernet@0 {
 299                                         compatible = "cavium,octeon-3860-pip-port";
 300                                         reg = <0x0>; /* Port */
 301                                         local-mac-address = [ 00 00 00 00 00 00 ];
 302                                         phy-handle = <&phy11>;
 303                                 };
 304                                 ethernet@1 {
 305                                         compatible = "cavium,octeon-3860-pip-port";
 306                                         reg = <0x1>; /* Port */
 307                                         local-mac-address = [ 00 00 00 00 00 00 ];
 308                                         phy-handle = <&phy12>;
 309                                 };
 310                                 ethernet@2 {
 311                                         compatible = "cavium,octeon-3860-pip-port";
 312                                         reg = <0x2>; /* Port */
 313                                         local-mac-address = [ 00 00 00 00 00 00 ];
 314                                         phy-handle = <&phy13>;
 315                                 };
 316                                 ethernet@3 {
 317                                         compatible = "cavium,octeon-3860-pip-port";
 318                                         reg = <0x3>; /* Port */
 319                                         local-mac-address = [ 00 00 00 00 00 00 ];
 320                                         phy-handle = <&phy14>;
 321                                 };
 322                         };
 323
 324                         interface@2 {
 325                                 compatible = "cavium,octeon-3860-pip-interface";
 326                                 #address-cells = <1>;
 327                                 #size-cells = <0>;
 328                                 reg = <0x2>; /* interface */
 329
 330                                 ethernet@0 {
 331                                         compatible = "cavium,octeon-3860-pip-port";
 332                                         reg = <0x0>; /* Port */
 333                                         local-mac-address = [ 00 00 00 00 00 00 ];
 334                                         phy-handle = <&phy21>;
 335                                 };
 336                                 ethernet@1 {
 337                                         compatible = "cavium,octeon-3860-pip-port";
 338                                         reg = <0x1>; /* Port */
 339                                         local-mac-address = [ 00 00 00 00 00 00 ];
 340                                         phy-handle = <&phy22>;
 341                                 };
 342                                 ethernet@2 {
 343                                         compatible = "cavium,octeon-3860-pip-port";
 344                                         reg = <0x2>; /* Port */
 345                                         local-mac-address = [ 00 00 00 00 00 00 ];
 346                                         phy-handle = <&phy23>;
 347                                 };
 348                                 ethernet@3 {
 349                                         compatible = "cavium,octeon-3860-pip-port";
 350                                         reg = <0x3>; /* Port */
 351                                         local-mac-address = [ 00 00 00 00 00 00 ];
 352                                         phy-handle = <&phy24>;
 353                                 };
 354                         };
 355
 356                         interface@1 {
 357                                 compatible = "cavium,octeon-3860-pip-interface";
 358                                 #address-cells = <1>;
 359                                 #size-cells = <0>;
 360                                 reg = <0x1>; /* interface */
 361
 362                                 ethernet@0 {
 363                                         compatible = "cavium,octeon-3860-pip-port";
 364                                         reg = <0x0>; /* Port */
 365                                         local-mac-address = [ 00 00 00 00 00 00 ];
 366                                 };
 367                         };
 368
 369                         interface@0 {
 370                                 compatible = "cavium,octeon-3860-pip-interface";
 371                                 #address-cells = <1>;
 372                                 #size-cells = <0>;
 373                                 reg = <0x0>; /* interface */
 374
 375                                 ethernet@0 {
 376                                         compatible = "cavium,octeon-3860-pip-port";
 377                                         reg = <0x0>; /* Port */
 378                                         local-mac-address = [ 00 00 00 00 00 00 ];
 379                                         phy-handle = <&phy41>;
 380                                 };
 381                                 ethernet@1 {
 382                                         compatible = "cavium,octeon-3860-pip-port";
 383                                         reg = <0x1>; /* Port */
 384                                         local-mac-address = [ 00 00 00 00 00 00 ];
 385                                         phy-handle = <&phy42>;
 386                                 };
 387                                 ethernet@2 {
 388                                         compatible = "cavium,octeon-3860-pip-port";
 389                                         reg = <0x2>; /* Port */
 390                                         local-mac-address = [ 00 00 00 00 00 00 ];
 391                                         phy-handle = <&phy43>;
 392                                 };
 393                                 ethernet@3 {
 394                                         compatible = "cavium,octeon-3860-pip-port";
 395                                         reg = <0x3>; /* Port */
 396                                         local-mac-address = [ 00 00 00 00 00 00 ];
 397                                         phy-handle = <&phy44>;
 398                                 };
 399                         };
 400                 };
 401
 402                 twsi0: i2c@1180000001000 {
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         compatible = "cavium,octeon-3860-twsi";
 406                         reg = <0x11800 0x00001000 0x0 0x200>;
 407                         interrupts = <3 32>;
 408                         clock-frequency = <100000>;
 409
 410                         rtc@68 {
 411                                 compatible = "dallas,ds1337";
 412                                 reg = <0x68>;
 413                         };
 414                         tmp@4c {
 415                                 compatible = "ti,tmp421";
 416                                 reg = <0x4c>;
 417                         };
 418                 };
 419
 420                 twsi1: i2c@1180000001200 {
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         compatible = "cavium,octeon-3860-twsi";
 424                         reg = <0x11800 0x00001200 0x0 0x200>;
 425                         interrupts = <3 33>;
 426                         clock-frequency = <100000>;
 427                 };
 428
 429                 uart0: serial@1180000000800 {
 430                         compatible = "cavium,octeon-3860-uart","ns16550";
 431                         reg = <0x11800 0x00000800 0x0 0x400>;
 432                         clock-frequency = <0>;
 433                         current-speed = <115200>;
 434                         reg-shift = <3>;
 435                         interrupts = <3 36>;
 436                 };
 437
 438                 uart1: serial@1180000000c00 {
 439                         compatible = "cavium,octeon-3860-uart","ns16550";
 440                         reg = <0x11800 0x00000c00 0x0 0x400>;
 441                         clock-frequency = <0>;
 442                         current-speed = <115200>;
 443                         reg-shift = <3>;
 444                         interrupts = <3 37>;
 445                 };
 446
 447                 bootbus: bootbus@1180000000000 {
 448                         compatible = "cavium,octeon-3860-bootbus";
 449                         reg = <0x11800 0x00000000 0x0 0x200>;
 450                         /* The chip select number and offset */
 451                         #address-cells = <2>;
 452                         /* The size of the chip select region */
 453                         #size-cells = <1>;
 454                         ranges = <0 0  0       0x1f400000  0xc00000>,
 455                                  <1 0  0x10000 0x30000000  0>,
 456                                  <2 0  0x10000 0x40000000  0>,
 457                                  <3 0  0x10000 0x50000000  0>,
 458                                  <4 0  0       0x1d020000  0x10000>,
 459                                  <5 0  0       0x1d040000  0x10000>,
 460                                  <6 0  0       0x1d050000  0x10000>,
 461                                  <7 0  0x10000 0x90000000  0>;
 462
 463                         cavium,cs-config@0 {
 464                                 compatible = "cavium,octeon-3860-bootbus-config";
 465                                 cavium,cs-index = <0>;
 466                                 cavium,t-adr  = <10>;
 467                                 cavium,t-ce   = <50>;
 468                                 cavium,t-oe   = <50>;
 469                                 cavium,t-we   = <35>;
 470                                 cavium,t-rd-hld = <25>;
 471                                 cavium,t-wr-hld = <35>;
 472                                 cavium,t-pause  = <0>;
 473                                 cavium,t-wait   = <300>;
 474                                 cavium,t-page   = <25>;
 475                                 cavium,t-rd-dly = <0>;
 476
 477                                 cavium,pages     = <0>;
 478                                 cavium,bus-width = <8>;
 479                         };
 480                         cavium,cs-config@4 {
 481                                 compatible = "cavium,octeon-3860-bootbus-config";
 482                                 cavium,cs-index = <4>;
 483                                 cavium,t-adr  = <320>;
 484                                 cavium,t-ce   = <320>;
 485                                 cavium,t-oe   = <320>;
 486                                 cavium,t-we   = <320>;
 487                                 cavium,t-rd-hld = <320>;
 488                                 cavium,t-wr-hld = <320>;
 489                                 cavium,t-pause  = <320>;
 490                                 cavium,t-wait   = <320>;
 491                                 cavium,t-page   = <320>;
 492                                 cavium,t-rd-dly = <0>;
 493
 494                                 cavium,pages     = <0>;
 495                                 cavium,bus-width = <8>;
 496                         };
 497                         cavium,cs-config@5 {
 498                                 compatible = "cavium,octeon-3860-bootbus-config";
 499                                 cavium,cs-index = <5>;
 500                                 cavium,t-adr  = <0>;
 501                                 cavium,t-ce   = <300>;
 502                                 cavium,t-oe   = <125>;
 503                                 cavium,t-we   = <150>;
 504                                 cavium,t-rd-hld = <100>;
 505                                 cavium,t-wr-hld = <300>;
 506                                 cavium,t-pause  = <0>;
 507                                 cavium,t-wait   = <300>;
 508                                 cavium,t-page   = <310>;
 509                                 cavium,t-rd-dly = <0>;
 510
 511                                 cavium,pages     = <0>;
 512                                 cavium,bus-width = <16>;
 513                         };
 514                         cavium,cs-config@6 {
 515                                 compatible = "cavium,octeon-3860-bootbus-config";
 516                                 cavium,cs-index = <6>;
 517                                 cavium,t-adr  = <0>;
 518                                 cavium,t-ce   = <30>;
 519                                 cavium,t-oe   = <125>;
 520                                 cavium,t-we   = <150>;
 521                                 cavium,t-rd-hld = <100>;
 522                                 cavium,t-wr-hld = <30>;
 523                                 cavium,t-pause  = <0>;
 524                                 cavium,t-wait   = <30>;
 525                                 cavium,t-page   = <310>;
 526                                 cavium,t-rd-dly = <0>;
 527
 528                                 cavium,pages     = <0>;
 529                                 cavium,wait-mode;
 530                                 cavium,bus-width = <16>;
 531                         };
 532
 533                         flash0: nor@0,0 {
 534                                 compatible = "cfi-flash";
 535                                 reg = <0 0 0x800000>;
 536                                 #address-cells = <1>;
 537                                 #size-cells = <1>;
 538
 539                                 partition@0 {
 540                                         label = "bootloader";
 541                                         reg = <0 0x200000>;
 542                                         read-only;
 543                                 };
 544                                 partition@200000 {
 545                                         label = "kernel";
 546                                         reg = <0x200000 0x200000>;
 547                                 };
 548                                 partition@400000 {
 549                                         label = "cramfs";
 550                                         reg = <0x400000 0x3fe000>;
 551                                 };
 552                                 partition@7fe000 {
 553                                         label = "environment";
 554                                         reg = <0x7fe000 0x2000>;
 555                                         read-only;
 556                                 };
 557                         };
 558
 559                         led0: led-display@4,0 {
 560                                 compatible = "avago,hdsp-253x";
 561                                 reg = <4 0x20 0x20>, <4 0 0x20>;
 562                         };
 563
 564                         compact-flash@5,0 {
 565                                 compatible = "cavium,ebt3000-compact-flash";
 566                                 reg = <5 0 0x10000>, <6 0 0x10000>;
 567                                 cavium,bus-width = <16>;
 568                                 cavium,true-ide;
 569                                 cavium,dma-engine-handle = <&dma0>;
 570                         };
 571                 };
 572
 573                 dma0: dma-engine@1180000000100 {
 574                         compatible = "cavium,octeon-5750-bootbus-dma";
 575                         reg = <0x11800 0x00000100 0x0 0x8>;
 576                         interrupts = <0 63>;
 577                 };
 578                 dma1: dma-engine@1180000000108 {
 579                         compatible = "cavium,octeon-5750-bootbus-dma";
 580                         reg = <0x11800 0x00000108 0x0 0x8>;
 581                         interrupts = <0 63>;
 582                 };
 583
 584                 uctl: uctl@118006f000000 {
 585                         compatible = "cavium,octeon-6335-uctl";
 586                         reg = <0x11800 0x6f000000 0x0 0x100>;
 587                         ranges; /* Direct mapping */
 588                         #address-cells = <2>;
 589                         #size-cells = <2>;
 590                         /* 12MHz, 24MHz and 48MHz allowed */
 591                         refclk-frequency = <12000000>;
 592                         /* Either "crystal" or "external" */
 593                         refclk-type = "crystal";
 594
 595                         ehci@16f0000000000 {
 596                                 compatible = "cavium,octeon-6335-ehci","usb-ehci";
 597                                 reg = <0x16f00 0x00000000 0x0 0x100>;
 598                                 interrupts = <3 44>;
 599                                 big-endian-regs;
 600                         };
 601                         ohci@16f0000000400 {
 602                                 compatible = "cavium,octeon-6335-ohci","usb-ohci";
 603                                 reg = <0x16f00 0x00000400 0x0 0x100>;
 604                                 interrupts = <3 44>;
 605                                 big-endian-regs;
 606                         };
 607                 };
 608         };
 609
 610         aliases {
 611                 mix0 = &mix0;
 612                 pip = &pip;
 613                 smi0 = &smi0;
 614                 smi1 = &smi1;
 615                 smi2 = &smi2;
 616                 smi3 = &smi3;
 617                 twsi0 = &twsi0;
 618                 twsi1 = &twsi1;
 619                 uart0 = &uart0;
 620                 uart1 = &uart1;
 621                 uctl = &uctl;
 622                 led0 = &led0;
 623                 flash0 = &flash0;
 624         };
 625  };