arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi

   1 /*
   2  * Device Tree Source for PIC32MZDA clock data
   3  *
   4  * Purna Chandra Mandal <purna.mandal@microchip.com>
   5  * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
   6  *
   7  * Licensed under GPLv2 or later.
   8  */
   9
  10 /* all fixed rate clocks */
  11
  12 / {
  13         POSC:posc_clk { /* On-chip primary oscillator */
  14                 #clock-cells = <0>;
  15                 compatible = "fixed-clock";
  16                 clock-frequency = <24000000>;
  17         };
  18
  19         FRC:frc_clk { /* internal FRC oscillator */
  20                 #clock-cells = <0>;
  21                 compatible = "fixed-clock";
  22                 clock-frequency = <8000000>;
  23         };
  24
  25         BFRC:bfrc_clk { /* internal backup FRC oscillator */
  26                 #clock-cells = <0>;
  27                 compatible = "fixed-clock";
  28                 clock-frequency = <8000000>;
  29         };
  30
  31         LPRC:lprc_clk { /* internal low-power FRC oscillator */
  32                 #clock-cells = <0>;
  33                 compatible = "fixed-clock";
  34                 clock-frequency = <32000>;
  35         };
  36
  37         /* UPLL provides clock to USBCORE */
  38         UPLL:usb_phy_clk {
  39                 #clock-cells = <0>;
  40                 compatible = "fixed-clock";
  41                 clock-frequency = <24000000>;
  42                 clock-output-names = "usbphy_clk";
  43         };
  44
  45         TxCKI:txcki_clk { /* external clock input on TxCLKI pin */
  46                 #clock-cells = <0>;
  47                 compatible = "fixed-clock";
  48                 clock-frequency = <4000000>;
  49                 status = "disabled";
  50         };
  51
  52         /* external clock input on REFCLKIx pin */
  53         REFIx:refix_clk {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-clock";
  56                 clock-frequency = <24000000>;
  57                 status = "disabled";
  58         };
  59
  60         /* PIC32 specific clks */
  61         pic32_clktree {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 reg = <0x1f801200 0x200>;
  65                 compatible = "microchip,pic32mzda-clk";
  66                 ranges = <0 0x1f801200 0x200>;
  67
  68                 /* secondary oscillator; external input on SOSCI pin */
  69                 SOSC:sosc_clk@0 {
  70                         #clock-cells = <0>;
  71                         compatible = "microchip,pic32mzda-sosc";
  72                         clock-frequency = <32768>;
  73                         reg = <0x000 0x10>,   /* enable reg */
  74                               <0x1d0 0x10>; /* status reg */
  75                         microchip,bit-mask = <0x02>; /* enable mask */
  76                         microchip,status-bit-mask = <0x10>; /* status-mask*/
  77                 };
  78
  79                 FRCDIV:frcdiv_clk {
  80                         #clock-cells = <0>;
  81                         compatible = "microchip,pic32mzda-frcdivclk";
  82                         clocks = <&FRC>;
  83                         clock-output-names = "frcdiv_clk";
  84                 };
  85
  86                 /* System PLL clock */
  87                 SYSPLL:spll_clk@020 {
  88                         #clock-cells = <0>;
  89                         compatible = "microchip,pic32mzda-syspll";
  90                         reg = <0x020 0x10>, /* SPLL register */
  91                               <0x1d0 0x10>; /* CLKSTAT register */
  92                         clocks = <&POSC>, <&FRC>;
  93                         clock-output-names = "sys_pll";
  94                         microchip,status-bit-mask = <0x80>; /* SPLLRDY */
  95                 };
  96
  97                 /* system clock; mux with postdiv & slew */
  98                 SYSCLK:sys_clk@1c0 {
  99                         #clock-cells = <0>;
 100                         compatible = "microchip,pic32mzda-sysclk-v2";
 101                         reg = <0x1c0 0x04>; /* SLEWCON */
 102                         clocks = <&FRCDIV>, <&SYSPLL>, <&POSC>, <&SOSC>,
 103                                  <&LPRC>, <&FRCDIV>;
 104                         microchip,clock-indices = <0>, <1>, <2>, <4>,
 105                                                   <5>, <7>;
 106                         clock-output-names = "sys_clk";
 107                 };
 108
 109                 /* Peripheral bus1 clock */
 110                 PBCLK1:pb1_clk@140 {
 111                         reg = <0x140 0x10>;
 112                         #clock-cells = <0>;
 113                         compatible = "microchip,pic32mzda-pbclk";
 114                         clocks = <&SYSCLK>;
 115                         clock-output-names = "pb1_clk";
 116                         /* used by system modules, not gateable */
 117                         microchip,ignore-unused;
 118                 };
 119
 120                 /* Peripheral bus2 clock */
 121                 PBCLK2:pb2_clk@150 {
 122                         reg = <0x150 0x10>;
 123                         #clock-cells = <0>;
 124                         compatible = "microchip,pic32mzda-pbclk";
 125                         clocks = <&SYSCLK>;
 126                         clock-output-names = "pb2_clk";
 127                         /* avoid gating even if unused */
 128                         microchip,ignore-unused;
 129                 };
 130
 131                 /* Peripheral bus3 clock */
 132                 PBCLK3:pb3_clk@160 {
 133                         reg = <0x160 0x10>;
 134                         #clock-cells = <0>;
 135                         compatible = "microchip,pic32mzda-pbclk";
 136                         clocks = <&SYSCLK>;
 137                         clock-output-names = "pb3_clk";
 138                 };
 139
 140                 /* Peripheral bus4 clock(I/O ports, GPIO) */
 141                 PBCLK4:pb4_clk@170 {
 142                         reg = <0x170 0x10>;
 143                         #clock-cells = <0>;
 144                         compatible = "microchip,pic32mzda-pbclk";
 145                         clocks = <&SYSCLK>;
 146                         clock-output-names = "pb4_clk";
 147                 };
 148
 149                 /* Peripheral bus clock */
 150                 PBCLK5:pb5_clk@180 {
 151                         reg = <0x180 0x10>;
 152                         #clock-cells = <0>;
 153                         compatible = "microchip,pic32mzda-pbclk";
 154                         clocks = <&SYSCLK>;
 155                         clock-output-names = "pb5_clk";
 156                 };
 157
 158                 /* Peripheral Bus6 clock; */
 159                 PBCLK6:pb6_clk@190 {
 160                         reg = <0x190 0x10>;
 161                         compatible = "microchip,pic32mzda-pbclk";
 162                         clocks = <&SYSCLK>;
 163                         #clock-cells = <0>;
 164                 };
 165
 166                 /* Peripheral bus7 clock */
 167                 PBCLK7:pb7_clk@1a0 {
 168                         reg = <0x1a0 0x10>;
 169                         #clock-cells = <0>;
 170                         compatible = "microchip,pic32mzda-pbclk";
 171                         /* CPU is driven by this clock; so named */
 172                         clock-output-names = "cpu_clk";
 173                         clocks = <&SYSCLK>;
 174                 };
 175
 176                 /* Reference Oscillator clock for SPI/I2S */
 177                 REFCLKO1:refo1_clk@80 {
 178                         reg = <0x080 0x20>;
 179                         #clock-cells = <0>;
 180                         compatible = "microchip,pic32mzda-refoclk";
 181                         clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
 182                                  <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
 183                         microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
 184                                                   <5>, <7>, <8>, <9>;
 185                         clock-output-names = "refo1_clk";
 186                 };
 187
 188                 /* Reference Oscillator clock for SQI */
 189                 REFCLKO2:refo2_clk@a0 {
 190                         reg = <0x0a0 0x20>;
 191                         #clock-cells = <0>;
 192                         compatible = "microchip,pic32mzda-refoclk";
 193                         clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
 194                                  <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
 195                         microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
 196                                                   <5>, <7>, <8>, <9>;
 197                         clock-output-names = "refo2_clk";
 198                 };
 199
 200                 /* Reference Oscillator clock, ADC */
 201                 REFCLKO3:refo3_clk@c0 {
 202                         reg = <0x0c0 0x20>;
 203                         compatible = "microchip,pic32mzda-refoclk";
 204                         clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
 205                                  <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
 206                         microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
 207                                                   <5>, <7>, <8>, <9>;
 208                         #clock-cells = <0>;
 209                         clock-output-names = "refo3_clk";
 210                 };
 211
 212                 /* Reference Oscillator clock */
 213                 REFCLKO4:refo4_clk@e0 {
 214                         reg = <0x0e0 0x20>;
 215                         compatible = "microchip,pic32mzda-refoclk";
 216                         clocks = <&SYSCLK>, <&PBCLK1>, <&POSC>, <&FRC>, <&LPRC>,
 217                                  <&SOSC>, <&SYSPLL>, <&REFIx>, <&BFRC>;
 218                         microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
 219                                                   <5>, <7>, <8>, <9>;
 220                         #clock-cells = <0>;
 221                         clock-output-names = "refo4_clk";
 222                 };
 223
 224                 /* Reference Oscillator clock, LCD */
 225                 REFCLKO5:refo5_clk@100 {
 226                         reg = <0x100 0x20>;
 227                         compatible = "microchip,pic32mzda-refoclk";
 228                         clocks = <&SYSCLK>,<&PBCLK1>,<&POSC>,<&FRC>,<&LPRC>,
 229                                  <&SOSC>,<&SYSPLL>,<&REFIx>,<&BFRC>;
 230                         microchip,clock-indices = <0>, <1>, <2>, <3>, <4>,
 231                                                   <5>, <7>, <8>, <9>;
 232                         #clock-cells = <0>;
 233                         clock-output-names = "refo5_clk";
 234                 };
 235         };
 236 };