arch/m32r/lib/delay.c

   1 /*
   2  * linux/arch/m32r/lib/delay.c
   3  *
   4  * Copyright (c) 2002  Hitoshi Yamamoto, Hirokazu Takata
   5  * Copyright (c) 2004  Hirokazu Takata
   6  */
   7
   8 #include <linux/param.h>
   9 #ifdef CONFIG_SMP
  10 #include <linux/sched.h>
  11 #include <asm/current.h>
  12 #include <asm/smp.h>
  13 #endif  /* CONFIG_SMP */
  14 #include <asm/processor.h>
  15
  16 void __delay(unsigned long loops)
  17 {
  18 #ifdef CONFIG_ISA_DUAL_ISSUE
  19         __asm__ __volatile__ (
  20                 "beqz   %0, 2f                  \n\t"
  21                 "addi   %0, #-1                 \n\t"
  22
  23                 " .fillinsn                     \n\t"
  24                 "1:                             \n\t"
  25                 "cmpz   %0  ||  addi  %0, #-1   \n\t"
  26                 "bc     2f  ||  cmpz  %0        \n\t"
  27                 "bc     2f  ||  addi  %0, #-1   \n\t"
  28                 "cmpz   %0  ||  addi  %0, #-1   \n\t"
  29                 "bc     2f  ||  cmpz  %0        \n\t"
  30                 "bnc    1b  ||  addi  %0, #-1   \n\t"
  31                 " .fillinsn                     \n\t"
  32                 "2:                             \n\t"
  33                 : "+r" (loops)
  34                 : "r" (0)
  35                 : "cbit"
  36         );
  37 #else
  38         __asm__ __volatile__ (
  39                 "beqz   %0, 2f                  \n\t"
  40                 " .fillinsn                     \n\t"
  41                 "1:                             \n\t"
  42                 "addi   %0, #-1                 \n\t"
  43                 "blez   %0, 2f                  \n\t"
  44                 "addi   %0, #-1                 \n\t"
  45                 "blez   %0, 2f                  \n\t"
  46                 "addi   %0, #-1                 \n\t"
  47                 "blez   %0, 2f                  \n\t"
  48                 "addi   %0, #-1                 \n\t"
  49                 "bgtz   %0, 1b                  \n\t"
  50                 " .fillinsn                     \n\t"
  51                 "2:                             \n\t"
  52                 : "+r" (loops)
  53                 : "r" (0)
  54         );
  55 #endif
  56 }
  57
  58 void __const_udelay(unsigned long xloops)
  59 {
  60 #if defined(CONFIG_ISA_M32R2) && defined(CONFIG_ISA_DSP_LEVEL2)
  61         /*
  62          * loops [1] = (xloops >> 32) [sec] * loops_per_jiffy [1/jiffy]
  63          *            * HZ [jiffy/sec]
  64          *          = (xloops >> 32) [sec] * (loops_per_jiffy * HZ) [1/sec]
  65          *          = (((xloops * loops_per_jiffy) >> 32) * HZ) [1]
  66          *
  67          * NOTE:
  68          *   - '[]' depicts variable's dimension in the above equation.
  69          *   - "rac" instruction rounds the accumulator in word size.
  70          */
  71         __asm__ __volatile__ (
  72                 "srli   %0, #1                          \n\t"
  73                 "mulwhi %0, %1  ; a0                    \n\t"
  74                 "mulwu1 %0, %1  ; a1                    \n\t"
  75                 "sadd           ; a0 += (a1 >> 16)      \n\t"
  76                 "rac    a0, a0, #1                      \n\t"
  77                 "mvfacmi %0, a0                         \n\t"
  78                 : "+r" (xloops)
  79                 : "r" (current_cpu_data.loops_per_jiffy)
  80                 : "a0", "a1"
  81         );
  82 #elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
  83         /*
  84          * u64 ull;
  85          * ull = (u64)xloops * (u64)current_cpu_data.loops_per_jiffy;
  86          * xloops = (ull >> 32);
  87          */
  88         __asm__ __volatile__ (
  89                 "and3   r4, %0, #0xffff         \n\t"
  90                 "and3   r5, %1, #0xffff         \n\t"
  91                 "mul    r4, r5                  \n\t"
  92                 "srl3   r6, %0, #16             \n\t"
  93                 "srli   r4, #16                 \n\t"
  94                 "mul    r5, r6                  \n\t"
  95                 "add    r4, r5                  \n\t"
  96                 "and3   r5, %0, #0xffff         \n\t"
  97                 "srl3   r6, %1, #16             \n\t"
  98                 "mul    r5, r6                  \n\t"
  99                 "add    r4, r5                  \n\t"
 100                 "srl3   r5, %0, #16             \n\t"
 101                 "srli   r4, #16                 \n\t"
 102                 "mul    r5, r6                  \n\t"
 103                 "add    r4, r5                  \n\t"
 104                 "mv     %0, r4                  \n\t"
 105                 : "+r" (xloops)
 106                 : "r" (current_cpu_data.loops_per_jiffy)
 107                 : "r4", "r5", "r6"
 108         );
 109 #else
 110 #error unknown isa configuration
 111 #endif
 112         __delay(xloops * HZ);
 113 }
 114
 115 void __udelay(unsigned long usecs)
 116 {
 117         __const_udelay(usecs * 0x000010c7);  /* 2**32 / 1000000 (rounded up) */
 118 }
 119
 120 void __ndelay(unsigned long nsecs)
 121 {
 122         __const_udelay(nsecs * 0x00005);  /* 2**32 / 1000000000 (rounded up) */
 123 }