arch/i386/kernel/cpu/cpufreq/speedstep-lib.c

   1 /*
   2  * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
   3  *
   4  *  Licensed under the terms of the GNU GPL License version 2.
   5  *
   6  *  Library for common functions for Intel SpeedStep v.1 and v.2 support
   7  *
   8  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/init.h>
  15 #include <linux/cpufreq.h>
  16 #include <linux/pci.h>
  17 #include <linux/slab.h>
  18
  19 #include <asm/msr.h>
  20 #include "speedstep-lib.h"
  21
  22 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)
  23
  24 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
  25 static int relaxed_check = 0;
  26 #else
  27 #define relaxed_check 0
  28 #endif
  29
  30 /*********************************************************************
  31  *                   GET PROCESSOR CORE SPEED IN KHZ                 *
  32  *********************************************************************/
  33
  34 static unsigned int pentium3_get_frequency (unsigned int processor)
  35 {
  36         /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
  37         struct {
  38                 unsigned int ratio;     /* Frequency Multiplier (x10) */
  39                 u8 bitmap;              /* power on configuration bits
  40                                         [27, 25:22] (in MSR 0x2a) */
  41         } msr_decode_mult [] = {
  42                 { 30, 0x01 },
  43                 { 35, 0x05 },
  44                 { 40, 0x02 },
  45                 { 45, 0x06 },
  46                 { 50, 0x00 },
  47                 { 55, 0x04 },
  48                 { 60, 0x0b },
  49                 { 65, 0x0f },
  50                 { 70, 0x09 },
  51                 { 75, 0x0d },
  52                 { 80, 0x0a },
  53                 { 85, 0x26 },
  54                 { 90, 0x20 },
  55                 { 100, 0x2b },
  56                 { 0, 0xff }     /* error or unknown value */
  57         };
  58
  59         /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
  60         struct {
  61                 unsigned int value;     /* Front Side Bus speed in MHz */
  62                 u8 bitmap;              /* power on configuration bits [18: 19]
  63                                         (in MSR 0x2a) */
  64         } msr_decode_fsb [] = {
  65                 {  66, 0x0 },
  66                 { 100, 0x2 },
  67                 { 133, 0x1 },
  68                 {   0, 0xff}
  69         };
  70
  71         u32 msr_lo, msr_tmp;
  72         int i = 0, j = 0;
  73
  74         /* read MSR 0x2a - we only need the low 32 bits */
  75         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
  76         dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
  77         msr_tmp = msr_lo;
  78
  79         /* decode the FSB */
  80         msr_tmp &= 0x00c0000;
  81         msr_tmp >>= 18;
  82         while (msr_tmp != msr_decode_fsb[i].bitmap) {
  83                 if (msr_decode_fsb[i].bitmap == 0xff)
  84                         return 0;
  85                 i++;
  86         }
  87
  88         /* decode the multiplier */
  89         if (processor == SPEEDSTEP_PROCESSOR_PIII_C_EARLY) {
  90                 dprintk("workaround for early PIIIs\n");
  91                 msr_lo &= 0x03c00000;
  92         } else
  93                 msr_lo &= 0x0bc00000;
  94         msr_lo >>= 22;
  95         while (msr_lo != msr_decode_mult[j].bitmap) {
  96                 if (msr_decode_mult[j].bitmap == 0xff)
  97                         return 0;
  98                 j++;
  99         }
 100
 101         dprintk("speed is %u\n", (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
 102
 103         return (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100);
 104 }
 105
 106
 107 static unsigned int pentiumM_get_frequency(void)
 108 {
 109         u32 msr_lo, msr_tmp;
 110
 111         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 112         dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 113
 114         /* see table B-2 of 24547212.pdf */
 115         if (msr_lo & 0x00040000) {
 116                 printk(KERN_DEBUG "speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo, msr_tmp);
 117                 return 0;
 118         }
 119
 120         msr_tmp = (msr_lo >> 22) & 0x1f;
 121         dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * 100 * 1000));
 122
 123         return (msr_tmp * 100 * 1000);
 124 }
 125
 126 static unsigned int pentium_core_get_frequency(void)
 127 {
 128         u32 fsb = 0;
 129         u32 msr_lo, msr_tmp;
 130
 131         rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
 132         /* see table B-2 of 25366920.pdf */
 133         switch (msr_lo & 0x07) {
 134         case 5:
 135                 fsb = 100000;
 136                 break;
 137         case 1:
 138                 fsb = 133333;
 139                 break;
 140         case 3:
 141                 fsb = 166667;
 142                 break;
 143         default:
 144                 printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value");
 145         }
 146
 147         rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
 148         dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
 149
 150         msr_tmp = (msr_lo >> 22) & 0x1f;
 151         dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp, (msr_tmp * fsb));
 152
 153         return (msr_tmp * fsb);
 154 }
 155
 156
 157 static unsigned int pentium4_get_frequency(void)
 158 {
 159         struct cpuinfo_x86 *c = &boot_cpu_data;
 160         u32 msr_lo, msr_hi, mult;
 161         unsigned int fsb = 0;
 162
 163         rdmsr(0x2c, msr_lo, msr_hi);
 164
 165         dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
 166
 167         /* decode the FSB: see IA-32 Intel (C) Architecture Software
 168          * Developer's Manual, Volume 3: System Prgramming Guide,
 169          * revision #12 in Table B-1: MSRs in the Pentium 4 and
 170          * Intel Xeon Processors, on page B-4 and B-5.
 171          */
 172         if (c->x86_model < 2)
 173                 fsb = 100 * 1000;
 174         else {
 175                 u8 fsb_code = (msr_lo >> 16) & 0x7;
 176                 switch (fsb_code) {
 177                 case 0:
 178                         fsb = 100 * 1000;
 179                         break;
 180                 case 1:
 181                         fsb = 13333 * 10;
 182                         break;
 183                 case 2:
 184                         fsb = 200 * 1000;
 185                         break;
 186                 }
 187         }
 188
 189         if (!fsb)
 190                 printk(KERN_DEBUG "speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
 191
 192         /* Multiplier. */
 193         if (c->x86_model < 2)
 194                 mult = msr_lo >> 27;
 195         else
 196                 mult = msr_lo >> 24;
 197
 198         dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb, mult, (fsb * mult));
 199
 200         return (fsb * mult);
 201 }
 202
 203
 204 unsigned int speedstep_get_processor_frequency(unsigned int processor)
 205 {
 206         switch (processor) {
 207         case SPEEDSTEP_PROCESSOR_PCORE:
 208                 return pentium_core_get_frequency();
 209         case SPEEDSTEP_PROCESSOR_PM:
 210                 return pentiumM_get_frequency();
 211         case SPEEDSTEP_PROCESSOR_P4D:
 212         case SPEEDSTEP_PROCESSOR_P4M:
 213                 return pentium4_get_frequency();
 214         case SPEEDSTEP_PROCESSOR_PIII_T:
 215         case SPEEDSTEP_PROCESSOR_PIII_C:
 216         case SPEEDSTEP_PROCESSOR_PIII_C_EARLY:
 217                 return pentium3_get_frequency(processor);
 218         default:
 219                 return 0;
 220         };
 221         return 0;
 222 }
 223 EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency);
 224
 225
 226 /*********************************************************************
 227  *                 DETECT SPEEDSTEP-CAPABLE PROCESSOR                *
 228  *********************************************************************/
 229
 230 unsigned int speedstep_detect_processor (void)
 231 {
 232         struct cpuinfo_x86 *c = cpu_data;
 233         u32 ebx, msr_lo, msr_hi;
 234
 235         dprintk("x86: %x, model: %x\n", c->x86, c->x86_model);
 236
 237         if ((c->x86_vendor != X86_VENDOR_INTEL) ||
 238             ((c->x86 != 6) && (c->x86 != 0xF)))
 239                 return 0;
 240
 241         if (c->x86 == 0xF) {
 242                 /* Intel Mobile Pentium 4-M
 243                  * or Intel Mobile Pentium 4 with 533 MHz FSB */
 244                 if (c->x86_model != 2)
 245                         return 0;
 246
 247                 ebx = cpuid_ebx(0x00000001);
 248                 ebx &= 0x000000FF;
 249
 250                 dprintk("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
 251
 252                 switch (c->x86_mask) {
 253                 case 4:
 254                         /*
 255                          * B-stepping [M-P4-M]
 256                          * sample has ebx = 0x0f, production has 0x0e.
 257                          */
 258                         if ((ebx == 0x0e) || (ebx == 0x0f))
 259                                 return SPEEDSTEP_PROCESSOR_P4M;
 260                         break;
 261                 case 7:
 262                         /*
 263                          * C-stepping [M-P4-M]
 264                          * needs to have ebx=0x0e, else it's a celeron:
 265                          * cf. 25130917.pdf / page 7, footnote 5 even
 266                          * though 25072120.pdf / page 7 doesn't say
 267                          * samples are only of B-stepping...
 268                          */
 269                         if (ebx == 0x0e)
 270                                 return SPEEDSTEP_PROCESSOR_P4M;
 271                         break;
 272                 case 9:
 273                         /*
 274                          * D-stepping [M-P4-M or M-P4/533]
 275                          *
 276                          * this is totally strange: CPUID 0x0F29 is
 277                          * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
 278                          * The latter need to be sorted out as they don't
 279                          * support speedstep.
 280                          * Celerons with CPUID 0x0F29 may have either
 281                          * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
 282                          * specific.
 283                          * M-P4-Ms may have either ebx=0xe or 0xf [see above]
 284                          * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
 285                          * also, M-P4M HTs have ebx=0x8, too
 286                          * For now, they are distinguished by the model_id string
 287                          */
 288                         if ((ebx == 0x0e) || (strstr(c->x86_model_id,"Mobile Intel(R) Pentium(R) 4") != NULL))
 289                                 return SPEEDSTEP_PROCESSOR_P4M;
 290                         break;
 291                 default:
 292                         break;
 293                 }
 294                 return 0;
 295         }
 296
 297         switch (c->x86_model) {
 298         case 0x0B: /* Intel PIII [Tualatin] */
 299                 /* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
 300                 ebx = cpuid_ebx(0x00000001);
 301                 dprintk("ebx is %x\n", ebx);
 302
 303                 ebx &= 0x000000FF;
 304
 305                 if (ebx != 0x06)
 306                         return 0;
 307
 308                 /* So far all PIII-M processors support SpeedStep. See
 309                  * Intel's 24540640.pdf of June 2003
 310                  */
 311                 return SPEEDSTEP_PROCESSOR_PIII_T;
 312
 313         case 0x08: /* Intel PIII [Coppermine] */
 314
 315                 /* all mobile PIII Coppermines have FSB 100 MHz
 316                  * ==> sort out a few desktop PIIIs. */
 317                 rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
 318                 dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo, msr_hi);
 319                 msr_lo &= 0x00c0000;
 320                 if (msr_lo != 0x0080000)
 321                         return 0;
 322
 323                 /*
 324                  * If the processor is a mobile version,
 325                  * platform ID has bit 50 set
 326                  * it has SpeedStep technology if either
 327                  * bit 56 or 57 is set
 328                  */
 329                 rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
 330                 dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo, msr_hi);
 331                 if ((msr_hi & (1<<18)) && (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
 332                         if (c->x86_mask == 0x01) {
 333                                 dprintk("early PIII version\n");
 334                                 return SPEEDSTEP_PROCESSOR_PIII_C_EARLY;
 335                         } else
 336                                 return SPEEDSTEP_PROCESSOR_PIII_C;
 337                 }
 338
 339         default:
 340                 return 0;
 341         }
 342 }
 343 EXPORT_SYMBOL_GPL(speedstep_detect_processor);
 344
 345
 346 /*********************************************************************
 347  *                     DETECT SPEEDSTEP SPEEDS                       *
 348  *********************************************************************/
 349
 350 unsigned int speedstep_get_freqs(unsigned int processor,
 351                                   unsigned int *low_speed,
 352                                   unsigned int *high_speed,
 353                                   unsigned int *transition_latency,
 354                                   void (*set_state) (unsigned int state))
 355 {
 356         unsigned int prev_speed;
 357         unsigned int ret = 0;
 358         unsigned long flags;
 359         struct timeval tv1, tv2;
 360
 361         if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
 362                 return -EINVAL;
 363
 364         dprintk("trying to determine both speeds\n");
 365
 366         /* get current speed */
 367         prev_speed = speedstep_get_processor_frequency(processor);
 368         if (!prev_speed)
 369                 return -EIO;
 370
 371         dprintk("previous speed is %u\n", prev_speed);
 372
 373         local_irq_save(flags);
 374
 375         /* switch to low state */
 376         set_state(SPEEDSTEP_LOW);
 377         *low_speed = speedstep_get_processor_frequency(processor);
 378         if (!*low_speed) {
 379                 ret = -EIO;
 380                 goto out;
 381         }
 382
 383         dprintk("low speed is %u\n", *low_speed);
 384
 385         /* start latency measurement */
 386         if (transition_latency)
 387                 do_gettimeofday(&tv1);
 388
 389         /* switch to high state */
 390         set_state(SPEEDSTEP_HIGH);
 391
 392         /* end latency measurement */
 393         if (transition_latency)
 394                 do_gettimeofday(&tv2);
 395
 396         *high_speed = speedstep_get_processor_frequency(processor);
 397         if (!*high_speed) {
 398                 ret = -EIO;
 399                 goto out;
 400         }
 401
 402         dprintk("high speed is %u\n", *high_speed);
 403
 404         if (*low_speed == *high_speed) {
 405                 ret = -ENODEV;
 406                 goto out;
 407         }
 408
 409         /* switch to previous state, if necessary */
 410         if (*high_speed != prev_speed)
 411                 set_state(SPEEDSTEP_LOW);
 412
 413         if (transition_latency) {
 414                 *transition_latency = (tv2.tv_sec - tv1.tv_sec) * USEC_PER_SEC +
 415                         tv2.tv_usec - tv1.tv_usec;
 416                 dprintk("transition latency is %u uSec\n", *transition_latency);
 417
 418                 /* convert uSec to nSec and add 20% for safety reasons */
 419                 *transition_latency *= 1200;
 420
 421                 /* check if the latency measurement is too high or too low
 422                  * and set it to a safe value (500uSec) in that case
 423                  */
 424                 if (*transition_latency > 10000000 || *transition_latency < 50000) {
 425                         printk (KERN_WARNING "speedstep: frequency transition measured seems out of "
 426                                         "range (%u nSec), falling back to a safe one of %u nSec.\n",
 427                                         *transition_latency, 500000);
 428                         *transition_latency = 500000;
 429                 }
 430         }
 431
 432 out:
 433         local_irq_restore(flags);
 434         return (ret);
 435 }
 436 EXPORT_SYMBOL_GPL(speedstep_get_freqs);
 437
 438 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
 439 module_param(relaxed_check, int, 0444);
 440 MODULE_PARM_DESC(relaxed_check, "Don't do all checks for speedstep capability.");
 441 #endif
 442
 443 MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
 444 MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
 445 MODULE_LICENSE ("GPL");