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[linux-drm-fsl-dcu.git] / arch / avr32 / mach-at32ap / extint.c
1 /*
2  * External interrupt handling for AT32AP CPUs
3  *
4  * Copyright (C) 2006 Atmel Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10
11 #include <linux/errno.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/random.h>
17
18 #include <asm/io.h>
19
20 #include <asm/arch/sm.h>
21
22 #include "sm.h"
23
24 static void eim_ack_irq(unsigned int irq)
25 {
26         struct at32_sm *sm = get_irq_chip_data(irq);
27         sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
28 }
29
30 static void eim_mask_irq(unsigned int irq)
31 {
32         struct at32_sm *sm = get_irq_chip_data(irq);
33         sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
34 }
35
36 static void eim_mask_ack_irq(unsigned int irq)
37 {
38         struct at32_sm *sm = get_irq_chip_data(irq);
39         sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
40         sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
41 }
42
43 static void eim_unmask_irq(unsigned int irq)
44 {
45         struct at32_sm *sm = get_irq_chip_data(irq);
46         sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
47 }
48
49 static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
50 {
51         struct at32_sm *sm = get_irq_chip_data(irq);
52         struct irq_desc *desc;
53         unsigned int i = irq - sm->eim_first_irq;
54         u32 mode, edge, level;
55         unsigned long flags;
56         int ret = 0;
57
58         if (flow_type == IRQ_TYPE_NONE)
59                 flow_type = IRQ_TYPE_LEVEL_LOW;
60
61         desc = &irq_desc[irq];
62         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
63         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
64
65         if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
66                 desc->status |= IRQ_LEVEL;
67                 set_irq_handler(irq, handle_level_irq);
68         } else {
69                 set_irq_handler(irq, handle_edge_irq);
70         }
71
72         spin_lock_irqsave(&sm->lock, flags);
73
74         mode = sm_readl(sm, EIM_MODE);
75         edge = sm_readl(sm, EIM_EDGE);
76         level = sm_readl(sm, EIM_LEVEL);
77
78         switch (flow_type) {
79         case IRQ_TYPE_LEVEL_LOW:
80                 mode |= 1 << i;
81                 level &= ~(1 << i);
82                 break;
83         case IRQ_TYPE_LEVEL_HIGH:
84                 mode |= 1 << i;
85                 level |= 1 << i;
86                 break;
87         case IRQ_TYPE_EDGE_RISING:
88                 mode &= ~(1 << i);
89                 edge |= 1 << i;
90                 break;
91         case IRQ_TYPE_EDGE_FALLING:
92                 mode &= ~(1 << i);
93                 edge &= ~(1 << i);
94                 break;
95         default:
96                 ret = -EINVAL;
97                 break;
98         }
99
100         sm_writel(sm, EIM_MODE, mode);
101         sm_writel(sm, EIM_EDGE, edge);
102         sm_writel(sm, EIM_LEVEL, level);
103
104         spin_unlock_irqrestore(&sm->lock, flags);
105
106         return ret;
107 }
108
109 struct irq_chip eim_chip = {
110         .name           = "eim",
111         .ack            = eim_ack_irq,
112         .mask           = eim_mask_irq,
113         .mask_ack       = eim_mask_ack_irq,
114         .unmask         = eim_unmask_irq,
115         .set_type       = eim_set_irq_type,
116 };
117
118 static void demux_eim_irq(unsigned int irq, struct irq_desc *desc)
119 {
120         struct at32_sm *sm = desc->handler_data;
121         struct irq_desc *ext_desc;
122         unsigned long status, pending;
123         unsigned int i, ext_irq;
124
125         spin_lock(&sm->lock);
126
127         status = sm_readl(sm, EIM_ISR);
128         pending = status & sm_readl(sm, EIM_IMR);
129
130         while (pending) {
131                 i = fls(pending) - 1;
132                 pending &= ~(1 << i);
133
134                 ext_irq = i + sm->eim_first_irq;
135                 ext_desc = irq_desc + ext_irq;
136                 ext_desc->handle_irq(ext_irq, ext_desc);
137         }
138
139         spin_unlock(&sm->lock);
140 }
141
142 static int __init eim_init(void)
143 {
144         struct at32_sm *sm = &system_manager;
145         unsigned int i;
146         unsigned int nr_irqs;
147         unsigned int int_irq;
148         u32 pattern;
149
150         /*
151          * The EIM is really the same module as SM, so register
152          * mapping, etc. has been taken care of already.
153          */
154
155         /*
156          * Find out how many interrupt lines that are actually
157          * implemented in hardware.
158          */
159         sm_writel(sm, EIM_IDR, ~0UL);
160         sm_writel(sm, EIM_MODE, ~0UL);
161         pattern = sm_readl(sm, EIM_MODE);
162         nr_irqs = fls(pattern);
163
164         /* Trigger on falling edge unless overridden by driver */
165         sm_writel(sm, EIM_MODE, 0UL);
166         sm_writel(sm, EIM_EDGE, 0UL);
167
168         sm->eim_chip = &eim_chip;
169
170         for (i = 0; i < nr_irqs; i++) {
171                 set_irq_chip_and_handler(sm->eim_first_irq + i, &eim_chip,
172                                          handle_edge_irq);
173                 set_irq_chip_data(sm->eim_first_irq + i, sm);
174         }
175
176         int_irq = platform_get_irq_byname(sm->pdev, "eim");
177
178         set_irq_chained_handler(int_irq, demux_eim_irq);
179         set_irq_data(int_irq, sm);
180
181         printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
182                sm->regs, int_irq);
183         printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
184                nr_irqs, sm->eim_first_irq);
185
186         return 0;
187 }
188 arch_initcall(eim_init);