arch/avr32/mach-at32ap/at32ap7000.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/init.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/spi/spi.h>
  12
  13 #include <asm/io.h>
  14
  15 #include <asm/arch/at32ap7000.h>
  16 #include <asm/arch/board.h>
  17 #include <asm/arch/portmux.h>
  18 #include <asm/arch/sm.h>
  19
  20 #include "clock.h"
  21 #include "hmatrix.h"
  22 #include "pio.h"
  23 #include "sm.h"
  24
  25 #define PBMEM(base)                                     \
  26         {                                               \
  27                 .start          = base,                 \
  28                 .end            = base + 0x3ff,         \
  29                 .flags          = IORESOURCE_MEM,       \
  30         }
  31 #define IRQ(num)                                        \
  32         {                                               \
  33                 .start          = num,                  \
  34                 .end            = num,                  \
  35                 .flags          = IORESOURCE_IRQ,       \
  36         }
  37 #define NAMED_IRQ(num, _name)                           \
  38         {                                               \
  39                 .start          = num,                  \
  40                 .end            = num,                  \
  41                 .name           = _name,                \
  42                 .flags          = IORESOURCE_IRQ,       \
  43         }
  44
  45 #define DEFINE_DEV(_name, _id)                                  \
  46 static struct platform_device _name##_id##_device = {           \
  47         .name           = #_name,                               \
  48         .id             = _id,                                  \
  49         .resource       = _name##_id##_resource,                \
  50         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  51 }
  52 #define DEFINE_DEV_DATA(_name, _id)                             \
  53 static struct platform_device _name##_id##_device = {           \
  54         .name           = #_name,                               \
  55         .id             = _id,                                  \
  56         .dev            = {                                     \
  57                 .platform_data  = &_name##_id##_data,           \
  58         },                                                      \
  59         .resource       = _name##_id##_resource,                \
  60         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  61 }
  62
  63 #define select_peripheral(pin, periph, flags)                   \
  64         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  65
  66 #define DEV_CLK(_name, devname, bus, _index)                    \
  67 static struct clk devname##_##_name = {                         \
  68         .name           = #_name,                               \
  69         .dev            = &devname##_device.dev,                \
  70         .parent         = &bus##_clk,                           \
  71         .mode           = bus##_clk_mode,                       \
  72         .get_rate       = bus##_clk_get_rate,                   \
  73         .index          = _index,                               \
  74 }
  75
  76 unsigned long at32ap7000_osc_rates[3] = {
  77         [0] = 32768,
  78         /* FIXME: these are ATSTK1002-specific */
  79         [1] = 20000000,
  80         [2] = 12000000,
  81 };
  82
  83 static unsigned long osc_get_rate(struct clk *clk)
  84 {
  85         return at32ap7000_osc_rates[clk->index];
  86 }
  87
  88 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
  89 {
  90         unsigned long div, mul, rate;
  91
  92         if (!(control & SM_BIT(PLLEN)))
  93                 return 0;
  94
  95         div = SM_BFEXT(PLLDIV, control) + 1;
  96         mul = SM_BFEXT(PLLMUL, control) + 1;
  97
  98         rate = clk->parent->get_rate(clk->parent);
  99         rate = (rate + div / 2) / div;
 100         rate *= mul;
 101
 102         return rate;
 103 }
 104
 105 static unsigned long pll0_get_rate(struct clk *clk)
 106 {
 107         u32 control;
 108
 109         control = sm_readl(&system_manager, PM_PLL0);
 110
 111         return pll_get_rate(clk, control);
 112 }
 113
 114 static unsigned long pll1_get_rate(struct clk *clk)
 115 {
 116         u32 control;
 117
 118         control = sm_readl(&system_manager, PM_PLL1);
 119
 120         return pll_get_rate(clk, control);
 121 }
 122
 123 /*
 124  * The AT32AP7000 has five primary clock sources: One 32kHz
 125  * oscillator, two crystal oscillators and two PLLs.
 126  */
 127 static struct clk osc32k = {
 128         .name           = "osc32k",
 129         .get_rate       = osc_get_rate,
 130         .users          = 1,
 131         .index          = 0,
 132 };
 133 static struct clk osc0 = {
 134         .name           = "osc0",
 135         .get_rate       = osc_get_rate,
 136         .users          = 1,
 137         .index          = 1,
 138 };
 139 static struct clk osc1 = {
 140         .name           = "osc1",
 141         .get_rate       = osc_get_rate,
 142         .index          = 2,
 143 };
 144 static struct clk pll0 = {
 145         .name           = "pll0",
 146         .get_rate       = pll0_get_rate,
 147         .parent         = &osc0,
 148 };
 149 static struct clk pll1 = {
 150         .name           = "pll1",
 151         .get_rate       = pll1_get_rate,
 152         .parent         = &osc0,
 153 };
 154
 155 /*
 156  * The main clock can be either osc0 or pll0.  The boot loader may
 157  * have chosen one for us, so we don't really know which one until we
 158  * have a look at the SM.
 159  */
 160 static struct clk *main_clock;
 161
 162 /*
 163  * Synchronous clocks are generated from the main clock. The clocks
 164  * must satisfy the constraint
 165  *   fCPU >= fHSB >= fPB
 166  * i.e. each clock must not be faster than its parent.
 167  */
 168 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 169 {
 170         return main_clock->get_rate(main_clock) >> shift;
 171 };
 172
 173 static void cpu_clk_mode(struct clk *clk, int enabled)
 174 {
 175         struct at32_sm *sm = &system_manager;
 176         unsigned long flags;
 177         u32 mask;
 178
 179         spin_lock_irqsave(&sm->lock, flags);
 180         mask = sm_readl(sm, PM_CPU_MASK);
 181         if (enabled)
 182                 mask |= 1 << clk->index;
 183         else
 184                 mask &= ~(1 << clk->index);
 185         sm_writel(sm, PM_CPU_MASK, mask);
 186         spin_unlock_irqrestore(&sm->lock, flags);
 187 }
 188
 189 static unsigned long cpu_clk_get_rate(struct clk *clk)
 190 {
 191         unsigned long cksel, shift = 0;
 192
 193         cksel = sm_readl(&system_manager, PM_CKSEL);
 194         if (cksel & SM_BIT(CPUDIV))
 195                 shift = SM_BFEXT(CPUSEL, cksel) + 1;
 196
 197         return bus_clk_get_rate(clk, shift);
 198 }
 199
 200 static void hsb_clk_mode(struct clk *clk, int enabled)
 201 {
 202         struct at32_sm *sm = &system_manager;
 203         unsigned long flags;
 204         u32 mask;
 205
 206         spin_lock_irqsave(&sm->lock, flags);
 207         mask = sm_readl(sm, PM_HSB_MASK);
 208         if (enabled)
 209                 mask |= 1 << clk->index;
 210         else
 211                 mask &= ~(1 << clk->index);
 212         sm_writel(sm, PM_HSB_MASK, mask);
 213         spin_unlock_irqrestore(&sm->lock, flags);
 214 }
 215
 216 static unsigned long hsb_clk_get_rate(struct clk *clk)
 217 {
 218         unsigned long cksel, shift = 0;
 219
 220         cksel = sm_readl(&system_manager, PM_CKSEL);
 221         if (cksel & SM_BIT(HSBDIV))
 222                 shift = SM_BFEXT(HSBSEL, cksel) + 1;
 223
 224         return bus_clk_get_rate(clk, shift);
 225 }
 226
 227 static void pba_clk_mode(struct clk *clk, int enabled)
 228 {
 229         struct at32_sm *sm = &system_manager;
 230         unsigned long flags;
 231         u32 mask;
 232
 233         spin_lock_irqsave(&sm->lock, flags);
 234         mask = sm_readl(sm, PM_PBA_MASK);
 235         if (enabled)
 236                 mask |= 1 << clk->index;
 237         else
 238                 mask &= ~(1 << clk->index);
 239         sm_writel(sm, PM_PBA_MASK, mask);
 240         spin_unlock_irqrestore(&sm->lock, flags);
 241 }
 242
 243 static unsigned long pba_clk_get_rate(struct clk *clk)
 244 {
 245         unsigned long cksel, shift = 0;
 246
 247         cksel = sm_readl(&system_manager, PM_CKSEL);
 248         if (cksel & SM_BIT(PBADIV))
 249                 shift = SM_BFEXT(PBASEL, cksel) + 1;
 250
 251         return bus_clk_get_rate(clk, shift);
 252 }
 253
 254 static void pbb_clk_mode(struct clk *clk, int enabled)
 255 {
 256         struct at32_sm *sm = &system_manager;
 257         unsigned long flags;
 258         u32 mask;
 259
 260         spin_lock_irqsave(&sm->lock, flags);
 261         mask = sm_readl(sm, PM_PBB_MASK);
 262         if (enabled)
 263                 mask |= 1 << clk->index;
 264         else
 265                 mask &= ~(1 << clk->index);
 266         sm_writel(sm, PM_PBB_MASK, mask);
 267         spin_unlock_irqrestore(&sm->lock, flags);
 268 }
 269
 270 static unsigned long pbb_clk_get_rate(struct clk *clk)
 271 {
 272         unsigned long cksel, shift = 0;
 273
 274         cksel = sm_readl(&system_manager, PM_CKSEL);
 275         if (cksel & SM_BIT(PBBDIV))
 276                 shift = SM_BFEXT(PBBSEL, cksel) + 1;
 277
 278         return bus_clk_get_rate(clk, shift);
 279 }
 280
 281 static struct clk cpu_clk = {
 282         .name           = "cpu",
 283         .get_rate       = cpu_clk_get_rate,
 284         .users          = 1,
 285 };
 286 static struct clk hsb_clk = {
 287         .name           = "hsb",
 288         .parent         = &cpu_clk,
 289         .get_rate       = hsb_clk_get_rate,
 290 };
 291 static struct clk pba_clk = {
 292         .name           = "pba",
 293         .parent         = &hsb_clk,
 294         .mode           = hsb_clk_mode,
 295         .get_rate       = pba_clk_get_rate,
 296         .index          = 1,
 297 };
 298 static struct clk pbb_clk = {
 299         .name           = "pbb",
 300         .parent         = &hsb_clk,
 301         .mode           = hsb_clk_mode,
 302         .get_rate       = pbb_clk_get_rate,
 303         .users          = 1,
 304         .index          = 2,
 305 };
 306
 307 /* --------------------------------------------------------------------
 308  *  Generic Clock operations
 309  * -------------------------------------------------------------------- */
 310
 311 static void genclk_mode(struct clk *clk, int enabled)
 312 {
 313         u32 control;
 314
 315         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 316         if (enabled)
 317                 control |= SM_BIT(CEN);
 318         else
 319                 control &= ~SM_BIT(CEN);
 320         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
 321 }
 322
 323 static unsigned long genclk_get_rate(struct clk *clk)
 324 {
 325         u32 control;
 326         unsigned long div = 1;
 327
 328         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 329         if (control & SM_BIT(DIVEN))
 330                 div = 2 * (SM_BFEXT(DIV, control) + 1);
 331
 332         return clk->parent->get_rate(clk->parent) / div;
 333 }
 334
 335 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 336 {
 337         u32 control;
 338         unsigned long parent_rate, actual_rate, div;
 339
 340         parent_rate = clk->parent->get_rate(clk->parent);
 341         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 342
 343         if (rate > 3 * parent_rate / 4) {
 344                 actual_rate = parent_rate;
 345                 control &= ~SM_BIT(DIVEN);
 346         } else {
 347                 div = (parent_rate + rate) / (2 * rate) - 1;
 348                 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
 349                 actual_rate = parent_rate / (2 * (div + 1));
 350         }
 351
 352         printk("clk %s: new rate %lu (actual rate %lu)\n",
 353                clk->name, rate, actual_rate);
 354
 355         if (apply)
 356                 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
 357                           control);
 358
 359         return actual_rate;
 360 }
 361
 362 int genclk_set_parent(struct clk *clk, struct clk *parent)
 363 {
 364         u32 control;
 365
 366         printk("clk %s: new parent %s (was %s)\n",
 367                clk->name, parent->name, clk->parent->name);
 368
 369         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 370
 371         if (parent == &osc1 || parent == &pll1)
 372                 control |= SM_BIT(OSCSEL);
 373         else if (parent == &osc0 || parent == &pll0)
 374                 control &= ~SM_BIT(OSCSEL);
 375         else
 376                 return -EINVAL;
 377
 378         if (parent == &pll0 || parent == &pll1)
 379                 control |= SM_BIT(PLLSEL);
 380         else
 381                 control &= ~SM_BIT(PLLSEL);
 382
 383         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
 384         clk->parent = parent;
 385
 386         return 0;
 387 }
 388
 389 static void __init genclk_init_parent(struct clk *clk)
 390 {
 391         u32 control;
 392         struct clk *parent;
 393
 394         BUG_ON(clk->index > 7);
 395
 396         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 397         if (control & SM_BIT(OSCSEL))
 398                 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
 399         else
 400                 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
 401
 402         clk->parent = parent;
 403 }
 404
 405 /* --------------------------------------------------------------------
 406  *  System peripherals
 407  * -------------------------------------------------------------------- */
 408 static struct resource sm_resource[] = {
 409         PBMEM(0xfff00000),
 410         NAMED_IRQ(19, "eim"),
 411         NAMED_IRQ(20, "pm"),
 412         NAMED_IRQ(21, "rtc"),
 413 };
 414 struct platform_device at32_sm_device = {
 415         .name           = "sm",
 416         .id             = 0,
 417         .resource       = sm_resource,
 418         .num_resources  = ARRAY_SIZE(sm_resource),
 419 };
 420 static struct clk at32_sm_pclk = {
 421         .name           = "pclk",
 422         .dev            = &at32_sm_device.dev,
 423         .parent         = &pbb_clk,
 424         .mode           = pbb_clk_mode,
 425         .get_rate       = pbb_clk_get_rate,
 426         .users          = 1,
 427         .index          = 0,
 428 };
 429
 430 static struct resource intc0_resource[] = {
 431         PBMEM(0xfff00400),
 432 };
 433 struct platform_device at32_intc0_device = {
 434         .name           = "intc",
 435         .id             = 0,
 436         .resource       = intc0_resource,
 437         .num_resources  = ARRAY_SIZE(intc0_resource),
 438 };
 439 DEV_CLK(pclk, at32_intc0, pbb, 1);
 440
 441 static struct clk ebi_clk = {
 442         .name           = "ebi",
 443         .parent         = &hsb_clk,
 444         .mode           = hsb_clk_mode,
 445         .get_rate       = hsb_clk_get_rate,
 446         .users          = 1,
 447 };
 448 static struct clk hramc_clk = {
 449         .name           = "hramc",
 450         .parent         = &hsb_clk,
 451         .mode           = hsb_clk_mode,
 452         .get_rate       = hsb_clk_get_rate,
 453         .users          = 1,
 454         .index          = 3,
 455 };
 456
 457 static struct resource smc0_resource[] = {
 458         PBMEM(0xfff03400),
 459 };
 460 DEFINE_DEV(smc, 0);
 461 DEV_CLK(pclk, smc0, pbb, 13);
 462 DEV_CLK(mck, smc0, hsb, 0);
 463
 464 static struct platform_device pdc_device = {
 465         .name           = "pdc",
 466         .id             = 0,
 467 };
 468 DEV_CLK(hclk, pdc, hsb, 4);
 469 DEV_CLK(pclk, pdc, pba, 16);
 470
 471 static struct clk pico_clk = {
 472         .name           = "pico",
 473         .parent         = &cpu_clk,
 474         .mode           = cpu_clk_mode,
 475         .get_rate       = cpu_clk_get_rate,
 476         .users          = 1,
 477 };
 478
 479 /* --------------------------------------------------------------------
 480  * HMATRIX
 481  * -------------------------------------------------------------------- */
 482
 483 static struct clk hmatrix_clk = {
 484         .name           = "hmatrix_clk",
 485         .parent         = &pbb_clk,
 486         .mode           = pbb_clk_mode,
 487         .get_rate       = pbb_clk_get_rate,
 488         .index          = 2,
 489         .users          = 1,
 490 };
 491 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 492
 493 #define hmatrix_readl(reg)                                      \
 494         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 495 #define hmatrix_writel(reg,value)                               \
 496         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 497
 498 /*
 499  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 500  * External Bus Interface (EBI). This can be used to enable special
 501  * features like CompactFlash support, NAND Flash support, etc. on
 502  * certain chipselects.
 503  */
 504 static inline void set_ebi_sfr_bits(u32 mask)
 505 {
 506         u32 sfr;
 507
 508         clk_enable(&hmatrix_clk);
 509         sfr = hmatrix_readl(SFR4);
 510         sfr |= mask;
 511         hmatrix_writel(SFR4, sfr);
 512         clk_disable(&hmatrix_clk);
 513 }
 514
 515 /* --------------------------------------------------------------------
 516  *  System Timer/Counter (TC)
 517  * -------------------------------------------------------------------- */
 518 static struct resource at32_systc0_resource[] = {
 519         PBMEM(0xfff00c00),
 520         IRQ(22),
 521 };
 522 struct platform_device at32_systc0_device = {
 523         .name           = "systc",
 524         .id             = 0,
 525         .resource       = at32_systc0_resource,
 526         .num_resources  = ARRAY_SIZE(at32_systc0_resource),
 527 };
 528 DEV_CLK(pclk, at32_systc0, pbb, 3);
 529
 530 /* --------------------------------------------------------------------
 531  *  PIO
 532  * -------------------------------------------------------------------- */
 533
 534 static struct resource pio0_resource[] = {
 535         PBMEM(0xffe02800),
 536         IRQ(13),
 537 };
 538 DEFINE_DEV(pio, 0);
 539 DEV_CLK(mck, pio0, pba, 10);
 540
 541 static struct resource pio1_resource[] = {
 542         PBMEM(0xffe02c00),
 543         IRQ(14),
 544 };
 545 DEFINE_DEV(pio, 1);
 546 DEV_CLK(mck, pio1, pba, 11);
 547
 548 static struct resource pio2_resource[] = {
 549         PBMEM(0xffe03000),
 550         IRQ(15),
 551 };
 552 DEFINE_DEV(pio, 2);
 553 DEV_CLK(mck, pio2, pba, 12);
 554
 555 static struct resource pio3_resource[] = {
 556         PBMEM(0xffe03400),
 557         IRQ(16),
 558 };
 559 DEFINE_DEV(pio, 3);
 560 DEV_CLK(mck, pio3, pba, 13);
 561
 562 static struct resource pio4_resource[] = {
 563         PBMEM(0xffe03800),
 564         IRQ(17),
 565 };
 566 DEFINE_DEV(pio, 4);
 567 DEV_CLK(mck, pio4, pba, 14);
 568
 569 void __init at32_add_system_devices(void)
 570 {
 571         system_manager.eim_first_irq = EIM_IRQ_BASE;
 572
 573         platform_device_register(&at32_sm_device);
 574         platform_device_register(&at32_intc0_device);
 575         platform_device_register(&smc0_device);
 576         platform_device_register(&pdc_device);
 577
 578         platform_device_register(&at32_systc0_device);
 579
 580         platform_device_register(&pio0_device);
 581         platform_device_register(&pio1_device);
 582         platform_device_register(&pio2_device);
 583         platform_device_register(&pio3_device);
 584         platform_device_register(&pio4_device);
 585 }
 586
 587 /* --------------------------------------------------------------------
 588  *  USART
 589  * -------------------------------------------------------------------- */
 590
 591 static struct atmel_uart_data atmel_usart0_data = {
 592         .use_dma_tx     = 1,
 593         .use_dma_rx     = 1,
 594 };
 595 static struct resource atmel_usart0_resource[] = {
 596         PBMEM(0xffe00c00),
 597         IRQ(6),
 598 };
 599 DEFINE_DEV_DATA(atmel_usart, 0);
 600 DEV_CLK(usart, atmel_usart0, pba, 4);
 601
 602 static struct atmel_uart_data atmel_usart1_data = {
 603         .use_dma_tx     = 1,
 604         .use_dma_rx     = 1,
 605 };
 606 static struct resource atmel_usart1_resource[] = {
 607         PBMEM(0xffe01000),
 608         IRQ(7),
 609 };
 610 DEFINE_DEV_DATA(atmel_usart, 1);
 611 DEV_CLK(usart, atmel_usart1, pba, 4);
 612
 613 static struct atmel_uart_data atmel_usart2_data = {
 614         .use_dma_tx     = 1,
 615         .use_dma_rx     = 1,
 616 };
 617 static struct resource atmel_usart2_resource[] = {
 618         PBMEM(0xffe01400),
 619         IRQ(8),
 620 };
 621 DEFINE_DEV_DATA(atmel_usart, 2);
 622 DEV_CLK(usart, atmel_usart2, pba, 5);
 623
 624 static struct atmel_uart_data atmel_usart3_data = {
 625         .use_dma_tx     = 1,
 626         .use_dma_rx     = 1,
 627 };
 628 static struct resource atmel_usart3_resource[] = {
 629         PBMEM(0xffe01800),
 630         IRQ(9),
 631 };
 632 DEFINE_DEV_DATA(atmel_usart, 3);
 633 DEV_CLK(usart, atmel_usart3, pba, 6);
 634
 635 static inline void configure_usart0_pins(void)
 636 {
 637         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 638         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 639 }
 640
 641 static inline void configure_usart1_pins(void)
 642 {
 643         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 644         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 645 }
 646
 647 static inline void configure_usart2_pins(void)
 648 {
 649         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 650         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 651 }
 652
 653 static inline void configure_usart3_pins(void)
 654 {
 655         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 656         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 657 }
 658
 659 static struct platform_device *__initdata at32_usarts[4];
 660
 661 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 662 {
 663         struct platform_device *pdev;
 664
 665         switch (hw_id) {
 666         case 0:
 667                 pdev = &atmel_usart0_device;
 668                 configure_usart0_pins();
 669                 break;
 670         case 1:
 671                 pdev = &atmel_usart1_device;
 672                 configure_usart1_pins();
 673                 break;
 674         case 2:
 675                 pdev = &atmel_usart2_device;
 676                 configure_usart2_pins();
 677                 break;
 678         case 3:
 679                 pdev = &atmel_usart3_device;
 680                 configure_usart3_pins();
 681                 break;
 682         default:
 683                 return;
 684         }
 685
 686         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 687                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 688                 struct atmel_uart_data *data = pdev->dev.platform_data;
 689                 data->regs = (void __iomem *)pdev->resource[0].start;
 690         }
 691
 692         pdev->id = line;
 693         at32_usarts[line] = pdev;
 694 }
 695
 696 struct platform_device *__init at32_add_device_usart(unsigned int id)
 697 {
 698         platform_device_register(at32_usarts[id]);
 699         return at32_usarts[id];
 700 }
 701
 702 struct platform_device *atmel_default_console_device;
 703
 704 void __init at32_setup_serial_console(unsigned int usart_id)
 705 {
 706         atmel_default_console_device = at32_usarts[usart_id];
 707 }
 708
 709 /* --------------------------------------------------------------------
 710  *  Ethernet
 711  * -------------------------------------------------------------------- */
 712
 713 static struct eth_platform_data macb0_data;
 714 static struct resource macb0_resource[] = {
 715         PBMEM(0xfff01800),
 716         IRQ(25),
 717 };
 718 DEFINE_DEV_DATA(macb, 0);
 719 DEV_CLK(hclk, macb0, hsb, 8);
 720 DEV_CLK(pclk, macb0, pbb, 6);
 721
 722 static struct eth_platform_data macb1_data;
 723 static struct resource macb1_resource[] = {
 724         PBMEM(0xfff01c00),
 725         IRQ(26),
 726 };
 727 DEFINE_DEV_DATA(macb, 1);
 728 DEV_CLK(hclk, macb1, hsb, 9);
 729 DEV_CLK(pclk, macb1, pbb, 7);
 730
 731 struct platform_device *__init
 732 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 733 {
 734         struct platform_device *pdev;
 735
 736         switch (id) {
 737         case 0:
 738                 pdev = &macb0_device;
 739
 740                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 741                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 742                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 743                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 744                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 745                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 746                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 747                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 748                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 749                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 750
 751                 if (!data->is_rmii) {
 752                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 753                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 754                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 755                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 756                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 757                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 758                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 759                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 760                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 761                 }
 762                 break;
 763
 764         case 1:
 765                 pdev = &macb1_device;
 766
 767                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 768                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 769                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 770                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 771                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 772                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 773                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 774                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 775                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 776                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 777
 778                 if (!data->is_rmii) {
 779                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 780                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 781                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 782                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 783                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 784                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 785                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 786                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 787                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 788                 }
 789                 break;
 790
 791         default:
 792                 return NULL;
 793         }
 794
 795         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 796         platform_device_register(pdev);
 797
 798         return pdev;
 799 }
 800
 801 /* --------------------------------------------------------------------
 802  *  SPI
 803  * -------------------------------------------------------------------- */
 804 static struct resource atmel_spi0_resource[] = {
 805         PBMEM(0xffe00000),
 806         IRQ(3),
 807 };
 808 DEFINE_DEV(atmel_spi, 0);
 809 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 810
 811 static struct resource atmel_spi1_resource[] = {
 812         PBMEM(0xffe00400),
 813         IRQ(4),
 814 };
 815 DEFINE_DEV(atmel_spi, 1);
 816 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 817
 818 static void __init
 819 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 820                       unsigned int n, const u8 *pins)
 821 {
 822         unsigned int pin, mode;
 823
 824         for (; n; n--, b++) {
 825                 b->bus_num = bus_num;
 826                 if (b->chip_select >= 4)
 827                         continue;
 828                 pin = (unsigned)b->controller_data;
 829                 if (!pin) {
 830                         pin = pins[b->chip_select];
 831                         b->controller_data = (void *)pin;
 832                 }
 833                 mode = AT32_GPIOF_OUTPUT;
 834                 if (!(b->mode & SPI_CS_HIGH))
 835                         mode |= AT32_GPIOF_HIGH;
 836                 at32_select_gpio(pin, mode);
 837         }
 838 }
 839
 840 struct platform_device *__init
 841 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 842 {
 843         /*
 844          * Manage the chipselects as GPIOs, normally using the same pins
 845          * the SPI controller expects; but boards can use other pins.
 846          */
 847         static u8 __initdata spi0_pins[] =
 848                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 849                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 850         static u8 __initdata spi1_pins[] =
 851                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 852                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 853         struct platform_device *pdev;
 854
 855         switch (id) {
 856         case 0:
 857                 pdev = &atmel_spi0_device;
 858                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 859                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 860                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 861                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 862                 break;
 863
 864         case 1:
 865                 pdev = &atmel_spi1_device;
 866                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 867                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 868                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 869                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 870                 break;
 871
 872         default:
 873                 return NULL;
 874         }
 875
 876         spi_register_board_info(b, n);
 877         platform_device_register(pdev);
 878         return pdev;
 879 }
 880
 881 /* --------------------------------------------------------------------
 882  *  LCDC
 883  * -------------------------------------------------------------------- */
 884 static struct lcdc_platform_data lcdc0_data;
 885 static struct resource lcdc0_resource[] = {
 886         {
 887                 .start          = 0xff000000,
 888                 .end            = 0xff000fff,
 889                 .flags          = IORESOURCE_MEM,
 890         },
 891         IRQ(1),
 892 };
 893 DEFINE_DEV_DATA(lcdc, 0);
 894 DEV_CLK(hclk, lcdc0, hsb, 7);
 895 static struct clk lcdc0_pixclk = {
 896         .name           = "pixclk",
 897         .dev            = &lcdc0_device.dev,
 898         .mode           = genclk_mode,
 899         .get_rate       = genclk_get_rate,
 900         .set_rate       = genclk_set_rate,
 901         .set_parent     = genclk_set_parent,
 902         .index          = 7,
 903 };
 904
 905 struct platform_device *__init
 906 at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
 907 {
 908         struct platform_device *pdev;
 909
 910         switch (id) {
 911         case 0:
 912                 pdev = &lcdc0_device;
 913                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
 914                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
 915                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
 916                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
 917                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
 918                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
 919                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
 920                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
 921                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
 922                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
 923                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
 924                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
 925                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
 926                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
 927                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
 928                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
 929                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
 930                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
 931                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
 932                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
 933                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
 934                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
 935                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
 936                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
 937                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
 938                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
 939                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
 940                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
 941                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
 942                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
 943                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
 944
 945                 clk_set_parent(&lcdc0_pixclk, &pll0);
 946                 clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0));
 947                 break;
 948
 949         default:
 950                 return NULL;
 951         }
 952
 953         memcpy(pdev->dev.platform_data, data,
 954                sizeof(struct lcdc_platform_data));
 955
 956         platform_device_register(pdev);
 957         return pdev;
 958 }
 959
 960 /* --------------------------------------------------------------------
 961  *  GCLK
 962  * -------------------------------------------------------------------- */
 963 static struct clk gclk0 = {
 964         .name           = "gclk0",
 965         .mode           = genclk_mode,
 966         .get_rate       = genclk_get_rate,
 967         .set_rate       = genclk_set_rate,
 968         .set_parent     = genclk_set_parent,
 969         .index          = 0,
 970 };
 971 static struct clk gclk1 = {
 972         .name           = "gclk1",
 973         .mode           = genclk_mode,
 974         .get_rate       = genclk_get_rate,
 975         .set_rate       = genclk_set_rate,
 976         .set_parent     = genclk_set_parent,
 977         .index          = 1,
 978 };
 979 static struct clk gclk2 = {
 980         .name           = "gclk2",
 981         .mode           = genclk_mode,
 982         .get_rate       = genclk_get_rate,
 983         .set_rate       = genclk_set_rate,
 984         .set_parent     = genclk_set_parent,
 985         .index          = 2,
 986 };
 987 static struct clk gclk3 = {
 988         .name           = "gclk3",
 989         .mode           = genclk_mode,
 990         .get_rate       = genclk_get_rate,
 991         .set_rate       = genclk_set_rate,
 992         .set_parent     = genclk_set_parent,
 993         .index          = 3,
 994 };
 995 static struct clk gclk4 = {
 996         .name           = "gclk4",
 997         .mode           = genclk_mode,
 998         .get_rate       = genclk_get_rate,
 999         .set_rate       = genclk_set_rate,
1000         .set_parent     = genclk_set_parent,
1001         .index          = 4,
1002 };
1003
1004 struct clk *at32_clock_list[] = {
1005         &osc32k,
1006         &osc0,
1007         &osc1,
1008         &pll0,
1009         &pll1,
1010         &cpu_clk,
1011         &hsb_clk,
1012         &pba_clk,
1013         &pbb_clk,
1014         &at32_sm_pclk,
1015         &at32_intc0_pclk,
1016         &hmatrix_clk,
1017         &ebi_clk,
1018         &hramc_clk,
1019         &smc0_pclk,
1020         &smc0_mck,
1021         &pdc_hclk,
1022         &pdc_pclk,
1023         &pico_clk,
1024         &pio0_mck,
1025         &pio1_mck,
1026         &pio2_mck,
1027         &pio3_mck,
1028         &pio4_mck,
1029         &at32_systc0_pclk,
1030         &atmel_usart0_usart,
1031         &atmel_usart1_usart,
1032         &atmel_usart2_usart,
1033         &atmel_usart3_usart,
1034         &macb0_hclk,
1035         &macb0_pclk,
1036         &macb1_hclk,
1037         &macb1_pclk,
1038         &atmel_spi0_spi_clk,
1039         &atmel_spi1_spi_clk,
1040         &lcdc0_hclk,
1041         &lcdc0_pixclk,
1042         &gclk0,
1043         &gclk1,
1044         &gclk2,
1045         &gclk3,
1046         &gclk4,
1047 };
1048 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1049
1050 void __init at32_portmux_init(void)
1051 {
1052         at32_init_pio(&pio0_device);
1053         at32_init_pio(&pio1_device);
1054         at32_init_pio(&pio2_device);
1055         at32_init_pio(&pio3_device);
1056         at32_init_pio(&pio4_device);
1057 }
1058
1059 void __init at32_clock_init(void)
1060 {
1061         struct at32_sm *sm = &system_manager;
1062         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1063         int i;
1064
1065         if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
1066                 main_clock = &pll0;
1067         else
1068                 main_clock = &osc0;
1069
1070         if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
1071                 pll0.parent = &osc1;
1072         if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
1073                 pll1.parent = &osc1;
1074
1075         genclk_init_parent(&gclk0);
1076         genclk_init_parent(&gclk1);
1077         genclk_init_parent(&gclk2);
1078         genclk_init_parent(&gclk3);
1079         genclk_init_parent(&gclk4);
1080         genclk_init_parent(&lcdc0_pixclk);
1081
1082         /*
1083          * Turn on all clocks that have at least one user already, and
1084          * turn off everything else. We only do this for module
1085          * clocks, and even though it isn't particularly pretty to
1086          * check the address of the mode function, it should do the
1087          * trick...
1088          */
1089         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1090                 struct clk *clk = at32_clock_list[i];
1091
1092                 if (clk->users == 0)
1093                         continue;
1094
1095                 if (clk->mode == &cpu_clk_mode)
1096                         cpu_mask |= 1 << clk->index;
1097                 else if (clk->mode == &hsb_clk_mode)
1098                         hsb_mask |= 1 << clk->index;
1099                 else if (clk->mode == &pba_clk_mode)
1100                         pba_mask |= 1 << clk->index;
1101                 else if (clk->mode == &pbb_clk_mode)
1102                         pbb_mask |= 1 << clk->index;
1103         }
1104
1105         sm_writel(sm, PM_CPU_MASK, cpu_mask);
1106         sm_writel(sm, PM_HSB_MASK, hsb_mask);
1107         sm_writel(sm, PM_PBA_MASK, pba_mask);
1108         sm_writel(sm, PM_PBB_MASK, pbb_mask);
1109 }