3 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_GCOV_PROFILE_ALL
6 select ARCH_HAS_SG_CHAIN
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_USE_CMPXCHG_LOCKREF
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_WANT_OPTIONAL_GPIOLIB
11 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
12 select ARCH_WANT_FRAME_POINTERS
16 select AUDIT_ARCH_COMPAT_GENERIC
17 select ARM_GIC_V2M if PCI_MSI
19 select ARM_GIC_V3_ITS if PCI_MSI
20 select BUILDTIME_EXTABLE_SORT
21 select CLONE_BACKWARDS
23 select CPU_PM if (SUSPEND || CPU_IDLE)
24 select DCACHE_WORD_ACCESS
25 select GENERIC_ALLOCATOR
26 select GENERIC_CLOCKEVENTS
27 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
28 select GENERIC_CPU_AUTOPROBE
29 select GENERIC_EARLY_IOREMAP
30 select GENERIC_IRQ_PROBE
31 select GENERIC_IRQ_SHOW
32 select GENERIC_PCI_IOMAP
33 select GENERIC_SCHED_CLOCK
34 select GENERIC_SMP_IDLE_THREAD
35 select GENERIC_STRNCPY_FROM_USER
36 select GENERIC_STRNLEN_USER
37 select GENERIC_TIME_VSYSCALL
38 select HANDLE_DOMAIN_IRQ
39 select HARDIRQS_SW_RESEND
40 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
41 select HAVE_ARCH_AUDITSYSCALL
42 select HAVE_ARCH_JUMP_LABEL
44 select HAVE_ARCH_SECCOMP_FILTER
45 select HAVE_ARCH_TRACEHOOK
47 select HAVE_C_RECORDMCOUNT
48 select HAVE_CC_STACKPROTECTOR
49 select HAVE_CMPXCHG_DOUBLE
50 select HAVE_DEBUG_BUGVERBOSE
51 select HAVE_DEBUG_KMEMLEAK
52 select HAVE_DMA_API_DEBUG
54 select HAVE_DMA_CONTIGUOUS
55 select HAVE_DYNAMIC_FTRACE
56 select HAVE_EFFICIENT_UNALIGNED_ACCESS
57 select HAVE_FTRACE_MCOUNT_RECORD
58 select HAVE_FUNCTION_TRACER
59 select HAVE_FUNCTION_GRAPH_TRACER
60 select HAVE_GENERIC_DMA_COHERENT
61 select HAVE_HW_BREAKPOINT if PERF_EVENTS
63 select HAVE_PATA_PLATFORM
64 select HAVE_PERF_EVENTS
66 select HAVE_PERF_USER_STACK_DUMP
67 select HAVE_RCU_TABLE_FREE
68 select HAVE_SYSCALL_TRACEPOINTS
70 select MODULES_USE_ELF_RELA
73 select OF_EARLY_FLATTREE
74 select OF_RESERVED_MEM
75 select PERF_USE_VMALLOC
80 select SYSCTL_EXCEPTION_TRACE
81 select HAVE_CONTEXT_TRACKING
83 ARM 64-bit (AArch64) Linux support.
88 config ARCH_PHYS_ADDR_T_64BIT
97 config STACKTRACE_SUPPORT
100 config LOCKDEP_SUPPORT
103 config TRACE_IRQFLAGS_SUPPORT
106 config RWSEM_XCHGADD_ALGORITHM
109 config GENERIC_HWEIGHT
115 config GENERIC_CALIBRATE_DELAY
121 config HAVE_GENERIC_RCU_GUP
124 config ARCH_DMA_ADDR_T_64BIT
127 config NEED_DMA_MAP_STATE
130 config NEED_SG_DMA_LENGTH
139 config KERNEL_MODE_NEON
142 config FIX_EARLYCON_MEM
145 source "init/Kconfig"
147 source "kernel/Kconfig.freezer"
149 menu "Platform selection"
152 bool "AMD Seattle SoC Family"
154 This enables support for AMD Seattle SOC Family
157 bool "Cavium Inc. Thunder SoC Family"
159 This enables support for Cavium's Thunder Family of SoCs.
162 bool "ARMv8 software model (Versatile Express)"
163 select ARCH_REQUIRE_GPIOLIB
164 select COMMON_CLK_VERSATILE
165 select POWER_RESET_VEXPRESS
166 select VEXPRESS_CONFIG
168 This enables support for the ARMv8 software model (Versatile
172 bool "AppliedMicro X-Gene SOC Family"
174 This enables support for AppliedMicro X-Gene SOC Family
183 This feature enables support for PCI bus system. If you say Y
184 here, the kernel will include drivers and infrastructure code
185 to support PCI bus devices.
190 config PCI_DOMAINS_GENERIC
196 source "drivers/pci/Kconfig"
197 source "drivers/pci/pcie/Kconfig"
198 source "drivers/pci/hotplug/Kconfig"
202 menu "Kernel Features"
204 menu "ARM errata workarounds via the alternatives framework"
206 config ARM64_ERRATUM_826319
207 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
210 This option adds an alternative code sequence to work around ARM
211 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
212 AXI master interface and an L2 cache.
214 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
215 and is unable to accept a certain write via this interface, it will
216 not progress on read data presented on the read data channel and the
219 The workaround promotes data cache clean instructions to
220 data cache clean-and-invalidate.
221 Please note that this does not necessarily enable the workaround,
222 as it depends on the alternative framework, which will only patch
223 the kernel if an affected CPU is detected.
227 config ARM64_ERRATUM_827319
228 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
231 This option adds an alternative code sequence to work around ARM
232 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
233 master interface and an L2 cache.
235 Under certain conditions this erratum can cause a clean line eviction
236 to occur at the same time as another transaction to the same address
237 on the AMBA 5 CHI interface, which can cause data corruption if the
238 interconnect reorders the two transactions.
240 The workaround promotes data cache clean instructions to
241 data cache clean-and-invalidate.
242 Please note that this does not necessarily enable the workaround,
243 as it depends on the alternative framework, which will only patch
244 the kernel if an affected CPU is detected.
248 config ARM64_ERRATUM_824069
249 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
252 This option adds an alternative code sequence to work around ARM
253 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
254 to a coherent interconnect.
256 If a Cortex-A53 processor is executing a store or prefetch for
257 write instruction at the same time as a processor in another
258 cluster is executing a cache maintenance operation to the same
259 address, then this erratum might cause a clean cache line to be
260 incorrectly marked as dirty.
262 The workaround promotes data cache clean instructions to
263 data cache clean-and-invalidate.
264 Please note that this option does not necessarily enable the
265 workaround, as it depends on the alternative framework, which will
266 only patch the kernel if an affected CPU is detected.
270 config ARM64_ERRATUM_819472
271 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
274 This option adds an alternative code sequence to work around ARM
275 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
276 present when it is connected to a coherent interconnect.
278 If the processor is executing a load and store exclusive sequence at
279 the same time as a processor in another cluster is executing a cache
280 maintenance operation to the same address, then this erratum might
281 cause data corruption.
283 The workaround promotes data cache clean instructions to
284 data cache clean-and-invalidate.
285 Please note that this does not necessarily enable the workaround,
286 as it depends on the alternative framework, which will only patch
287 the kernel if an affected CPU is detected.
291 config ARM64_ERRATUM_832075
292 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
295 This option adds an alternative code sequence to work around ARM
296 erratum 832075 on Cortex-A57 parts up to r1p2.
298 Affected Cortex-A57 parts might deadlock when exclusive load/store
299 instructions to Write-Back memory are mixed with Device loads.
301 The workaround is to promote device loads to use Load-Acquire
303 Please note that this does not necessarily enable the workaround,
304 as it depends on the alternative framework, which will only patch
305 the kernel if an affected CPU is detected.
314 default ARM64_4K_PAGES
316 Page size (translation granule) configuration.
318 config ARM64_4K_PAGES
321 This feature enables 4KB pages support.
323 config ARM64_64K_PAGES
326 This feature enables 64KB pages support (4KB by default)
327 allowing only two levels of page tables and faster TLB
328 look-up. AArch32 emulation is not available when this feature
334 prompt "Virtual address space size"
335 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
336 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
338 Allows choosing one of multiple possible virtual address
339 space sizes. The level of translation table is determined by
340 a combination of page size and virtual address space size.
342 config ARM64_VA_BITS_39
344 depends on ARM64_4K_PAGES
346 config ARM64_VA_BITS_42
348 depends on ARM64_64K_PAGES
350 config ARM64_VA_BITS_48
357 default 39 if ARM64_VA_BITS_39
358 default 42 if ARM64_VA_BITS_42
359 default 48 if ARM64_VA_BITS_48
361 config ARM64_PGTABLE_LEVELS
363 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
364 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
365 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
366 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
368 config CPU_BIG_ENDIAN
369 bool "Build big-endian kernel"
371 Say Y if you plan on running a kernel in big-endian mode.
374 bool "Symmetric Multi-Processing"
376 This enables support for systems with more than one CPU. If
377 you say N here, the kernel will run on single and
378 multiprocessor machines, but will use only one CPU of a
379 multiprocessor machine. If you say Y here, the kernel will run
380 on many, but not all, single processor machines. On a single
381 processor machine, the kernel will run faster if you say N
384 If you don't know what to do here, say N.
387 bool "Multi-core scheduler support"
390 Multi-core scheduler support improves the CPU scheduler's decision
391 making when dealing with multi-core CPU chips at a cost of slightly
392 increased overhead in some places. If unsure say N here.
395 bool "SMT scheduler support"
398 Improves the CPU scheduler's decision making when dealing with
399 MultiThreading at a cost of slightly increased overhead in some
400 places. If unsure say N here.
403 int "Maximum number of CPUs (2-64)"
406 # These have to remain sorted largest to smallest
410 bool "Support for hot-pluggable CPUs"
413 Say Y here to experiment with turning CPUs off and on. CPUs
414 can be controlled through /sys/devices/system/cpu.
416 source kernel/Kconfig.preempt
422 config ARCH_HAS_HOLES_MEMORYMODEL
423 def_bool y if SPARSEMEM
425 config ARCH_SPARSEMEM_ENABLE
427 select SPARSEMEM_VMEMMAP_ENABLE
429 config ARCH_SPARSEMEM_DEFAULT
430 def_bool ARCH_SPARSEMEM_ENABLE
432 config ARCH_SELECT_MEMORY_MODEL
433 def_bool ARCH_SPARSEMEM_ENABLE
435 config HAVE_ARCH_PFN_VALID
436 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
438 config HW_PERF_EVENTS
439 bool "Enable hardware performance counter support for perf events"
440 depends on PERF_EVENTS
443 Enable hardware performance counter support for perf events. If
444 disabled, perf events will use software events only.
446 config SYS_SUPPORTS_HUGETLBFS
449 config ARCH_WANT_GENERAL_HUGETLB
452 config ARCH_WANT_HUGE_PMD_SHARE
453 def_bool y if !ARM64_64K_PAGES
455 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
458 config ARCH_HAS_CACHE_LINE_SIZE
464 bool "Enable seccomp to safely compute untrusted bytecode"
466 This kernel feature is useful for number crunching applications
467 that may need to compute untrusted bytecode during their
468 execution. By using pipes or other transports made available to
469 the process as file descriptors supporting the read/write
470 syscalls, it's possible to isolate those applications in
471 their own address space using seccomp. Once seccomp is
472 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
473 and the task is only allowed to execute a few safe syscalls
474 defined by each seccomp mode.
481 bool "Xen guest support on ARM64"
482 depends on ARM64 && OF
485 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
487 config FORCE_MAX_ZONEORDER
489 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
492 menuconfig ARMV8_DEPRECATED
493 bool "Emulate deprecated/obsolete ARMv8 instructions"
496 Legacy software support may require certain instructions
497 that have been deprecated or obsoleted in the architecture.
499 Enable this config to enable selective emulation of these
507 bool "Emulate SWP/SWPB instructions"
509 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
510 they are always undefined. Say Y here to enable software
511 emulation of these instructions for userspace using LDXR/STXR.
513 In some older versions of glibc [<=2.8] SWP is used during futex
514 trylock() operations with the assumption that the code will not
515 be preempted. This invalid assumption may be more likely to fail
516 with SWP emulation enabled, leading to deadlock of the user
519 NOTE: when accessing uncached shared regions, LDXR/STXR rely
520 on an external transaction monitoring block called a global
521 monitor to maintain update atomicity. If your system does not
522 implement a global monitor, this option can cause programs that
523 perform SWP operations to uncached memory to deadlock.
527 config CP15_BARRIER_EMULATION
528 bool "Emulate CP15 Barrier instructions"
530 The CP15 barrier instructions - CP15ISB, CP15DSB, and
531 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
532 strongly recommended to use the ISB, DSB, and DMB
533 instructions instead.
535 Say Y here to enable software emulation of these
536 instructions for AArch32 userspace code. When this option is
537 enabled, CP15 barrier usage is traced which can help
538 identify software that needs updating.
549 string "Default kernel command string"
552 Provide a set of default command-line options at build time by
553 entering them here. As a minimum, you should specify the the
554 root device (e.g. root=/dev/nfs).
557 bool "Always use the default kernel command string"
559 Always use the default kernel command string, even if the boot
560 loader passes other arguments to the kernel.
561 This is useful if you cannot or don't want to change the
562 command-line options your boot loader passes to the kernel.
568 bool "UEFI runtime support"
569 depends on OF && !CPU_BIG_ENDIAN
572 select EFI_PARAMS_FROM_FDT
573 select EFI_RUNTIME_WRAPPERS
578 This option provides support for runtime services provided
579 by UEFI firmware (such as non-volatile variables, realtime
580 clock, and platform reset). A UEFI stub is also provided to
581 allow the kernel to be booted as an EFI application. This
582 is only useful on systems that have UEFI firmware.
585 bool "Enable support for SMBIOS (DMI) tables"
589 This enables SMBIOS/DMI feature for systems.
591 This option is only useful on systems that have UEFI firmware.
592 However, even with this option, the resultant kernel should
593 continue to boot on existing non-UEFI platforms.
597 menu "Userspace binary formats"
599 source "fs/Kconfig.binfmt"
602 bool "Kernel support for 32-bit EL0"
603 depends on !ARM64_64K_PAGES
604 select COMPAT_BINFMT_ELF
606 select OLD_SIGSUSPEND3
607 select COMPAT_OLD_SIGACTION
609 This option enables support for a 32-bit EL0 running under a 64-bit
610 kernel at EL1. AArch32-specific components such as system calls,
611 the user helper functions, VFP support and the ptrace interface are
612 handled appropriately by the kernel.
614 If you want to execute 32-bit userspace applications, say Y.
616 config SYSVIPC_COMPAT
618 depends on COMPAT && SYSVIPC
622 menu "Power management options"
624 source "kernel/power/Kconfig"
626 config ARCH_SUSPEND_POSSIBLE
629 config ARM64_CPU_SUSPEND
634 menu "CPU Power Management"
636 source "drivers/cpuidle/Kconfig"
638 source "drivers/cpufreq/Kconfig"
644 source "drivers/Kconfig"
646 source "drivers/firmware/Kconfig"
650 source "arch/arm64/kvm/Kconfig"
652 source "arch/arm64/Kconfig.debug"
654 source "security/Kconfig"
656 source "crypto/Kconfig"
658 source "arch/arm64/crypto/Kconfig"