arch/arm/mach-vexpress/tc2_pm.c

   1 /*
   2  * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
   3  *
   4  * Created by:  Nicolas Pitre, October 2012
   5  * Copyright:   (C) 2012-2013  Linaro Limited
   6  *
   7  * Some portions of this file were originally written by Achin Gupta
   8  * Copyright:   (C) 2012  ARM Limited
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/kernel.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/errno.h>
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #include <asm/mcpm.h>
  25 #include <asm/proc-fns.h>
  26 #include <asm/cacheflush.h>
  27 #include <asm/cputype.h>
  28 #include <asm/cp15.h>
  29
  30 #include <linux/arm-cci.h>
  31
  32 #include "spc.h"
  33
  34 /* SCC conf registers */
  35 #define A15_CONF                0x400
  36 #define A7_CONF                 0x500
  37 #define SYS_INFO                0x700
  38 #define SPC_BASE                0xb00
  39
  40 /*
  41  * We can't use regular spinlocks. In the switcher case, it is possible
  42  * for an outbound CPU to call power_down() after its inbound counterpart
  43  * is already live using the same logical CPU number which trips lockdep
  44  * debugging.
  45  */
  46 static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
  47
  48 #define TC2_CLUSTERS                    2
  49 #define TC2_MAX_CPUS_PER_CLUSTER        3
  50
  51 static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
  52
  53 /* Keep per-cpu usage count to cope with unordered up/down requests */
  54 static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
  55
  56 #define tc2_cluster_unused(cluster) \
  57         (!tc2_pm_use_count[0][cluster] && \
  58          !tc2_pm_use_count[1][cluster] && \
  59          !tc2_pm_use_count[2][cluster])
  60
  61 static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
  62 {
  63         pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
  64         if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
  65                 return -EINVAL;
  66
  67         /*
  68          * Since this is called with IRQs enabled, and no arch_spin_lock_irq
  69          * variant exists, we need to disable IRQs manually here.
  70          */
  71         local_irq_disable();
  72         arch_spin_lock(&tc2_pm_lock);
  73
  74         if (tc2_cluster_unused(cluster))
  75                 ve_spc_powerdown(cluster, false);
  76
  77         tc2_pm_use_count[cpu][cluster]++;
  78         if (tc2_pm_use_count[cpu][cluster] == 1) {
  79                 ve_spc_set_resume_addr(cluster, cpu,
  80                                        virt_to_phys(mcpm_entry_point));
  81                 ve_spc_cpu_wakeup_irq(cluster, cpu, true);
  82         } else if (tc2_pm_use_count[cpu][cluster] != 2) {
  83                 /*
  84                  * The only possible values are:
  85                  * 0 = CPU down
  86                  * 1 = CPU (still) up
  87                  * 2 = CPU requested to be up before it had a chance
  88                  *     to actually make itself down.
  89                  * Any other value is a bug.
  90                  */
  91                 BUG();
  92         }
  93
  94         arch_spin_unlock(&tc2_pm_lock);
  95         local_irq_enable();
  96
  97         return 0;
  98 }
  99
 100 static void tc2_pm_down(u64 residency)
 101 {
 102         unsigned int mpidr, cpu, cluster;
 103         bool last_man = false, skip_wfi = false;
 104
 105         mpidr = read_cpuid_mpidr();
 106         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 107         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 108
 109         pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 110         BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
 111
 112         __mcpm_cpu_going_down(cpu, cluster);
 113
 114         arch_spin_lock(&tc2_pm_lock);
 115         BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
 116         tc2_pm_use_count[cpu][cluster]--;
 117         if (tc2_pm_use_count[cpu][cluster] == 0) {
 118                 ve_spc_cpu_wakeup_irq(cluster, cpu, true);
 119                 if (tc2_cluster_unused(cluster)) {
 120                         ve_spc_powerdown(cluster, true);
 121                         ve_spc_global_wakeup_irq(true);
 122                         last_man = true;
 123                 }
 124         } else if (tc2_pm_use_count[cpu][cluster] == 1) {
 125                 /*
 126                  * A power_up request went ahead of us.
 127                  * Even if we do not want to shut this CPU down,
 128                  * the caller expects a certain state as if the WFI
 129                  * was aborted.  So let's continue with cache cleaning.
 130                  */
 131                 skip_wfi = true;
 132         } else
 133                 BUG();
 134
 135         /*
 136          * If the CPU is committed to power down, make sure
 137          * the power controller will be in charge of waking it
 138          * up upon IRQ, ie IRQ lines are cut from GIC CPU IF
 139          * to the CPU by disabling the GIC CPU IF to prevent wfi
 140          * from completing execution behind power controller back
 141          */
 142         if (!skip_wfi)
 143                 gic_cpu_if_down();
 144
 145         if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
 146                 arch_spin_unlock(&tc2_pm_lock);
 147
 148                 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
 149                         /*
 150                          * On the Cortex-A15 we need to disable
 151                          * L2 prefetching before flushing the cache.
 152                          */
 153                         asm volatile(
 154                         "mcr    p15, 1, %0, c15, c0, 3 \n\t"
 155                         "isb    \n\t"
 156                         "dsb    "
 157                         : : "r" (0x400) );
 158                 }
 159
 160                 v7_exit_coherency_flush(all);
 161
 162                 cci_disable_port_by_cpu(mpidr);
 163
 164                 __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
 165         } else {
 166                 /*
 167                  * If last man then undo any setup done previously.
 168                  */
 169                 if (last_man) {
 170                         ve_spc_powerdown(cluster, false);
 171                         ve_spc_global_wakeup_irq(false);
 172                 }
 173
 174                 arch_spin_unlock(&tc2_pm_lock);
 175
 176                 v7_exit_coherency_flush(louis);
 177         }
 178
 179         __mcpm_cpu_down(cpu, cluster);
 180
 181         /* Now we are prepared for power-down, do it: */
 182         if (!skip_wfi)
 183                 wfi();
 184
 185         /* Not dead at this point?  Let our caller cope. */
 186 }
 187
 188 static void tc2_pm_power_down(void)
 189 {
 190         tc2_pm_down(0);
 191 }
 192
 193 static void tc2_pm_suspend(u64 residency)
 194 {
 195         unsigned int mpidr, cpu, cluster;
 196
 197         mpidr = read_cpuid_mpidr();
 198         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 199         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 200         ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
 201         tc2_pm_down(residency);
 202 }
 203
 204 static void tc2_pm_powered_up(void)
 205 {
 206         unsigned int mpidr, cpu, cluster;
 207         unsigned long flags;
 208
 209         mpidr = read_cpuid_mpidr();
 210         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 211         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 212
 213         pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 214         BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
 215
 216         local_irq_save(flags);
 217         arch_spin_lock(&tc2_pm_lock);
 218
 219         if (tc2_cluster_unused(cluster)) {
 220                 ve_spc_powerdown(cluster, false);
 221                 ve_spc_global_wakeup_irq(false);
 222         }
 223
 224         if (!tc2_pm_use_count[cpu][cluster])
 225                 tc2_pm_use_count[cpu][cluster] = 1;
 226
 227         ve_spc_cpu_wakeup_irq(cluster, cpu, false);
 228         ve_spc_set_resume_addr(cluster, cpu, 0);
 229
 230         arch_spin_unlock(&tc2_pm_lock);
 231         local_irq_restore(flags);
 232 }
 233
 234 static const struct mcpm_platform_ops tc2_pm_power_ops = {
 235         .power_up       = tc2_pm_power_up,
 236         .power_down     = tc2_pm_power_down,
 237         .suspend        = tc2_pm_suspend,
 238         .powered_up     = tc2_pm_powered_up,
 239 };
 240
 241 static bool __init tc2_pm_usage_count_init(void)
 242 {
 243         unsigned int mpidr, cpu, cluster;
 244
 245         mpidr = read_cpuid_mpidr();
 246         cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
 247         cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
 248
 249         pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
 250         if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
 251                 pr_err("%s: boot CPU is out of bound!\n", __func__);
 252                 return false;
 253         }
 254         tc2_pm_use_count[cpu][cluster] = 1;
 255         return true;
 256 }
 257
 258 /*
 259  * Enable cluster-level coherency, in preparation for turning on the MMU.
 260  */
 261 static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
 262 {
 263         asm volatile (" \n"
 264 "       cmp     r0, #1 \n"
 265 "       bxne    lr \n"
 266 "       b       cci_enable_port_for_self ");
 267 }
 268
 269 static int __init tc2_pm_init(void)
 270 {
 271         int ret, irq;
 272         void __iomem *scc;
 273         u32 a15_cluster_id, a7_cluster_id, sys_info;
 274         struct device_node *np;
 275
 276         /*
 277          * The power management-related features are hidden behind
 278          * SCC registers. We need to extract runtime information like
 279          * cluster ids and number of CPUs really available in clusters.
 280          */
 281         np = of_find_compatible_node(NULL, NULL,
 282                         "arm,vexpress-scc,v2p-ca15_a7");
 283         scc = of_iomap(np, 0);
 284         if (!scc)
 285                 return -ENODEV;
 286
 287         a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
 288         a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
 289         if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
 290                 return -EINVAL;
 291
 292         sys_info = readl_relaxed(scc + SYS_INFO);
 293         tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
 294         tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
 295
 296         irq = irq_of_parse_and_map(np, 0);
 297
 298         /*
 299          * A subset of the SCC registers is also used to communicate
 300          * with the SPC (power controller). We need to be able to
 301          * drive it very early in the boot process to power up
 302          * processors, so we initialize the SPC driver here.
 303          */
 304         ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id, irq);
 305         if (ret)
 306                 return ret;
 307
 308         if (!cci_probed())
 309                 return -ENODEV;
 310
 311         if (!tc2_pm_usage_count_init())
 312                 return -EINVAL;
 313
 314         ret = mcpm_platform_register(&tc2_pm_power_ops);
 315         if (!ret) {
 316                 mcpm_sync_init(tc2_pm_power_up_setup);
 317                 pr_info("TC2 power management initialized\n");
 318         }
 319         return ret;
 320 }
 321
 322 early_initcall(tc2_pm_init);