2 * drivers/powergate/tegra-powergate.c
4 * Copyright (c) 2010 Google, Inc
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/debugfs.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/export.h>
26 #include <linux/init.h>
28 #include <linux/seq_file.h>
29 #include <linux/spinlock.h>
30 #include <linux/clk/tegra.h>
31 #include <linux/tegra-powergate.h>
36 #define PWRGATE_TOGGLE 0x30
37 #define PWRGATE_TOGGLE_START (1 << 8)
39 #define REMOVE_CLAMPING 0x34
41 #define PWRGATE_STATUS 0x38
43 static int tegra_num_powerdomains;
44 static int tegra_num_cpu_domains;
45 static const u8 *tegra_cpu_domains;
47 static const u8 tegra30_cpu_domains[] = {
54 static const u8 tegra114_cpu_domains[] = {
61 static DEFINE_SPINLOCK(tegra_powergate_lock);
63 static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
65 static u32 pmc_read(unsigned long reg)
67 return readl(pmc + reg);
70 static void pmc_write(u32 val, unsigned long reg)
72 writel(val, pmc + reg);
75 static int tegra_powergate_set(int id, bool new_state)
80 spin_lock_irqsave(&tegra_powergate_lock, flags);
82 status = pmc_read(PWRGATE_STATUS) & (1 << id);
84 if (status == new_state) {
85 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
89 pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
91 spin_unlock_irqrestore(&tegra_powergate_lock, flags);
96 int tegra_powergate_power_on(int id)
98 if (id < 0 || id >= tegra_num_powerdomains)
101 return tegra_powergate_set(id, true);
104 int tegra_powergate_power_off(int id)
106 if (id < 0 || id >= tegra_num_powerdomains)
109 return tegra_powergate_set(id, false);
112 int tegra_powergate_is_powered(int id)
116 if (id < 0 || id >= tegra_num_powerdomains)
119 status = pmc_read(PWRGATE_STATUS) & (1 << id);
123 int tegra_powergate_remove_clamping(int id)
127 if (id < 0 || id >= tegra_num_powerdomains)
131 * Tegra 2 has a bug where PCIE and VDE clamping masks are
132 * swapped relatively to the partition ids
134 if (id == TEGRA_POWERGATE_VDEC)
135 mask = (1 << TEGRA_POWERGATE_PCIE);
136 else if (id == TEGRA_POWERGATE_PCIE)
137 mask = (1 << TEGRA_POWERGATE_VDEC);
141 pmc_write(mask, REMOVE_CLAMPING);
146 /* Must be called with clk disabled, and returns with clk enabled */
147 int tegra_powergate_sequence_power_up(int id, struct clk *clk)
151 tegra_periph_reset_assert(clk);
153 ret = tegra_powergate_power_on(id);
157 ret = clk_prepare_enable(clk);
163 ret = tegra_powergate_remove_clamping(id);
168 tegra_periph_reset_deassert(clk);
173 clk_disable_unprepare(clk);
175 tegra_powergate_power_off(id);
179 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
181 int tegra_cpu_powergate_id(int cpuid)
183 if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
184 return tegra_cpu_domains[cpuid];
189 int __init tegra_powergate_init(void)
191 switch (tegra_chip_id) {
193 tegra_num_powerdomains = 7;
196 tegra_num_powerdomains = 14;
197 tegra_num_cpu_domains = 4;
198 tegra_cpu_domains = tegra30_cpu_domains;
201 tegra_num_powerdomains = 23;
202 tegra_num_cpu_domains = 4;
203 tegra_cpu_domains = tegra114_cpu_domains;
206 /* Unknown Tegra variant. Disable powergating */
207 tegra_num_powerdomains = 0;
214 #ifdef CONFIG_DEBUG_FS
216 static const char * const *powergate_name;
218 static const char * const powergate_name_t20[] = {
219 [TEGRA_POWERGATE_CPU] = "cpu",
220 [TEGRA_POWERGATE_3D] = "3d",
221 [TEGRA_POWERGATE_VENC] = "venc",
222 [TEGRA_POWERGATE_VDEC] = "vdec",
223 [TEGRA_POWERGATE_PCIE] = "pcie",
224 [TEGRA_POWERGATE_L2] = "l2",
225 [TEGRA_POWERGATE_MPE] = "mpe",
228 static const char * const powergate_name_t30[] = {
229 [TEGRA_POWERGATE_CPU] = "cpu0",
230 [TEGRA_POWERGATE_3D] = "3d0",
231 [TEGRA_POWERGATE_VENC] = "venc",
232 [TEGRA_POWERGATE_VDEC] = "vdec",
233 [TEGRA_POWERGATE_PCIE] = "pcie",
234 [TEGRA_POWERGATE_L2] = "l2",
235 [TEGRA_POWERGATE_MPE] = "mpe",
236 [TEGRA_POWERGATE_HEG] = "heg",
237 [TEGRA_POWERGATE_SATA] = "sata",
238 [TEGRA_POWERGATE_CPU1] = "cpu1",
239 [TEGRA_POWERGATE_CPU2] = "cpu2",
240 [TEGRA_POWERGATE_CPU3] = "cpu3",
241 [TEGRA_POWERGATE_CELP] = "celp",
242 [TEGRA_POWERGATE_3D1] = "3d1",
245 static const char * const powergate_name_t114[] = {
246 [TEGRA_POWERGATE_CPU] = "cpu0",
247 [TEGRA_POWERGATE_3D] = "3d",
248 [TEGRA_POWERGATE_VENC] = "venc",
249 [TEGRA_POWERGATE_VDEC] = "vdec",
250 [TEGRA_POWERGATE_MPE] = "mpe",
251 [TEGRA_POWERGATE_HEG] = "heg",
252 [TEGRA_POWERGATE_CPU1] = "cpu1",
253 [TEGRA_POWERGATE_CPU2] = "cpu2",
254 [TEGRA_POWERGATE_CPU3] = "cpu3",
255 [TEGRA_POWERGATE_CELP] = "celp",
256 [TEGRA_POWERGATE_CPU0] = "cpu0",
257 [TEGRA_POWERGATE_C0NC] = "c0nc",
258 [TEGRA_POWERGATE_C1NC] = "c1nc",
259 [TEGRA_POWERGATE_DIS] = "dis",
260 [TEGRA_POWERGATE_DISB] = "disb",
261 [TEGRA_POWERGATE_XUSBA] = "xusba",
262 [TEGRA_POWERGATE_XUSBB] = "xusbb",
263 [TEGRA_POWERGATE_XUSBC] = "xusbc",
266 static int powergate_show(struct seq_file *s, void *data)
270 seq_printf(s, " powergate powered\n");
271 seq_printf(s, "------------------\n");
273 for (i = 0; i < tegra_num_powerdomains; i++) {
274 if (!powergate_name[i])
277 seq_printf(s, " %9s %7s\n", powergate_name[i],
278 tegra_powergate_is_powered(i) ? "yes" : "no");
284 static int powergate_open(struct inode *inode, struct file *file)
286 return single_open(file, powergate_show, inode->i_private);
289 static const struct file_operations powergate_fops = {
290 .open = powergate_open,
293 .release = single_release,
296 int __init tegra_powergate_debugfs_init(void)
300 switch (tegra_chip_id) {
302 powergate_name = powergate_name_t20;
305 powergate_name = powergate_name_t30;
308 powergate_name = powergate_name_t114;
312 if (powergate_name) {
313 d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,