arch/arm/mach-shmobile/setup-r8a7779.c

   1 /*
   2  * r8a7779 processor support
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irq.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/irqchip/arm-gic.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/platform_data/dma-rcar-hpbdma.h>
  25 #include <linux/platform_data/gpio-rcar.h>
  26 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/delay.h>
  29 #include <linux/input.h>
  30 #include <linux/io.h>
  31 #include <linux/serial_sci.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/dma-mapping.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/usb/hcd.h>
  36 #include <linux/usb/ehci_pdriver.h>
  37 #include <linux/usb/ohci_pdriver.h>
  38 #include <linux/pm_runtime.h>
  39
  40 #include <asm/mach-types.h>
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/time.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/hardware/cache-l2x0.h>
  45
  46 #include "common.h"
  47 #include "irqs.h"
  48 #include "r8a7779.h"
  49
  50 static struct map_desc r8a7779_io_desc[] __initdata = {
  51         /* 2M identity mapping for 0xf0000000 (MPCORE) */
  52         {
  53                 .virtual        = 0xf0000000,
  54                 .pfn            = __phys_to_pfn(0xf0000000),
  55                 .length         = SZ_2M,
  56                 .type           = MT_DEVICE_NONSHARED
  57         },
  58         /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  59         {
  60                 .virtual        = 0xfe000000,
  61                 .pfn            = __phys_to_pfn(0xfe000000),
  62                 .length         = SZ_16M,
  63                 .type           = MT_DEVICE_NONSHARED
  64         },
  65 };
  66
  67 void __init r8a7779_map_io(void)
  68 {
  69         debug_ll_io_init();
  70         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  71 }
  72
  73 /* IRQ */
  74 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
  75 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
  76 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
  77 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
  78 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
  79
  80 #define INT2NTSR0 IOMEM(0xfe700060)
  81 #define INT2NTSR1 IOMEM(0xfe700064)
  82
  83 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
  84         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
  85         .sense_bitfield_width = 2,
  86 };
  87
  88 static struct resource irqpin0_resources[] __initdata = {
  89         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
  90         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
  91         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
  92         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
  93         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
  94         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
  95         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
  96         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
  97         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
  98 };
  99
 100 void __init r8a7779_init_irq_extpin_dt(int irlm)
 101 {
 102         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 103         u32 tmp;
 104
 105         if (!icr0) {
 106                 pr_warn("r8a7779: unable to setup external irq pin mode\n");
 107                 return;
 108         }
 109
 110         tmp = ioread32(icr0);
 111         if (irlm)
 112                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 113         else
 114                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 115         tmp |= (1 << 21); /* LVLMODE = 1 */
 116         iowrite32(tmp, icr0);
 117         iounmap(icr0);
 118 }
 119
 120 void __init r8a7779_init_irq_extpin(int irlm)
 121 {
 122         r8a7779_init_irq_extpin_dt(irlm);
 123         if (irlm)
 124                 platform_device_register_resndata(
 125                         NULL, "renesas_intc_irqpin", -1,
 126                         irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
 127                         &irqpin0_platform_data, sizeof(irqpin0_platform_data));
 128 }
 129
 130 /* PFC/GPIO */
 131 static struct resource r8a7779_pfc_resources[] = {
 132         DEFINE_RES_MEM(0xfffc0000, 0x023c),
 133 };
 134
 135 static struct platform_device r8a7779_pfc_device = {
 136         .name           = "pfc-r8a7779",
 137         .id             = -1,
 138         .resource       = r8a7779_pfc_resources,
 139         .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
 140 };
 141
 142 #define R8A7779_GPIO(idx, npins) \
 143 static struct resource r8a7779_gpio##idx##_resources[] = {              \
 144         DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
 145         DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 146 };                                                                      \
 147                                                                         \
 148 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
 149         .gpio_base      = 32 * (idx),                                   \
 150         .irq_base       = 0,                                            \
 151         .number_of_pins = npins,                                        \
 152         .pctl_name      = "pfc-r8a7779",                                \
 153 };                                                                      \
 154                                                                         \
 155 static struct platform_device r8a7779_gpio##idx##_device = {            \
 156         .name           = "gpio_rcar",                                  \
 157         .id             = idx,                                          \
 158         .resource       = r8a7779_gpio##idx##_resources,                \
 159         .num_resources  = ARRAY_SIZE(r8a7779_gpio##idx##_resources),    \
 160         .dev            = {                                             \
 161                 .platform_data  = &r8a7779_gpio##idx##_platform_data,   \
 162         },                                                              \
 163 }
 164
 165 R8A7779_GPIO(0, 32);
 166 R8A7779_GPIO(1, 32);
 167 R8A7779_GPIO(2, 32);
 168 R8A7779_GPIO(3, 32);
 169 R8A7779_GPIO(4, 32);
 170 R8A7779_GPIO(5, 32);
 171 R8A7779_GPIO(6, 9);
 172
 173 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
 174         &r8a7779_pfc_device,
 175         &r8a7779_gpio0_device,
 176         &r8a7779_gpio1_device,
 177         &r8a7779_gpio2_device,
 178         &r8a7779_gpio3_device,
 179         &r8a7779_gpio4_device,
 180         &r8a7779_gpio5_device,
 181         &r8a7779_gpio6_device,
 182 };
 183
 184 void __init r8a7779_pinmux_init(void)
 185 {
 186         platform_add_devices(r8a7779_pinctrl_devices,
 187                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 188 }
 189
 190 /* SCIF */
 191 #define R8A7779_SCIF(index, baseaddr, irq)                      \
 192 static struct plat_sci_port scif##index##_platform_data = {     \
 193         .type           = PORT_SCIF,                            \
 194         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
 195         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
 196 };                                                              \
 197                                                                 \
 198 static struct resource scif##index##_resources[] = {            \
 199         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 200         DEFINE_RES_IRQ(irq),                                    \
 201 };                                                              \
 202                                                                 \
 203 static struct platform_device scif##index##_device = {          \
 204         .name           = "sh-sci",                             \
 205         .id             = index,                                \
 206         .resource       = scif##index##_resources,              \
 207         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 208         .dev            = {                                     \
 209                 .platform_data  = &scif##index##_platform_data, \
 210         },                                                      \
 211 }
 212
 213 R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
 214 R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
 215 R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
 216 R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
 217 R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
 218 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 219
 220 /* TMU */
 221 static struct sh_timer_config tmu0_platform_data = {
 222         .channels_mask = 7,
 223 };
 224
 225 static struct resource tmu0_resources[] = {
 226         DEFINE_RES_MEM(0xffd80000, 0x30),
 227         DEFINE_RES_IRQ(gic_iid(0x40)),
 228         DEFINE_RES_IRQ(gic_iid(0x41)),
 229         DEFINE_RES_IRQ(gic_iid(0x42)),
 230 };
 231
 232 static struct platform_device tmu0_device = {
 233         .name           = "sh-tmu",
 234         .id             = 0,
 235         .dev = {
 236                 .platform_data  = &tmu0_platform_data,
 237         },
 238         .resource       = tmu0_resources,
 239         .num_resources  = ARRAY_SIZE(tmu0_resources),
 240 };
 241
 242 /* I2C */
 243 static struct resource rcar_i2c0_res[] = {
 244         {
 245                 .start  = 0xffc70000,
 246                 .end    = 0xffc70fff,
 247                 .flags  = IORESOURCE_MEM,
 248         }, {
 249                 .start  = gic_iid(0x6f),
 250                 .flags  = IORESOURCE_IRQ,
 251         },
 252 };
 253
 254 static struct platform_device i2c0_device = {
 255         .name           = "i2c-rcar",
 256         .id             = 0,
 257         .resource       = rcar_i2c0_res,
 258         .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
 259 };
 260
 261 static struct resource rcar_i2c1_res[] = {
 262         {
 263                 .start  = 0xffc71000,
 264                 .end    = 0xffc71fff,
 265                 .flags  = IORESOURCE_MEM,
 266         }, {
 267                 .start  = gic_iid(0x72),
 268                 .flags  = IORESOURCE_IRQ,
 269         },
 270 };
 271
 272 static struct platform_device i2c1_device = {
 273         .name           = "i2c-rcar",
 274         .id             = 1,
 275         .resource       = rcar_i2c1_res,
 276         .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
 277 };
 278
 279 static struct resource rcar_i2c2_res[] = {
 280         {
 281                 .start  = 0xffc72000,
 282                 .end    = 0xffc72fff,
 283                 .flags  = IORESOURCE_MEM,
 284         }, {
 285                 .start  = gic_iid(0x70),
 286                 .flags  = IORESOURCE_IRQ,
 287         },
 288 };
 289
 290 static struct platform_device i2c2_device = {
 291         .name           = "i2c-rcar",
 292         .id             = 2,
 293         .resource       = rcar_i2c2_res,
 294         .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
 295 };
 296
 297 static struct resource rcar_i2c3_res[] = {
 298         {
 299                 .start  = 0xffc73000,
 300                 .end    = 0xffc73fff,
 301                 .flags  = IORESOURCE_MEM,
 302         }, {
 303                 .start  = gic_iid(0x71),
 304                 .flags  = IORESOURCE_IRQ,
 305         },
 306 };
 307
 308 static struct platform_device i2c3_device = {
 309         .name           = "i2c-rcar",
 310         .id             = 3,
 311         .resource       = rcar_i2c3_res,
 312         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 313 };
 314
 315 static struct resource sata_resources[] = {
 316         [0] = {
 317                 .name   = "rcar-sata",
 318                 .start  = 0xfc600000,
 319                 .end    = 0xfc601fff,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = gic_iid(0x84),
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 static struct platform_device sata_device = {
 329         .name           = "sata_rcar",
 330         .id             = -1,
 331         .resource       = sata_resources,
 332         .num_resources  = ARRAY_SIZE(sata_resources),
 333         .dev            = {
 334                 .dma_mask               = &sata_device.dev.coherent_dma_mask,
 335                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 336         },
 337 };
 338
 339 /* USB */
 340 static struct usb_phy *phy;
 341
 342 static int usb_power_on(struct platform_device *pdev)
 343 {
 344         if (IS_ERR(phy))
 345                 return PTR_ERR(phy);
 346
 347         pm_runtime_enable(&pdev->dev);
 348         pm_runtime_get_sync(&pdev->dev);
 349
 350         usb_phy_init(phy);
 351
 352         return 0;
 353 }
 354
 355 static void usb_power_off(struct platform_device *pdev)
 356 {
 357         if (IS_ERR(phy))
 358                 return;
 359
 360         usb_phy_shutdown(phy);
 361
 362         pm_runtime_put_sync(&pdev->dev);
 363         pm_runtime_disable(&pdev->dev);
 364 }
 365
 366 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 367 {
 368         /*
 369          * Below are recommended values from the datasheet;
 370          * see [USB :: Setting of EHCI Internal Buffer].
 371          */
 372         /* EHCI IP internal buffer setting */
 373         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 374         /* EHCI IP internal buffer enable */
 375         iowrite32(0x00000001, hcd->regs + 0x009C);
 376
 377         return 0;
 378 }
 379
 380 static struct usb_ehci_pdata ehcix_pdata = {
 381         .power_on       = usb_power_on,
 382         .power_off      = usb_power_off,
 383         .power_suspend  = usb_power_off,
 384         .pre_setup      = ehci_init_internal_buffer,
 385 };
 386
 387 static struct resource ehci0_resources[] = {
 388         [0] = {
 389                 .start  = 0xffe70000,
 390                 .end    = 0xffe70400 - 1,
 391                 .flags  = IORESOURCE_MEM,
 392         },
 393         [1] = {
 394                 .start  = gic_iid(0x4c),
 395                 .flags  = IORESOURCE_IRQ,
 396         },
 397 };
 398
 399 static struct platform_device ehci0_device = {
 400         .name   = "ehci-platform",
 401         .id     = 0,
 402         .dev    = {
 403                 .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
 404                 .coherent_dma_mask      = 0xffffffff,
 405                 .platform_data          = &ehcix_pdata,
 406         },
 407         .num_resources  = ARRAY_SIZE(ehci0_resources),
 408         .resource       = ehci0_resources,
 409 };
 410
 411 static struct resource ehci1_resources[] = {
 412         [0] = {
 413                 .start  = 0xfff70000,
 414                 .end    = 0xfff70400 - 1,
 415                 .flags  = IORESOURCE_MEM,
 416         },
 417         [1] = {
 418                 .start  = gic_iid(0x4d),
 419                 .flags  = IORESOURCE_IRQ,
 420         },
 421 };
 422
 423 static struct platform_device ehci1_device = {
 424         .name   = "ehci-platform",
 425         .id     = 1,
 426         .dev    = {
 427                 .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
 428                 .coherent_dma_mask      = 0xffffffff,
 429                 .platform_data          = &ehcix_pdata,
 430         },
 431         .num_resources  = ARRAY_SIZE(ehci1_resources),
 432         .resource       = ehci1_resources,
 433 };
 434
 435 static struct usb_ohci_pdata ohcix_pdata = {
 436         .power_on       = usb_power_on,
 437         .power_off      = usb_power_off,
 438         .power_suspend  = usb_power_off,
 439 };
 440
 441 static struct resource ohci0_resources[] = {
 442         [0] = {
 443                 .start  = 0xffe70400,
 444                 .end    = 0xffe70800 - 1,
 445                 .flags  = IORESOURCE_MEM,
 446         },
 447         [1] = {
 448                 .start  = gic_iid(0x4c),
 449                 .flags  = IORESOURCE_IRQ,
 450         },
 451 };
 452
 453 static struct platform_device ohci0_device = {
 454         .name   = "ohci-platform",
 455         .id     = 0,
 456         .dev    = {
 457                 .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
 458                 .coherent_dma_mask      = 0xffffffff,
 459                 .platform_data          = &ohcix_pdata,
 460         },
 461         .num_resources  = ARRAY_SIZE(ohci0_resources),
 462         .resource       = ohci0_resources,
 463 };
 464
 465 static struct resource ohci1_resources[] = {
 466         [0] = {
 467                 .start  = 0xfff70400,
 468                 .end    = 0xfff70800 - 1,
 469                 .flags  = IORESOURCE_MEM,
 470         },
 471         [1] = {
 472                 .start  = gic_iid(0x4d),
 473                 .flags  = IORESOURCE_IRQ,
 474         },
 475 };
 476
 477 static struct platform_device ohci1_device = {
 478         .name   = "ohci-platform",
 479         .id     = 1,
 480         .dev    = {
 481                 .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
 482                 .coherent_dma_mask      = 0xffffffff,
 483                 .platform_data          = &ohcix_pdata,
 484         },
 485         .num_resources  = ARRAY_SIZE(ohci1_resources),
 486         .resource       = ohci1_resources,
 487 };
 488
 489 /* HPB-DMA */
 490
 491 /* Asynchronous mode register bits */
 492 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
 493 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
 494 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
 495 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
 496 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
 497 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
 498 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
 499 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
 500 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
 501 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
 502 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
 503 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
 504 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
 505 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
 506 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
 507 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
 508 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
 509 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
 510 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
 511 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
 512 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
 513 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
 514 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
 515 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
 516 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
 517 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
 518 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
 519 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
 520 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
 521 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
 522 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
 523 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
 524 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
 525 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
 526 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
 527 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
 528 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
 529 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
 530 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
 531 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
 532 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
 533 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
 534 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
 535 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
 536 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
 537 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
 538 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
 539 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
 540 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
 541 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
 542 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
 543 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
 544 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
 545 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
 546 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
 547 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
 548 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
 549 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
 550 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
 551 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
 552 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
 553 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
 554 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
 555 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
 556 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
 557 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
 558 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
 559 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
 560 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
 561 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
 562 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
 563 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
 564
 565 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 566         {
 567                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 568                 .addr   = 0xffe4c000 + 0x30,
 569                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 570                           HPB_DMAE_DCR_DMDL |
 571                           HPB_DMAE_DCR_DPDS_16BIT,
 572                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 573                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 574                           HPB_DMAE_ASYNCRSTR_ASRST23,
 575                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
 576                           HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
 577                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
 578                           HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
 579                 .port   = 0x0D0C,
 580                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 581                 .dma_ch = 21,
 582         }, {
 583                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 584                 .addr   = 0xffe4c000 + 0x30,
 585                 .dcr    = HPB_DMAE_DCR_SMDL |
 586                           HPB_DMAE_DCR_SPDS_16BIT |
 587                           HPB_DMAE_DCR_DPDS_16BIT,
 588                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 589                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 590                           HPB_DMAE_ASYNCRSTR_ASRST23,
 591                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
 592                           HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
 593                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
 594                           HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
 595                 .port   = 0x0D0C,
 596                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 597                 .dma_ch = 22,
 598         },
 599 };
 600
 601 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 602         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 603         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 604 };
 605
 606 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 607         .slaves                 = hpb_dmae_slaves,
 608         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 609         .channels               = hpb_dmae_channels,
 610         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 611         .ts_shift               = {
 612                 [XMIT_SZ_8BIT]  = 0,
 613                 [XMIT_SZ_16BIT] = 1,
 614                 [XMIT_SZ_32BIT] = 2,
 615         },
 616         .num_hw_channels        = 44,
 617 };
 618
 619 static struct resource hpb_dmae_resources[] __initdata = {
 620         /* Channel registers */
 621         DEFINE_RES_MEM(0xffc08000, 0x1000),
 622         /* Common registers */
 623         DEFINE_RES_MEM(0xffc09000, 0x170),
 624         /* Asynchronous reset registers */
 625         DEFINE_RES_MEM(0xffc00300, 4),
 626         /* Asynchronous mode registers */
 627         DEFINE_RES_MEM(0xffc00400, 4),
 628         /* IRQ for DMA channels */
 629         DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
 630 };
 631
 632 static void __init r8a7779_register_hpb_dmae(void)
 633 {
 634         platform_device_register_resndata(NULL, "hpb-dma-engine",
 635                                           -1, hpb_dmae_resources,
 636                                           ARRAY_SIZE(hpb_dmae_resources),
 637                                           &dma_platform_data,
 638                                           sizeof(dma_platform_data));
 639 }
 640
 641 static struct platform_device *r8a7779_early_devices[] __initdata = {
 642         &tmu0_device,
 643 };
 644
 645 static struct platform_device *r8a7779_standard_devices[] __initdata = {
 646         &scif0_device,
 647         &scif1_device,
 648         &scif2_device,
 649         &scif3_device,
 650         &scif4_device,
 651         &scif5_device,
 652         &i2c0_device,
 653         &i2c1_device,
 654         &i2c2_device,
 655         &i2c3_device,
 656         &sata_device,
 657 };
 658
 659 void __init r8a7779_add_standard_devices(void)
 660 {
 661 #ifdef CONFIG_CACHE_L2X0
 662         /* Shared attribute override enable, 64K*16way */
 663         l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 664 #endif
 665         r8a7779_pm_init();
 666
 667         r8a7779_init_pm_domains();
 668
 669         platform_add_devices(r8a7779_early_devices,
 670                             ARRAY_SIZE(r8a7779_early_devices));
 671         platform_add_devices(r8a7779_standard_devices,
 672                             ARRAY_SIZE(r8a7779_standard_devices));
 673         r8a7779_register_hpb_dmae();
 674 }
 675
 676 void __init r8a7779_add_early_devices(void)
 677 {
 678         early_platform_add_devices(r8a7779_early_devices,
 679                                    ARRAY_SIZE(r8a7779_early_devices));
 680
 681         /* Early serial console setup is not included here due to
 682          * memory map collisions. The SCIF serial ports in r8a7779
 683          * are difficult to identity map 1:1 due to collision with the
 684          * virtual memory range used by the coherent DMA code on ARM.
 685          *
 686          * Anyone wanting to debug early can remove UPF_IOREMAP from
 687          * the sh-sci serial console platform data, adjust mapbase
 688          * to a static M:N virt:phys mapping that needs to be added to
 689          * the mappings passed with iotable_init() above.
 690          *
 691          * Then add a call to shmobile_setup_console() from this function.
 692          *
 693          * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
 694          * command line in case of the marzen board.
 695          */
 696 }
 697
 698 static struct platform_device *r8a7779_late_devices[] __initdata = {
 699         &ehci0_device,
 700         &ehci1_device,
 701         &ohci0_device,
 702         &ohci1_device,
 703 };
 704
 705 void __init r8a7779_init_late(void)
 706 {
 707         /* get USB PHY */
 708         phy = usb_get_phy(USB_PHY_TYPE_USB2);
 709
 710         shmobile_init_late();
 711         platform_add_devices(r8a7779_late_devices,
 712                              ARRAY_SIZE(r8a7779_late_devices));
 713 }
 714
 715 #ifdef CONFIG_USE_OF
 716 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 717 {
 718         return 0; /* always allow wakeup */
 719 }
 720
 721 void __init r8a7779_init_irq_dt(void)
 722 {
 723 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
 724         void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
 725         void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
 726 #endif
 727         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 728
 729 #ifdef CONFIG_ARCH_SHMOBILE_LEGACY
 730         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 731 #else
 732         irqchip_init();
 733 #endif
 734         /* route all interrupts to ARM */
 735         __raw_writel(0xffffffff, INT2NTSR0);
 736         __raw_writel(0x3fffffff, INT2NTSR1);
 737
 738         /* unmask all known interrupts in INTCS2 */
 739         __raw_writel(0xfffffff0, INT2SMSKCR0);
 740         __raw_writel(0xfff7ffff, INT2SMSKCR1);
 741         __raw_writel(0xfffbffdf, INT2SMSKCR2);
 742         __raw_writel(0xbffffffc, INT2SMSKCR3);
 743         __raw_writel(0x003fee3f, INT2SMSKCR4);
 744 }
 745
 746 #define MODEMR          0xffcc0020
 747
 748 u32 __init r8a7779_read_mode_pins(void)
 749 {
 750         static u32 mode;
 751         static bool mode_valid;
 752
 753         if (!mode_valid) {
 754                 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
 755                 BUG_ON(!modemr);
 756                 mode = ioread32(modemr);
 757                 iounmap(modemr);
 758                 mode_valid = true;
 759         }
 760
 761         return mode;
 762 }
 763
 764 static const char *r8a7779_compat_dt[] __initdata = {
 765         "renesas,r8a7779",
 766         NULL,
 767 };
 768
 769 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
 770         .map_io         = r8a7779_map_io,
 771         .init_early     = shmobile_init_delay,
 772         .init_irq       = r8a7779_init_irq_dt,
 773         .init_late      = shmobile_init_late,
 774         .dt_compat      = r8a7779_compat_dt,
 775 MACHINE_END
 776 #endif /* CONFIG_USE_OF */