arch/arm/mach-shmobile/setup-r8a7779.c

   1 /*
   2  * r8a7779 processor support
   3  *
   4  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_data/dma-rcar-hpbdma.h>
  29 #include <linux/platform_data/gpio-rcar.h>
  30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/delay.h>
  33 #include <linux/input.h>
  34 #include <linux/io.h>
  35 #include <linux/serial_sci.h>
  36 #include <linux/sh_timer.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/usb/otg.h>
  39 #include <linux/usb/hcd.h>
  40 #include <linux/usb/ehci_pdriver.h>
  41 #include <linux/usb/ohci_pdriver.h>
  42 #include <linux/pm_runtime.h>
  43 #include <mach/irqs.h>
  44 #include <mach/r8a7779.h>
  45 #include <mach/common.h>
  46 #include <asm/mach-types.h>
  47 #include <asm/mach/arch.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/map.h>
  50 #include <asm/hardware/cache-l2x0.h>
  51
  52 static struct map_desc r8a7779_io_desc[] __initdata = {
  53         /* 2M entity map for 0xf0000000 (MPCORE) */
  54         {
  55                 .virtual        = 0xf0000000,
  56                 .pfn            = __phys_to_pfn(0xf0000000),
  57                 .length         = SZ_2M,
  58                 .type           = MT_DEVICE_NONSHARED
  59         },
  60         /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
  61         {
  62                 .virtual        = 0xfe000000,
  63                 .pfn            = __phys_to_pfn(0xfe000000),
  64                 .length         = SZ_16M,
  65                 .type           = MT_DEVICE_NONSHARED
  66         },
  67 };
  68
  69 void __init r8a7779_map_io(void)
  70 {
  71         iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
  72 }
  73
  74 /* IRQ */
  75 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
  76 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
  77 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
  78 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
  79 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
  80
  81 #define INT2NTSR0 IOMEM(0xfe700060)
  82 #define INT2NTSR1 IOMEM(0xfe700064)
  83
  84 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
  85         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
  86         .sense_bitfield_width = 2,
  87 };
  88
  89 static struct resource irqpin0_resources[] __initdata = {
  90         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
  91         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
  92         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
  93         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
  94         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
  95         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
  96         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
  97         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
  98         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
  99 };
 100
 101 void __init r8a7779_init_irq_extpin_dt(int irlm)
 102 {
 103         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 104         u32 tmp;
 105
 106         if (!icr0) {
 107                 pr_warn("r8a7779: unable to setup external irq pin mode\n");
 108                 return;
 109         }
 110
 111         tmp = ioread32(icr0);
 112         if (irlm)
 113                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 114         else
 115                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 116         tmp |= (1 << 21); /* LVLMODE = 1 */
 117         iowrite32(tmp, icr0);
 118         iounmap(icr0);
 119 }
 120
 121 void __init r8a7779_init_irq_extpin(int irlm)
 122 {
 123         r8a7779_init_irq_extpin_dt(irlm);
 124         if (irlm)
 125                 platform_device_register_resndata(
 126                         &platform_bus, "renesas_intc_irqpin", -1,
 127                         irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
 128                         &irqpin0_platform_data, sizeof(irqpin0_platform_data));
 129 }
 130
 131 /* PFC/GPIO */
 132 static struct resource r8a7779_pfc_resources[] = {
 133         DEFINE_RES_MEM(0xfffc0000, 0x023c),
 134 };
 135
 136 static struct platform_device r8a7779_pfc_device = {
 137         .name           = "pfc-r8a7779",
 138         .id             = -1,
 139         .resource       = r8a7779_pfc_resources,
 140         .num_resources  = ARRAY_SIZE(r8a7779_pfc_resources),
 141 };
 142
 143 #define R8A7779_GPIO(idx, npins) \
 144 static struct resource r8a7779_gpio##idx##_resources[] = {              \
 145         DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
 146         DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 147 };                                                                      \
 148                                                                         \
 149 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
 150         .gpio_base      = 32 * (idx),                                   \
 151         .irq_base       = 0,                                            \
 152         .number_of_pins = npins,                                        \
 153         .pctl_name      = "pfc-r8a7779",                                \
 154 };                                                                      \
 155                                                                         \
 156 static struct platform_device r8a7779_gpio##idx##_device = {            \
 157         .name           = "gpio_rcar",                                  \
 158         .id             = idx,                                          \
 159         .resource       = r8a7779_gpio##idx##_resources,                \
 160         .num_resources  = ARRAY_SIZE(r8a7779_gpio##idx##_resources),    \
 161         .dev            = {                                             \
 162                 .platform_data  = &r8a7779_gpio##idx##_platform_data,   \
 163         },                                                              \
 164 }
 165
 166 R8A7779_GPIO(0, 32);
 167 R8A7779_GPIO(1, 32);
 168 R8A7779_GPIO(2, 32);
 169 R8A7779_GPIO(3, 32);
 170 R8A7779_GPIO(4, 32);
 171 R8A7779_GPIO(5, 32);
 172 R8A7779_GPIO(6, 9);
 173
 174 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
 175         &r8a7779_pfc_device,
 176         &r8a7779_gpio0_device,
 177         &r8a7779_gpio1_device,
 178         &r8a7779_gpio2_device,
 179         &r8a7779_gpio3_device,
 180         &r8a7779_gpio4_device,
 181         &r8a7779_gpio5_device,
 182         &r8a7779_gpio6_device,
 183 };
 184
 185 void __init r8a7779_pinmux_init(void)
 186 {
 187         platform_add_devices(r8a7779_pinctrl_devices,
 188                             ARRAY_SIZE(r8a7779_pinctrl_devices));
 189 }
 190
 191 static struct plat_sci_port scif0_platform_data = {
 192         .mapbase        = 0xffe40000,
 193         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 194         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 195         .scbrr_algo_id  = SCBRR_ALGO_2,
 196         .type           = PORT_SCIF,
 197         .irqs           = SCIx_IRQ_MUXED(gic_iid(0x78)),
 198 };
 199
 200 static struct platform_device scif0_device = {
 201         .name           = "sh-sci",
 202         .id             = 0,
 203         .dev            = {
 204                 .platform_data  = &scif0_platform_data,
 205         },
 206 };
 207
 208 static struct plat_sci_port scif1_platform_data = {
 209         .mapbase        = 0xffe41000,
 210         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 211         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 212         .scbrr_algo_id  = SCBRR_ALGO_2,
 213         .type           = PORT_SCIF,
 214         .irqs           = SCIx_IRQ_MUXED(gic_iid(0x79)),
 215 };
 216
 217 static struct platform_device scif1_device = {
 218         .name           = "sh-sci",
 219         .id             = 1,
 220         .dev            = {
 221                 .platform_data  = &scif1_platform_data,
 222         },
 223 };
 224
 225 static struct plat_sci_port scif2_platform_data = {
 226         .mapbase        = 0xffe42000,
 227         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 228         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 229         .scbrr_algo_id  = SCBRR_ALGO_2,
 230         .type           = PORT_SCIF,
 231         .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7a)),
 232 };
 233
 234 static struct platform_device scif2_device = {
 235         .name           = "sh-sci",
 236         .id             = 2,
 237         .dev            = {
 238                 .platform_data  = &scif2_platform_data,
 239         },
 240 };
 241
 242 static struct plat_sci_port scif3_platform_data = {
 243         .mapbase        = 0xffe43000,
 244         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 245         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 246         .scbrr_algo_id  = SCBRR_ALGO_2,
 247         .type           = PORT_SCIF,
 248         .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7b)),
 249 };
 250
 251 static struct platform_device scif3_device = {
 252         .name           = "sh-sci",
 253         .id             = 3,
 254         .dev            = {
 255                 .platform_data  = &scif3_platform_data,
 256         },
 257 };
 258
 259 static struct plat_sci_port scif4_platform_data = {
 260         .mapbase        = 0xffe44000,
 261         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 262         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 263         .scbrr_algo_id  = SCBRR_ALGO_2,
 264         .type           = PORT_SCIF,
 265         .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7c)),
 266 };
 267
 268 static struct platform_device scif4_device = {
 269         .name           = "sh-sci",
 270         .id             = 4,
 271         .dev            = {
 272                 .platform_data  = &scif4_platform_data,
 273         },
 274 };
 275
 276 static struct plat_sci_port scif5_platform_data = {
 277         .mapbase        = 0xffe45000,
 278         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
 279         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
 280         .scbrr_algo_id  = SCBRR_ALGO_2,
 281         .type           = PORT_SCIF,
 282         .irqs           = SCIx_IRQ_MUXED(gic_iid(0x7d)),
 283 };
 284
 285 static struct platform_device scif5_device = {
 286         .name           = "sh-sci",
 287         .id             = 5,
 288         .dev            = {
 289                 .platform_data  = &scif5_platform_data,
 290         },
 291 };
 292
 293 /* TMU */
 294 static struct sh_timer_config tmu00_platform_data = {
 295         .name = "TMU00",
 296         .channel_offset = 0x4,
 297         .timer_bit = 0,
 298         .clockevent_rating = 200,
 299 };
 300
 301 static struct resource tmu00_resources[] = {
 302         [0] = {
 303                 .name   = "TMU00",
 304                 .start  = 0xffd80008,
 305                 .end    = 0xffd80013,
 306                 .flags  = IORESOURCE_MEM,
 307         },
 308         [1] = {
 309                 .start  = gic_iid(0x40),
 310                 .flags  = IORESOURCE_IRQ,
 311         },
 312 };
 313
 314 static struct platform_device tmu00_device = {
 315         .name           = "sh_tmu",
 316         .id             = 0,
 317         .dev = {
 318                 .platform_data  = &tmu00_platform_data,
 319         },
 320         .resource       = tmu00_resources,
 321         .num_resources  = ARRAY_SIZE(tmu00_resources),
 322 };
 323
 324 static struct sh_timer_config tmu01_platform_data = {
 325         .name = "TMU01",
 326         .channel_offset = 0x10,
 327         .timer_bit = 1,
 328         .clocksource_rating = 200,
 329 };
 330
 331 static struct resource tmu01_resources[] = {
 332         [0] = {
 333                 .name   = "TMU01",
 334                 .start  = 0xffd80014,
 335                 .end    = 0xffd8001f,
 336                 .flags  = IORESOURCE_MEM,
 337         },
 338         [1] = {
 339                 .start  = gic_iid(0x41),
 340                 .flags  = IORESOURCE_IRQ,
 341         },
 342 };
 343
 344 static struct platform_device tmu01_device = {
 345         .name           = "sh_tmu",
 346         .id             = 1,
 347         .dev = {
 348                 .platform_data  = &tmu01_platform_data,
 349         },
 350         .resource       = tmu01_resources,
 351         .num_resources  = ARRAY_SIZE(tmu01_resources),
 352 };
 353
 354 /* I2C */
 355 static struct resource rcar_i2c0_res[] = {
 356         {
 357                 .start  = 0xffc70000,
 358                 .end    = 0xffc70fff,
 359                 .flags  = IORESOURCE_MEM,
 360         }, {
 361                 .start  = gic_iid(0x6f),
 362                 .flags  = IORESOURCE_IRQ,
 363         },
 364 };
 365
 366 static struct platform_device i2c0_device = {
 367         .name           = "i2c-rcar",
 368         .id             = 0,
 369         .resource       = rcar_i2c0_res,
 370         .num_resources  = ARRAY_SIZE(rcar_i2c0_res),
 371 };
 372
 373 static struct resource rcar_i2c1_res[] = {
 374         {
 375                 .start  = 0xffc71000,
 376                 .end    = 0xffc71fff,
 377                 .flags  = IORESOURCE_MEM,
 378         }, {
 379                 .start  = gic_iid(0x72),
 380                 .flags  = IORESOURCE_IRQ,
 381         },
 382 };
 383
 384 static struct platform_device i2c1_device = {
 385         .name           = "i2c-rcar",
 386         .id             = 1,
 387         .resource       = rcar_i2c1_res,
 388         .num_resources  = ARRAY_SIZE(rcar_i2c1_res),
 389 };
 390
 391 static struct resource rcar_i2c2_res[] = {
 392         {
 393                 .start  = 0xffc72000,
 394                 .end    = 0xffc72fff,
 395                 .flags  = IORESOURCE_MEM,
 396         }, {
 397                 .start  = gic_iid(0x70),
 398                 .flags  = IORESOURCE_IRQ,
 399         },
 400 };
 401
 402 static struct platform_device i2c2_device = {
 403         .name           = "i2c-rcar",
 404         .id             = 2,
 405         .resource       = rcar_i2c2_res,
 406         .num_resources  = ARRAY_SIZE(rcar_i2c2_res),
 407 };
 408
 409 static struct resource rcar_i2c3_res[] = {
 410         {
 411                 .start  = 0xffc73000,
 412                 .end    = 0xffc73fff,
 413                 .flags  = IORESOURCE_MEM,
 414         }, {
 415                 .start  = gic_iid(0x71),
 416                 .flags  = IORESOURCE_IRQ,
 417         },
 418 };
 419
 420 static struct platform_device i2c3_device = {
 421         .name           = "i2c-rcar",
 422         .id             = 3,
 423         .resource       = rcar_i2c3_res,
 424         .num_resources  = ARRAY_SIZE(rcar_i2c3_res),
 425 };
 426
 427 static struct resource sata_resources[] = {
 428         [0] = {
 429                 .name   = "rcar-sata",
 430                 .start  = 0xfc600000,
 431                 .end    = 0xfc601fff,
 432                 .flags  = IORESOURCE_MEM,
 433         },
 434         [1] = {
 435                 .start  = gic_iid(0x84),
 436                 .flags  = IORESOURCE_IRQ,
 437         },
 438 };
 439
 440 static struct platform_device sata_device = {
 441         .name           = "sata_rcar",
 442         .id             = -1,
 443         .resource       = sata_resources,
 444         .num_resources  = ARRAY_SIZE(sata_resources),
 445         .dev            = {
 446                 .dma_mask               = &sata_device.dev.coherent_dma_mask,
 447                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 448         },
 449 };
 450
 451 /* USB */
 452 static struct usb_phy *phy;
 453
 454 static int usb_power_on(struct platform_device *pdev)
 455 {
 456         if (IS_ERR(phy))
 457                 return PTR_ERR(phy);
 458
 459         pm_runtime_enable(&pdev->dev);
 460         pm_runtime_get_sync(&pdev->dev);
 461
 462         usb_phy_init(phy);
 463
 464         return 0;
 465 }
 466
 467 static void usb_power_off(struct platform_device *pdev)
 468 {
 469         if (IS_ERR(phy))
 470                 return;
 471
 472         usb_phy_shutdown(phy);
 473
 474         pm_runtime_put_sync(&pdev->dev);
 475         pm_runtime_disable(&pdev->dev);
 476 }
 477
 478 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 479 {
 480         /*
 481          * Below are recommended values from the datasheet;
 482          * see [USB :: Setting of EHCI Internal Buffer].
 483          */
 484         /* EHCI IP internal buffer setting */
 485         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 486         /* EHCI IP internal buffer enable */
 487         iowrite32(0x00000001, hcd->regs + 0x009C);
 488
 489         return 0;
 490 }
 491
 492 static struct usb_ehci_pdata ehcix_pdata = {
 493         .power_on       = usb_power_on,
 494         .power_off      = usb_power_off,
 495         .power_suspend  = usb_power_off,
 496         .pre_setup      = ehci_init_internal_buffer,
 497 };
 498
 499 static struct resource ehci0_resources[] = {
 500         [0] = {
 501                 .start  = 0xffe70000,
 502                 .end    = 0xffe70400 - 1,
 503                 .flags  = IORESOURCE_MEM,
 504         },
 505         [1] = {
 506                 .start  = gic_iid(0x4c),
 507                 .flags  = IORESOURCE_IRQ,
 508         },
 509 };
 510
 511 static struct platform_device ehci0_device = {
 512         .name   = "ehci-platform",
 513         .id     = 0,
 514         .dev    = {
 515                 .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
 516                 .coherent_dma_mask      = 0xffffffff,
 517                 .platform_data          = &ehcix_pdata,
 518         },
 519         .num_resources  = ARRAY_SIZE(ehci0_resources),
 520         .resource       = ehci0_resources,
 521 };
 522
 523 static struct resource ehci1_resources[] = {
 524         [0] = {
 525                 .start  = 0xfff70000,
 526                 .end    = 0xfff70400 - 1,
 527                 .flags  = IORESOURCE_MEM,
 528         },
 529         [1] = {
 530                 .start  = gic_iid(0x4d),
 531                 .flags  = IORESOURCE_IRQ,
 532         },
 533 };
 534
 535 static struct platform_device ehci1_device = {
 536         .name   = "ehci-platform",
 537         .id     = 1,
 538         .dev    = {
 539                 .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
 540                 .coherent_dma_mask      = 0xffffffff,
 541                 .platform_data          = &ehcix_pdata,
 542         },
 543         .num_resources  = ARRAY_SIZE(ehci1_resources),
 544         .resource       = ehci1_resources,
 545 };
 546
 547 static struct usb_ohci_pdata ohcix_pdata = {
 548         .power_on       = usb_power_on,
 549         .power_off      = usb_power_off,
 550         .power_suspend  = usb_power_off,
 551 };
 552
 553 static struct resource ohci0_resources[] = {
 554         [0] = {
 555                 .start  = 0xffe70400,
 556                 .end    = 0xffe70800 - 1,
 557                 .flags  = IORESOURCE_MEM,
 558         },
 559         [1] = {
 560                 .start  = gic_iid(0x4c),
 561                 .flags  = IORESOURCE_IRQ,
 562         },
 563 };
 564
 565 static struct platform_device ohci0_device = {
 566         .name   = "ohci-platform",
 567         .id     = 0,
 568         .dev    = {
 569                 .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
 570                 .coherent_dma_mask      = 0xffffffff,
 571                 .platform_data          = &ohcix_pdata,
 572         },
 573         .num_resources  = ARRAY_SIZE(ohci0_resources),
 574         .resource       = ohci0_resources,
 575 };
 576
 577 static struct resource ohci1_resources[] = {
 578         [0] = {
 579                 .start  = 0xfff70400,
 580                 .end    = 0xfff70800 - 1,
 581                 .flags  = IORESOURCE_MEM,
 582         },
 583         [1] = {
 584                 .start  = gic_iid(0x4d),
 585                 .flags  = IORESOURCE_IRQ,
 586         },
 587 };
 588
 589 static struct platform_device ohci1_device = {
 590         .name   = "ohci-platform",
 591         .id     = 1,
 592         .dev    = {
 593                 .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
 594                 .coherent_dma_mask      = 0xffffffff,
 595                 .platform_data          = &ohcix_pdata,
 596         },
 597         .num_resources  = ARRAY_SIZE(ohci1_resources),
 598         .resource       = ohci1_resources,
 599 };
 600
 601 /* Ether */
 602 static struct resource ether_resources[] __initdata = {
 603         {
 604                 .start  = 0xfde00000,
 605                 .end    = 0xfde003ff,
 606                 .flags  = IORESOURCE_MEM,
 607         }, {
 608                 .start  = gic_iid(0xb4),
 609                 .flags  = IORESOURCE_IRQ,
 610         },
 611 };
 612
 613 #define R8A7779_VIN(idx) \
 614 static struct resource vin##idx##_resources[] __initdata = {            \
 615         DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000),            \
 616         DEFINE_RES_IRQ(gic_iid(0x5f + (idx))),                          \
 617 };                                                                      \
 618                                                                         \
 619 static struct platform_device_info vin##idx##_info __initdata = {       \
 620         .parent         = &platform_bus,                                \
 621         .name           = "r8a7779-vin",                                \
 622         .id             = idx,                                          \
 623         .res            = vin##idx##_resources,                         \
 624         .num_res        = ARRAY_SIZE(vin##idx##_resources),             \
 625         .dma_mask       = DMA_BIT_MASK(32),                             \
 626 }
 627
 628 R8A7779_VIN(0);
 629 R8A7779_VIN(1);
 630 R8A7779_VIN(2);
 631 R8A7779_VIN(3);
 632
 633 static struct platform_device_info *vin_info_table[] __initdata = {
 634         &vin0_info,
 635         &vin1_info,
 636         &vin2_info,
 637         &vin3_info,
 638 };
 639
 640 /* HPB-DMA */
 641
 642 /* Asynchronous mode register bits */
 643 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK           BIT(23) /* MMC1 */
 644 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE         BIT(23) /* MMC1 */
 645 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI          0       /* MMC1 */
 646 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK         BIT(22) /* MMC1 */
 647 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST        BIT(22) /* MMC1 */
 648 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST       0       /* MMC1 */
 649 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK           BIT(21) /* MMC0 */
 650 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE         BIT(21) /* MMC0 */
 651 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI          0       /* MMC0 */
 652 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK         BIT(20) /* MMC0 */
 653 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST        BIT(20) /* MMC0 */
 654 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST       0       /* MMC0 */
 655 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK           BIT(19) /* SDHI3 */
 656 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE         BIT(19) /* SDHI3 */
 657 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI          0       /* SDHI3 */
 658 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK         BIT(18) /* SDHI3 */
 659 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST        BIT(18) /* SDHI3 */
 660 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST       0       /* SDHI3 */
 661 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK           BIT(17) /* SDHI3 */
 662 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE         BIT(17) /* SDHI3 */
 663 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI          0       /* SDHI3 */
 664 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK         BIT(16) /* SDHI3 */
 665 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST        BIT(16) /* SDHI3 */
 666 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST       0       /* SDHI3 */
 667 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK           BIT(15) /* SDHI3 */
 668 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE         BIT(15) /* SDHI3 */
 669 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI          0       /* SDHI3 */
 670 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK         BIT(14) /* SDHI3 */
 671 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST        BIT(14) /* SDHI3 */
 672 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST       0       /* SDHI3 */
 673 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK           BIT(13) /* SDHI2 */
 674 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE         BIT(13) /* SDHI2 */
 675 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI          0       /* SDHI2 */
 676 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK         BIT(12) /* SDHI2 */
 677 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST        BIT(12) /* SDHI2 */
 678 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST       0       /* SDHI2 */
 679 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK           BIT(11) /* SDHI2 */
 680 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE         BIT(11) /* SDHI2 */
 681 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI          0       /* SDHI2 */
 682 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK         BIT(10) /* SDHI2 */
 683 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST        BIT(10) /* SDHI2 */
 684 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST       0       /* SDHI2 */
 685 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK           BIT(9)  /* SDHI2 */
 686 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE         BIT(9)  /* SDHI2 */
 687 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI          0       /* SDHI2 */
 688 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK         BIT(8)  /* SDHI2 */
 689 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST        BIT(8)  /* SDHI2 */
 690 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST       0       /* SDHI2 */
 691 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK           BIT(7)  /* SDHI0 */
 692 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE         BIT(7)  /* SDHI0 */
 693 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI          0       /* SDHI0 */
 694 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK         BIT(6)  /* SDHI0 */
 695 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST        BIT(6)  /* SDHI0 */
 696 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST       0       /* SDHI0 */
 697 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK           BIT(5)  /* SDHI0 */
 698 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE         BIT(5)  /* SDHI0 */
 699 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI          0       /* SDHI0 */
 700 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK         BIT(4)  /* SDHI0 */
 701 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST        BIT(4)  /* SDHI0 */
 702 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST       0       /* SDHI0 */
 703 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK           BIT(3)  /* SDHI0 */
 704 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE         BIT(3)  /* SDHI0 */
 705 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI          0       /* SDHI0 */
 706 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK         BIT(2)  /* SDHI0 */
 707 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST        BIT(2)  /* SDHI0 */
 708 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST       0       /* SDHI0 */
 709 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK           BIT(1)  /* SDHI1 */
 710 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE         BIT(1)  /* SDHI1 */
 711 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI          0       /* SDHI1 */
 712 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK         BIT(0)  /* SDHI1 */
 713 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST        BIT(0)  /* SDHI1 */
 714 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST       0       /* SDHI1 */
 715
 716 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 717         {
 718                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 719                 .addr   = 0xffe4c000 + 0x30,
 720                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 721                           HPB_DMAE_DCR_DMDL |
 722                           HPB_DMAE_DCR_DPDS_16BIT,
 723                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 724                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 725                           HPB_DMAE_ASYNCRSTR_ASRST23,
 726                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
 727                           HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
 728                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
 729                           HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
 730                 .port   = 0x0D0C,
 731                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 732                 .dma_ch = 21,
 733         }, {
 734                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 735                 .addr   = 0xffe4c000 + 0x30,
 736                 .dcr    = HPB_DMAE_DCR_SMDL |
 737                           HPB_DMAE_DCR_SPDS_16BIT |
 738                           HPB_DMAE_DCR_DPDS_16BIT,
 739                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 740                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 741                           HPB_DMAE_ASYNCRSTR_ASRST23,
 742                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
 743                           HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
 744                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
 745                           HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
 746                 .port   = 0x0D0C,
 747                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 748                 .dma_ch = 22,
 749         },
 750 };
 751
 752 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 753         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 754         HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 755 };
 756
 757 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 758         .slaves                 = hpb_dmae_slaves,
 759         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 760         .channels               = hpb_dmae_channels,
 761         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 762         .ts_shift               = {
 763                 [XMIT_SZ_8BIT]  = 0,
 764                 [XMIT_SZ_16BIT] = 1,
 765                 [XMIT_SZ_32BIT] = 2,
 766         },
 767         .num_hw_channels        = 44,
 768 };
 769
 770 static struct resource hpb_dmae_resources[] __initdata = {
 771         /* Channel registers */
 772         DEFINE_RES_MEM(0xffc08000, 0x1000),
 773         /* Common registers */
 774         DEFINE_RES_MEM(0xffc09000, 0x170),
 775         /* Asynchronous reset registers */
 776         DEFINE_RES_MEM(0xffc00300, 4),
 777         /* Asynchronous mode registers */
 778         DEFINE_RES_MEM(0xffc00400, 4),
 779         /* IRQ for DMA channels */
 780         DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
 781 };
 782
 783 static void __init r8a7779_register_hpb_dmae(void)
 784 {
 785         platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
 786                                           hpb_dmae_resources,
 787                                           ARRAY_SIZE(hpb_dmae_resources),
 788                                           &dma_platform_data,
 789                                           sizeof(dma_platform_data));
 790 }
 791
 792 static struct platform_device *r8a7779_devices_dt[] __initdata = {
 793         &scif0_device,
 794         &scif1_device,
 795         &scif2_device,
 796         &scif3_device,
 797         &scif4_device,
 798         &scif5_device,
 799         &tmu00_device,
 800         &tmu01_device,
 801 };
 802
 803 static struct platform_device *r8a7779_standard_devices[] __initdata = {
 804         &i2c0_device,
 805         &i2c1_device,
 806         &i2c2_device,
 807         &i2c3_device,
 808         &sata_device,
 809 };
 810
 811 void __init r8a7779_add_standard_devices(void)
 812 {
 813 #ifdef CONFIG_CACHE_L2X0
 814         /* Early BRESP enable, Shared attribute override enable, 64K*16way */
 815         l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
 816 #endif
 817         r8a7779_pm_init();
 818
 819         r8a7779_init_pm_domains();
 820
 821         platform_add_devices(r8a7779_devices_dt,
 822                             ARRAY_SIZE(r8a7779_devices_dt));
 823         platform_add_devices(r8a7779_standard_devices,
 824                             ARRAY_SIZE(r8a7779_standard_devices));
 825         r8a7779_register_hpb_dmae();
 826 }
 827
 828 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
 829 {
 830         platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
 831                                           ether_resources,
 832                                           ARRAY_SIZE(ether_resources),
 833                                           pdata, sizeof(*pdata));
 834 }
 835
 836 void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
 837 {
 838         BUG_ON(id < 0 || id > 3);
 839
 840         vin_info_table[id]->data = pdata;
 841         vin_info_table[id]->size_data = sizeof(*pdata);
 842
 843         platform_device_register_full(vin_info_table[id]);
 844 }
 845
 846 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 847 void __init __weak r8a7779_register_twd(void) { }
 848
 849 void __init r8a7779_earlytimer_init(void)
 850 {
 851         r8a7779_clock_init();
 852         r8a7779_register_twd();
 853         shmobile_earlytimer_init();
 854 }
 855
 856 void __init r8a7779_add_early_devices(void)
 857 {
 858         early_platform_add_devices(r8a7779_devices_dt,
 859                                    ARRAY_SIZE(r8a7779_devices_dt));
 860
 861         /* Early serial console setup is not included here due to
 862          * memory map collisions. The SCIF serial ports in r8a7779
 863          * are difficult to entity map 1:1 due to collision with the
 864          * virtual memory range used by the coherent DMA code on ARM.
 865          *
 866          * Anyone wanting to debug early can remove UPF_IOREMAP from
 867          * the sh-sci serial console platform data, adjust mapbase
 868          * to a static M:N virt:phys mapping that needs to be added to
 869          * the mappings passed with iotable_init() above.
 870          *
 871          * Then add a call to shmobile_setup_console() from this function.
 872          *
 873          * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
 874          * command line in case of the marzen board.
 875          */
 876 }
 877
 878 static struct platform_device *r8a7779_late_devices[] __initdata = {
 879         &ehci0_device,
 880         &ehci1_device,
 881         &ohci0_device,
 882         &ohci1_device,
 883 };
 884
 885 void __init r8a7779_init_late(void)
 886 {
 887         /* get USB PHY */
 888         phy = usb_get_phy(USB_PHY_TYPE_USB2);
 889
 890         shmobile_init_late();
 891         platform_add_devices(r8a7779_late_devices,
 892                              ARRAY_SIZE(r8a7779_late_devices));
 893 }
 894
 895 #ifdef CONFIG_USE_OF
 896 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 897 {
 898         return 0; /* always allow wakeup */
 899 }
 900
 901 void __init r8a7779_init_irq_dt(void)
 902 {
 903         gic_arch_extn.irq_set_wake = r8a7779_set_wake;
 904
 905         irqchip_init();
 906
 907         /* route all interrupts to ARM */
 908         __raw_writel(0xffffffff, INT2NTSR0);
 909         __raw_writel(0x3fffffff, INT2NTSR1);
 910
 911         /* unmask all known interrupts in INTCS2 */
 912         __raw_writel(0xfffffff0, INT2SMSKCR0);
 913         __raw_writel(0xfff7ffff, INT2SMSKCR1);
 914         __raw_writel(0xfffbffdf, INT2SMSKCR2);
 915         __raw_writel(0xbffffffc, INT2SMSKCR3);
 916         __raw_writel(0x003fee3f, INT2SMSKCR4);
 917 }
 918
 919 void __init r8a7779_init_delay(void)
 920 {
 921         shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
 922 }
 923
 924 void __init r8a7779_add_standard_devices_dt(void)
 925 {
 926         /* clocks are setup late during boot in the case of DT */
 927         r8a7779_clock_init();
 928
 929         platform_add_devices(r8a7779_devices_dt,
 930                              ARRAY_SIZE(r8a7779_devices_dt));
 931         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 932 }
 933
 934 static const char *r8a7779_compat_dt[] __initdata = {
 935         "renesas,r8a7779",
 936         NULL,
 937 };
 938
 939 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
 940         .map_io         = r8a7779_map_io,
 941         .init_early     = r8a7779_init_delay,
 942         .nr_irqs        = NR_IRQS_LEGACY,
 943         .init_irq       = r8a7779_init_irq_dt,
 944         .init_machine   = r8a7779_add_standard_devices_dt,
 945         .init_late      = r8a7779_init_late,
 946         .dt_compat      = r8a7779_compat_dt,
 947 MACHINE_END
 948 #endif /* CONFIG_USE_OF */