arch/arm/mach-shmobile/setup-r8a73a4.c

   1 /*
   2  * r8a73a4 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/platform_data/irq-renesas-irqc.h>
  24 #include <linux/serial_sci.h>
  25 #include <linux/sh_dma.h>
  26 #include <linux/sh_timer.h>
  27 #include <mach/common.h>
  28 #include <mach/dma-register.h>
  29 #include <mach/irqs.h>
  30 #include <mach/r8a73a4.h>
  31 #include <asm/mach/arch.h>
  32
  33 static const struct resource pfc_resources[] = {
  34         DEFINE_RES_MEM(0xe6050000, 0x9000),
  35 };
  36
  37 void __init r8a73a4_pinmux_init(void)
  38 {
  39         platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
  40                                         ARRAY_SIZE(pfc_resources));
  41 }
  42
  43 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
  44         .type           = scif_type,                            \
  45         .mapbase        = baseaddr,                             \
  46         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
  47         .scbrr_algo_id  = SCBRR_ALGO_4,                         \
  48         .irqs           = SCIx_IRQ_MUXED(irq)
  49
  50 #define SCIFA_DATA(index, baseaddr, irq)                \
  51 [index] = {                                             \
  52         SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
  53         .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,      \
  54 }
  55
  56 #define SCIFB_DATA(index, baseaddr, irq)        \
  57 [index] = {                                     \
  58         SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
  59         .scscr = SCSCR_RE | SCSCR_TE,           \
  60 }
  61
  62 enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
  63
  64 static const struct plat_sci_port scif[] = {
  65         SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
  66         SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
  67         SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
  68         SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
  69         SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
  70         SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
  71 };
  72
  73 static inline void r8a73a4_register_scif(int idx)
  74 {
  75         platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
  76                                       sizeof(struct plat_sci_port));
  77 }
  78
  79 static const struct renesas_irqc_config irqc0_data = {
  80         .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
  81 };
  82
  83 static const struct resource irqc0_resources[] = {
  84         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
  85         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
  86         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
  87         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
  88         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
  89         DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
  90         DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
  91         DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
  92         DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
  93         DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
  94         DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
  95         DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
  96         DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
  97         DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
  98         DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
  99         DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
 100         DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
 101         DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
 102         DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
 103         DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
 104         DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
 105         DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
 106         DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
 107         DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
 108         DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
 109         DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
 110         DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
 111         DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
 112         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
 113         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
 114         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
 115         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
 116         DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
 117 };
 118
 119 static const struct renesas_irqc_config irqc1_data = {
 120         .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
 121 };
 122
 123 static const struct resource irqc1_resources[] = {
 124         DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
 125         DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
 126         DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
 127         DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
 128         DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
 129         DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
 130         DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
 131         DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
 132         DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
 133         DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
 134         DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
 135         DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
 136         DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
 137         DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
 138         DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
 139         DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
 140         DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
 141         DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
 142         DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
 143         DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
 144         DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
 145         DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
 146         DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
 147         DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
 148         DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
 149         DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
 150         DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
 151 };
 152
 153 #define r8a73a4_register_irqc(idx)                                      \
 154         platform_device_register_resndata(&platform_bus, "renesas_irqc", \
 155                                           idx, irqc##idx##_resources,   \
 156                                           ARRAY_SIZE(irqc##idx##_resources), \
 157                                           &irqc##idx##_data,            \
 158                                           sizeof(struct renesas_irqc_config))
 159
 160 /* Thermal0 -> Thermal2 */
 161 static const struct resource thermal0_resources[] = {
 162         DEFINE_RES_MEM(0xe61f0000, 0x14),
 163         DEFINE_RES_MEM(0xe61f0100, 0x38),
 164         DEFINE_RES_MEM(0xe61f0200, 0x38),
 165         DEFINE_RES_MEM(0xe61f0300, 0x38),
 166         DEFINE_RES_IRQ(gic_spi(69)),
 167 };
 168
 169 #define r8a73a4_register_thermal()                                      \
 170         platform_device_register_simple("rcar_thermal", -1,             \
 171                                         thermal0_resources,             \
 172                                         ARRAY_SIZE(thermal0_resources))
 173
 174 static struct sh_timer_config cmt10_platform_data = {
 175         .name = "CMT10",
 176         .timer_bit = 0,
 177         .clockevent_rating = 80,
 178 };
 179
 180 static struct resource cmt10_resources[] = {
 181         DEFINE_RES_MEM(0xe6130010, 0x0c),
 182         DEFINE_RES_MEM(0xe6130000, 0x04),
 183         DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
 184 };
 185
 186 #define r8a7790_register_cmt(idx)                                       \
 187         platform_device_register_resndata(&platform_bus, "sh_cmt",      \
 188                                           idx, cmt##idx##_resources,    \
 189                                           ARRAY_SIZE(cmt##idx##_resources), \
 190                                           &cmt##idx##_platform_data,    \
 191                                           sizeof(struct sh_timer_config))
 192
 193 void __init r8a73a4_add_dt_devices(void)
 194 {
 195         r8a73a4_register_scif(SCIFA0);
 196         r8a73a4_register_scif(SCIFA1);
 197         r8a73a4_register_scif(SCIFB0);
 198         r8a73a4_register_scif(SCIFB1);
 199         r8a73a4_register_scif(SCIFB2);
 200         r8a73a4_register_scif(SCIFB3);
 201         r8a7790_register_cmt(10);
 202 }
 203
 204 /* DMA */
 205 static const struct sh_dmae_slave_config dma_slaves[] = {
 206         {
 207                 .slave_id       = SHDMA_SLAVE_MMCIF0_TX,
 208                 .addr           = 0xee200034,
 209                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 210                 .mid_rid        = 0xd1,
 211         }, {
 212                 .slave_id       = SHDMA_SLAVE_MMCIF0_RX,
 213                 .addr           = 0xee200034,
 214                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 215                 .mid_rid        = 0xd2,
 216         }, {
 217                 .slave_id       = SHDMA_SLAVE_MMCIF1_TX,
 218                 .addr           = 0xee220034,
 219                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 220                 .mid_rid        = 0xe1,
 221         }, {
 222                 .slave_id       = SHDMA_SLAVE_MMCIF1_RX,
 223                 .addr           = 0xee220034,
 224                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 225                 .mid_rid        = 0xe2,
 226         },
 227 };
 228
 229 #define DMAE_CHANNEL(a, b)                              \
 230         {                                               \
 231                 .offset         = (a) - 0x20,           \
 232                 .dmars          = (a) - 0x20 + 0x40,    \
 233                 .chclr_bit      = (b),                  \
 234                 .chclr_offset   = 0x80 - 0x20,          \
 235         }
 236
 237 static const struct sh_dmae_channel dma_channels[] = {
 238         DMAE_CHANNEL(0x8000, 0),
 239         DMAE_CHANNEL(0x8080, 1),
 240         DMAE_CHANNEL(0x8100, 2),
 241         DMAE_CHANNEL(0x8180, 3),
 242         DMAE_CHANNEL(0x8200, 4),
 243         DMAE_CHANNEL(0x8280, 5),
 244         DMAE_CHANNEL(0x8300, 6),
 245         DMAE_CHANNEL(0x8380, 7),
 246         DMAE_CHANNEL(0x8400, 8),
 247         DMAE_CHANNEL(0x8480, 9),
 248         DMAE_CHANNEL(0x8500, 10),
 249         DMAE_CHANNEL(0x8580, 11),
 250         DMAE_CHANNEL(0x8600, 12),
 251         DMAE_CHANNEL(0x8680, 13),
 252         DMAE_CHANNEL(0x8700, 14),
 253         DMAE_CHANNEL(0x8780, 15),
 254         DMAE_CHANNEL(0x8800, 16),
 255         DMAE_CHANNEL(0x8880, 17),
 256         DMAE_CHANNEL(0x8900, 18),
 257         DMAE_CHANNEL(0x8980, 19),
 258 };
 259
 260 static const struct sh_dmae_pdata dma_pdata = {
 261         .slave          = dma_slaves,
 262         .slave_num      = ARRAY_SIZE(dma_slaves),
 263         .channel        = dma_channels,
 264         .channel_num    = ARRAY_SIZE(dma_channels),
 265         .ts_low_shift   = TS_LOW_SHIFT,
 266         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 267         .ts_high_shift  = TS_HI_SHIFT,
 268         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 269         .ts_shift       = dma_ts_shift,
 270         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 271         .dmaor_init     = DMAOR_DME,
 272         .chclr_present  = 1,
 273         .chclr_bitwise  = 1,
 274 };
 275
 276 static struct resource dma_resources[] = {
 277         DEFINE_RES_MEM(0xe6700020, 0x89e0),
 278         DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
 279         {
 280                 /* IRQ for channels 0-19 */
 281                 .start  = gic_spi(200),
 282                 .end    = gic_spi(219),
 283                 .flags  = IORESOURCE_IRQ,
 284         },
 285 };
 286
 287 #define r8a73a4_register_dmac()                                                 \
 288         platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0,    \
 289                                 dma_resources, ARRAY_SIZE(dma_resources),       \
 290                                 &dma_pdata, sizeof(dma_pdata))
 291
 292 void __init r8a73a4_add_standard_devices(void)
 293 {
 294         r8a73a4_add_dt_devices();
 295         r8a73a4_register_irqc(0);
 296         r8a73a4_register_irqc(1);
 297         r8a73a4_register_thermal();
 298         r8a73a4_register_dmac();
 299 }
 300
 301 void __init r8a73a4_init_early(void)
 302 {
 303 #ifndef CONFIG_ARM_ARCH_TIMER
 304         shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
 305 #endif
 306 }
 307
 308 #ifdef CONFIG_USE_OF
 309
 310 static const char *r8a73a4_boards_compat_dt[] __initdata = {
 311         "renesas,r8a73a4",
 312         NULL,
 313 };
 314
 315 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
 316         .init_early     = r8a73a4_init_early,
 317         .dt_compat      = r8a73a4_boards_compat_dt,
 318 MACHINE_END
 319 #endif /* CONFIG_USE_OF */