1 /* linux/arch/arm/mach-s3c2410/mach-osiris.c
3 * Copyright (c) 2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
20 #include <asm/mach/arch.h>
21 #include <asm/mach/map.h>
22 #include <asm/mach/irq.h>
24 #include <asm/arch/osiris-map.h>
25 #include <asm/arch/osiris-cpld.h>
27 #include <asm/hardware.h>
30 #include <asm/mach-types.h>
32 #include <asm/arch/regs-serial.h>
33 #include <asm/arch/regs-gpio.h>
34 #include <asm/arch/regs-mem.h>
35 #include <asm/arch/regs-lcd.h>
36 #include <asm/arch/nand.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/nand.h>
40 #include <linux/mtd/nand_ecc.h>
41 #include <linux/mtd/partitions.h>
47 /* onboard perihpheral map */
49 static struct map_desc osiris_iodesc[] __initdata = {
50 /* ISA IO areas (may be over-written later) */
53 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
54 .pfn = __phys_to_pfn(S3C2410_CS5),
58 .virtual = (u32)S3C24XX_VA_ISA_WORD,
59 .pfn = __phys_to_pfn(S3C2410_CS5),
64 /* CPLD control registers */
67 .virtual = (u32)OSIRIS_VA_CTRL1,
68 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
72 .virtual = (u32)OSIRIS_VA_CTRL2,
73 .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
79 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
80 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
81 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
83 static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
98 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
105 .clocks = osiris_serial_clocks,
106 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
114 .clocks = osiris_serial_clocks,
115 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
123 .clocks = osiris_serial_clocks,
124 .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
128 /* NAND Flash on Osiris board */
130 static int external_map[] = { 2 };
131 static int chip0_map[] = { 0 };
132 static int chip1_map[] = { 1 };
134 static struct mtd_partition osiris_default_nand_part[] = {
136 .name = "Boot Agent",
142 .size = SZ_4M - SZ_16K,
148 .size = SZ_32M - SZ_4M,
153 .size = MTDPART_SIZ_FULL,
157 /* the Osiris has 3 selectable slots for nand-flash, the two
158 * on-board chip areas, as well as the external slot.
160 * Note, there is no current hot-plug support for the External
164 static struct s3c2410_nand_set osiris_nand_sets[] = {
168 .nr_map = external_map,
169 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
170 .partitions = osiris_default_nand_part,
176 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
177 .partitions = osiris_default_nand_part,
183 .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
184 .partitions = osiris_default_nand_part,
188 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
192 slot = set->nr_map[slot] & 3;
194 pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
195 slot, set, set->nr_map);
197 tmp = __raw_readb(OSIRIS_VA_CTRL1);
198 tmp &= ~OSIRIS_CTRL1_NANDSEL;
201 pr_debug("osiris_nand: ctrl1 now %02x\n", tmp);
203 __raw_writeb(tmp, OSIRIS_VA_CTRL1);
206 static struct s3c2410_platform_nand osiris_nand_info = {
210 .nr_sets = ARRAY_SIZE(osiris_nand_sets),
211 .sets = osiris_nand_sets,
212 .select_chip = osiris_nand_select,
215 /* PCMCIA control and configuration */
217 static struct resource osiris_pcmcia_resource[] = {
221 .flags = IORESOURCE_MEM,
226 .flags = IORESOURCE_MEM,
230 static struct platform_device osiris_pcmcia = {
231 .name = "osiris-pcmcia",
233 .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
234 .resource = osiris_pcmcia_resource,
237 /* Standard Osiris devices */
239 static struct platform_device *osiris_devices[] __initdata = {
245 static struct clk *osiris_clocks[] = {
253 static struct s3c24xx_board osiris_board __initdata = {
254 .devices = osiris_devices,
255 .devices_count = ARRAY_SIZE(osiris_devices),
256 .clocks = osiris_clocks,
257 .clocks_count = ARRAY_SIZE(osiris_clocks),
260 static void __init osiris_map_io(void)
264 /* initialise the clocks */
266 s3c24xx_dclk0.parent = NULL;
267 s3c24xx_dclk0.rate = 12*1000*1000;
269 s3c24xx_dclk1.parent = NULL;
270 s3c24xx_dclk1.rate = 24*1000*1000;
272 s3c24xx_clkout0.parent = &s3c24xx_dclk0;
273 s3c24xx_clkout1.parent = &s3c24xx_dclk1;
275 s3c24xx_uclk.parent = &s3c24xx_clkout1;
277 s3c_device_nand.dev.platform_data = &osiris_nand_info;
279 s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
280 s3c24xx_init_clocks(0);
281 s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
282 s3c24xx_set_board(&osiris_board);
284 /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
286 local_irq_save(flags);
287 __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
288 local_irq_restore(flags);
290 /* write-protect line to the NAND */
291 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
294 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
295 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
296 .phys_io = S3C2410_PA_UART,
297 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
298 .boot_params = S3C2410_SDRAM_PA + 0x100,
299 .map_io = osiris_map_io,
300 .init_irq = s3c24xx_init_irq,
301 .timer = &s3c24xx_timer,