arch/arm/mach-pxa/cm-x2xx-pci.c

   1 /*
   2  * linux/arch/arm/mach-pxa/cm-x2xx-pci.c
   3  *
   4  * PCI bios-type initialisation for PCI machines
   5  *
   6  * Bits taken from various places.
   7  *
   8  * Copyright (C) 2007, 2008 Compulab, Ltd.
   9  * Mike Rapoport <mike@compulab.co.il>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22 #include <linux/gpio.h>
  23
  24 #include <asm/mach/pci.h>
  25 #include <asm/mach-types.h>
  26
  27 #include <asm/hardware/it8152.h>
  28
  29 void __iomem *it8152_base_address;
  30 static int cmx2xx_it8152_irq_gpio;
  31
  32 static void cmx2xx_it8152_irq_demux(unsigned int __irq, struct irq_desc *desc)
  33 {
  34         unsigned int irq = irq_desc_get_irq(desc);
  35         /* clear our parent irq */
  36         desc->irq_data.chip->irq_ack(&desc->irq_data);
  37
  38         it8152_irq_demux(irq, desc);
  39 }
  40
  41 void __cmx2xx_pci_init_irq(int irq_gpio)
  42 {
  43         it8152_init_irq();
  44
  45         cmx2xx_it8152_irq_gpio = irq_gpio;
  46
  47         irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
  48
  49         irq_set_chained_handler(gpio_to_irq(irq_gpio),
  50                                 cmx2xx_it8152_irq_demux);
  51 }
  52
  53 #ifdef CONFIG_PM
  54 static unsigned long sleep_save_ite[10];
  55
  56 void __cmx2xx_pci_suspend(void)
  57 {
  58         /* save ITE state */
  59         sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
  60         sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
  61         sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
  62
  63         /* Clear ITE IRQ's */
  64         __raw_writel((0), IT8152_INTC_PDCNIRR);
  65         __raw_writel((0), IT8152_INTC_LPCNIRR);
  66 }
  67
  68 void __cmx2xx_pci_resume(void)
  69 {
  70         /* restore IT8152 state */
  71         __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
  72         __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
  73         __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
  74 }
  75 #else
  76 void cmx2xx_pci_suspend(void) {}
  77 void cmx2xx_pci_resume(void) {}
  78 #endif
  79
  80 /* PCI IRQ mapping*/
  81 static int __init cmx2xx_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  82 {
  83         int irq;
  84
  85         dev_dbg(&dev->dev, "%s: slot=%x, pin=%x\n", __func__, slot, pin);
  86
  87         irq = it8152_pci_map_irq(dev, slot, pin);
  88         if (irq)
  89                 return irq;
  90
  91         /*
  92           Here comes the ugly part. The routing is baseboard specific,
  93           but defining a platform for each possible base of CM-X2XX is
  94           unrealistic. Here we keep mapping for ATXBase and SB-X2XX.
  95         */
  96         /* ATXBASE PCI slot */
  97         if (slot == 7)
  98                 return IT8152_PCI_INTA;
  99
 100         /* ATXBase/SB-X2XX CardBus */
 101         if (slot == 8 || slot == 0)
 102                 return IT8152_PCI_INTB;
 103
 104         /* ATXBase Ethernet */
 105         if (slot == 9)
 106                 return IT8152_PCI_INTA;
 107
 108         /* CM-x255 Onboard Ethernet */
 109         if (slot == 15)
 110                 return IT8152_PCI_INTC;
 111
 112         /* SB-x2xx Ethernet */
 113         if (slot == 16)
 114                 return IT8152_PCI_INTA;
 115
 116         /* PC104+ interrupt routing */
 117         if ((slot == 17) || (slot == 19))
 118                 return IT8152_PCI_INTA;
 119         if ((slot == 18) || (slot == 20))
 120                 return IT8152_PCI_INTB;
 121
 122         return(0);
 123 }
 124
 125 static void cmx2xx_pci_preinit(void)
 126 {
 127         pr_info("Initializing CM-X2XX PCI subsystem\n");
 128
 129         pcibios_min_io = 0;
 130         pcibios_min_mem = 0;
 131
 132         __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
 133         if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
 134                 pr_info("PCI Bridge found.\n");
 135
 136                 /* set PCI I/O base at 0 */
 137                 writel(0x848, IT8152_PCI_CFG_ADDR);
 138                 writel(0, IT8152_PCI_CFG_DATA);
 139
 140                 /* set PCI memory base at 0 */
 141                 writel(0x840, IT8152_PCI_CFG_ADDR);
 142                 writel(0, IT8152_PCI_CFG_DATA);
 143
 144                 writel(0x20, IT8152_GPIO_GPDR);
 145
 146                 /* CardBus Controller on ATXbase baseboard */
 147                 writel(0x4000, IT8152_PCI_CFG_ADDR);
 148                 if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
 149                         pr_info("CardBus Bridge found.\n");
 150
 151                         /* Configure socket 0 */
 152                         writel(0x408C, IT8152_PCI_CFG_ADDR);
 153                         writel(0x1022, IT8152_PCI_CFG_DATA);
 154
 155                         writel(0x4080, IT8152_PCI_CFG_ADDR);
 156                         writel(0x3844d060, IT8152_PCI_CFG_DATA);
 157
 158                         writel(0x4090, IT8152_PCI_CFG_ADDR);
 159                         writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
 160                                 0x60440000),
 161                                IT8152_PCI_CFG_DATA);
 162
 163                         writel(0x4018, IT8152_PCI_CFG_ADDR);
 164                         writel(0xb0000000, IT8152_PCI_CFG_DATA);
 165
 166                         /* Configure socket 1 */
 167                         writel(0x418C, IT8152_PCI_CFG_ADDR);
 168                         writel(0x1022, IT8152_PCI_CFG_DATA);
 169
 170                         writel(0x4180, IT8152_PCI_CFG_ADDR);
 171                         writel(0x3844d060, IT8152_PCI_CFG_DATA);
 172
 173                         writel(0x4190, IT8152_PCI_CFG_ADDR);
 174                         writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
 175                                 0x60440000),
 176                                IT8152_PCI_CFG_DATA);
 177
 178                         writel(0x4118, IT8152_PCI_CFG_ADDR);
 179                         writel(0xb0000000, IT8152_PCI_CFG_DATA);
 180                 }
 181         }
 182 }
 183
 184 static struct hw_pci cmx2xx_pci __initdata = {
 185         .map_irq        = cmx2xx_pci_map_irq,
 186         .nr_controllers = 1,
 187         .ops            = &it8152_ops,
 188         .setup          = it8152_pci_setup,
 189         .preinit        = cmx2xx_pci_preinit,
 190 };
 191
 192 static int __init cmx2xx_init_pci(void)
 193 {
 194         if (machine_is_armcore())
 195                 pci_common_init(&cmx2xx_pci);
 196
 197         return 0;
 198 }
 199
 200 subsys_initcall(cmx2xx_init_pci);