arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21
  22 #include <linux/omap-dma.h>
  23 #include "l3_3xxx.h"
  24 #include "l4_3xxx.h"
  25 #include <linux/platform_data/asoc-ti-mcbsp.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/iommu-omap.h>
  28 #include <linux/platform_data/mailbox-omap.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "am35xx.h"
  32
  33 #include "soc.h"
  34 #include "omap_hwmod.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "cm-regbits-34xx.h"
  38
  39 #include "i2c.h"
  40 #include "mmc.h"
  41 #include "wd_timer.h"
  42 #include "serial.h"
  43
  44 /*
  45  * OMAP3xxx hardware module integration data
  46  *
  47  * All of the data in this section should be autogeneratable from the
  48  * TI hardware database or other technical documentation.  Data that
  49  * is driver-specific or driver-kernel integration-specific belongs
  50  * elsewhere.
  51  */
  52
  53 /*
  54  * IP blocks
  55  */
  56
  57 /* L3 */
  58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  59         { .irq = 9 + OMAP_INTC_START, },
  60         { .irq = 10 + OMAP_INTC_START, },
  61         { .irq = -1 },
  62 };
  63
  64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  65         .name           = "l3_main",
  66         .class          = &l3_hwmod_class,
  67         .mpu_irqs       = omap3xxx_l3_main_irqs,
  68         .flags          = HWMOD_NO_IDLEST,
  69 };
  70
  71 /* L4 CORE */
  72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  73         .name           = "l4_core",
  74         .class          = &l4_hwmod_class,
  75         .flags          = HWMOD_NO_IDLEST,
  76 };
  77
  78 /* L4 PER */
  79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  80         .name           = "l4_per",
  81         .class          = &l4_hwmod_class,
  82         .flags          = HWMOD_NO_IDLEST,
  83 };
  84
  85 /* L4 WKUP */
  86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  87         .name           = "l4_wkup",
  88         .class          = &l4_hwmod_class,
  89         .flags          = HWMOD_NO_IDLEST,
  90 };
  91
  92 /* L4 SEC */
  93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  94         .name           = "l4_sec",
  95         .class          = &l4_hwmod_class,
  96         .flags          = HWMOD_NO_IDLEST,
  97 };
  98
  99 /* MPU */
 100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
 101         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 102         { .irq = -1 }
 103 };
 104
 105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 106         .name           = "mpu",
 107         .mpu_irqs       = omap3xxx_mpu_irqs,
 108         .class          = &mpu_hwmod_class,
 109         .main_clk       = "arm_fck",
 110 };
 111
 112 /* IVA2 (IVA2) */
 113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 114         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 115         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 116         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 117 };
 118
 119 static struct omap_hwmod omap3xxx_iva_hwmod = {
 120         .name           = "iva",
 121         .class          = &iva_hwmod_class,
 122         .clkdm_name     = "iva2_clkdm",
 123         .rst_lines      = omap3xxx_iva_resets,
 124         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 125         .main_clk       = "iva2_ck",
 126         .prcm = {
 127                 .omap2 = {
 128                         .module_offs = OMAP3430_IVA2_MOD,
 129                         .prcm_reg_id = 1,
 130                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 131                         .idlest_reg_id = 1,
 132                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 133                 }
 134         },
 135 };
 136
 137 /*
 138  * 'debugss' class
 139  * debug and emulation sub system
 140  */
 141
 142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 143         .name   = "debugss",
 144 };
 145
 146 /* debugss */
 147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 148         .name           = "debugss",
 149         .class          = &omap3xxx_debugss_hwmod_class,
 150         .clkdm_name     = "emu_clkdm",
 151         .main_clk       = "emu_src_ck",
 152         .flags          = HWMOD_NO_IDLEST,
 153 };
 154
 155 /* timer class */
 156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 157         .rev_offs       = 0x0000,
 158         .sysc_offs      = 0x0010,
 159         .syss_offs      = 0x0014,
 160         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 161                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 162                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 163                            SYSS_HAS_RESET_STATUS),
 164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 165         .clockact       = CLOCKACT_TEST_ICLK,
 166         .sysc_fields    = &omap_hwmod_sysc_type1,
 167 };
 168
 169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 170         .name = "timer",
 171         .sysc = &omap3xxx_timer_sysc,
 172 };
 173
 174 /* secure timers dev attribute */
 175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 176         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 177 };
 178
 179 /* always-on timers dev attribute */
 180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 181         .timer_capability       = OMAP_TIMER_ALWON,
 182 };
 183
 184 /* pwm timers dev attribute */
 185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 186         .timer_capability       = OMAP_TIMER_HAS_PWM,
 187 };
 188
 189 /* timers with DSP interrupt dev attribute */
 190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 191         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 192 };
 193
 194 /* pwm timers with DSP interrupt dev attribute */
 195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 196         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 197 };
 198
 199 /* timer1 */
 200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 201         .name           = "timer1",
 202         .mpu_irqs       = omap2_timer1_mpu_irqs,
 203         .main_clk       = "gpt1_fck",
 204         .prcm           = {
 205                 .omap2 = {
 206                         .prcm_reg_id = 1,
 207                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 208                         .module_offs = WKUP_MOD,
 209                         .idlest_reg_id = 1,
 210                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 211                 },
 212         },
 213         .dev_attr       = &capability_alwon_dev_attr,
 214         .class          = &omap3xxx_timer_hwmod_class,
 215         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 216 };
 217
 218 /* timer2 */
 219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 220         .name           = "timer2",
 221         .mpu_irqs       = omap2_timer2_mpu_irqs,
 222         .main_clk       = "gpt2_fck",
 223         .prcm           = {
 224                 .omap2 = {
 225                         .prcm_reg_id = 1,
 226                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 227                         .module_offs = OMAP3430_PER_MOD,
 228                         .idlest_reg_id = 1,
 229                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 230                 },
 231         },
 232         .class          = &omap3xxx_timer_hwmod_class,
 233         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 234 };
 235
 236 /* timer3 */
 237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 238         .name           = "timer3",
 239         .mpu_irqs       = omap2_timer3_mpu_irqs,
 240         .main_clk       = "gpt3_fck",
 241         .prcm           = {
 242                 .omap2 = {
 243                         .prcm_reg_id = 1,
 244                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 245                         .module_offs = OMAP3430_PER_MOD,
 246                         .idlest_reg_id = 1,
 247                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 248                 },
 249         },
 250         .class          = &omap3xxx_timer_hwmod_class,
 251         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 252 };
 253
 254 /* timer4 */
 255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 256         .name           = "timer4",
 257         .mpu_irqs       = omap2_timer4_mpu_irqs,
 258         .main_clk       = "gpt4_fck",
 259         .prcm           = {
 260                 .omap2 = {
 261                         .prcm_reg_id = 1,
 262                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 263                         .module_offs = OMAP3430_PER_MOD,
 264                         .idlest_reg_id = 1,
 265                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 266                 },
 267         },
 268         .class          = &omap3xxx_timer_hwmod_class,
 269         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 270 };
 271
 272 /* timer5 */
 273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 274         .name           = "timer5",
 275         .mpu_irqs       = omap2_timer5_mpu_irqs,
 276         .main_clk       = "gpt5_fck",
 277         .prcm           = {
 278                 .omap2 = {
 279                         .prcm_reg_id = 1,
 280                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 281                         .module_offs = OMAP3430_PER_MOD,
 282                         .idlest_reg_id = 1,
 283                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 284                 },
 285         },
 286         .dev_attr       = &capability_dsp_dev_attr,
 287         .class          = &omap3xxx_timer_hwmod_class,
 288         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 289 };
 290
 291 /* timer6 */
 292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 293         .name           = "timer6",
 294         .mpu_irqs       = omap2_timer6_mpu_irqs,
 295         .main_clk       = "gpt6_fck",
 296         .prcm           = {
 297                 .omap2 = {
 298                         .prcm_reg_id = 1,
 299                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 300                         .module_offs = OMAP3430_PER_MOD,
 301                         .idlest_reg_id = 1,
 302                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 303                 },
 304         },
 305         .dev_attr       = &capability_dsp_dev_attr,
 306         .class          = &omap3xxx_timer_hwmod_class,
 307         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 308 };
 309
 310 /* timer7 */
 311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 312         .name           = "timer7",
 313         .mpu_irqs       = omap2_timer7_mpu_irqs,
 314         .main_clk       = "gpt7_fck",
 315         .prcm           = {
 316                 .omap2 = {
 317                         .prcm_reg_id = 1,
 318                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 319                         .module_offs = OMAP3430_PER_MOD,
 320                         .idlest_reg_id = 1,
 321                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 322                 },
 323         },
 324         .dev_attr       = &capability_dsp_dev_attr,
 325         .class          = &omap3xxx_timer_hwmod_class,
 326         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 327 };
 328
 329 /* timer8 */
 330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 331         .name           = "timer8",
 332         .mpu_irqs       = omap2_timer8_mpu_irqs,
 333         .main_clk       = "gpt8_fck",
 334         .prcm           = {
 335                 .omap2 = {
 336                         .prcm_reg_id = 1,
 337                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 338                         .module_offs = OMAP3430_PER_MOD,
 339                         .idlest_reg_id = 1,
 340                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 341                 },
 342         },
 343         .dev_attr       = &capability_dsp_pwm_dev_attr,
 344         .class          = &omap3xxx_timer_hwmod_class,
 345         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 346 };
 347
 348 /* timer9 */
 349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 350         .name           = "timer9",
 351         .mpu_irqs       = omap2_timer9_mpu_irqs,
 352         .main_clk       = "gpt9_fck",
 353         .prcm           = {
 354                 .omap2 = {
 355                         .prcm_reg_id = 1,
 356                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 357                         .module_offs = OMAP3430_PER_MOD,
 358                         .idlest_reg_id = 1,
 359                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 360                 },
 361         },
 362         .dev_attr       = &capability_pwm_dev_attr,
 363         .class          = &omap3xxx_timer_hwmod_class,
 364         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 365 };
 366
 367 /* timer10 */
 368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 369         .name           = "timer10",
 370         .mpu_irqs       = omap2_timer10_mpu_irqs,
 371         .main_clk       = "gpt10_fck",
 372         .prcm           = {
 373                 .omap2 = {
 374                         .prcm_reg_id = 1,
 375                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 376                         .module_offs = CORE_MOD,
 377                         .idlest_reg_id = 1,
 378                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 379                 },
 380         },
 381         .dev_attr       = &capability_pwm_dev_attr,
 382         .class          = &omap3xxx_timer_hwmod_class,
 383         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 384 };
 385
 386 /* timer11 */
 387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 388         .name           = "timer11",
 389         .mpu_irqs       = omap2_timer11_mpu_irqs,
 390         .main_clk       = "gpt11_fck",
 391         .prcm           = {
 392                 .omap2 = {
 393                         .prcm_reg_id = 1,
 394                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 395                         .module_offs = CORE_MOD,
 396                         .idlest_reg_id = 1,
 397                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 398                 },
 399         },
 400         .dev_attr       = &capability_pwm_dev_attr,
 401         .class          = &omap3xxx_timer_hwmod_class,
 402         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 403 };
 404
 405 /* timer12 */
 406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 407         { .irq = 95 + OMAP_INTC_START, },
 408         { .irq = -1 },
 409 };
 410
 411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 412         .name           = "timer12",
 413         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 414         .main_clk       = "gpt12_fck",
 415         .prcm           = {
 416                 .omap2 = {
 417                         .prcm_reg_id = 1,
 418                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 419                         .module_offs = WKUP_MOD,
 420                         .idlest_reg_id = 1,
 421                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 422                 },
 423         },
 424         .dev_attr       = &capability_secure_dev_attr,
 425         .class          = &omap3xxx_timer_hwmod_class,
 426         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 427 };
 428
 429 /*
 430  * 'wd_timer' class
 431  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 432  * overflow condition
 433  */
 434
 435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 436         .rev_offs       = 0x0000,
 437         .sysc_offs      = 0x0010,
 438         .syss_offs      = 0x0014,
 439         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 440                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 441                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 442                            SYSS_HAS_RESET_STATUS),
 443         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 444         .sysc_fields    = &omap_hwmod_sysc_type1,
 445 };
 446
 447 /* I2C common */
 448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 449         .rev_offs       = 0x00,
 450         .sysc_offs      = 0x20,
 451         .syss_offs      = 0x10,
 452         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 453                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 454                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 455         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 456         .clockact       = CLOCKACT_TEST_ICLK,
 457         .sysc_fields    = &omap_hwmod_sysc_type1,
 458 };
 459
 460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 461         .name           = "wd_timer",
 462         .sysc           = &omap3xxx_wd_timer_sysc,
 463         .pre_shutdown   = &omap2_wd_timer_disable,
 464         .reset          = &omap2_wd_timer_reset,
 465 };
 466
 467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 468         .name           = "wd_timer2",
 469         .class          = &omap3xxx_wd_timer_hwmod_class,
 470         .main_clk       = "wdt2_fck",
 471         .prcm           = {
 472                 .omap2 = {
 473                         .prcm_reg_id = 1,
 474                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 475                         .module_offs = WKUP_MOD,
 476                         .idlest_reg_id = 1,
 477                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 478                 },
 479         },
 480         /*
 481          * XXX: Use software supervised mode, HW supervised smartidle seems to
 482          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 483          */
 484         .flags          = HWMOD_SWSUP_SIDLE,
 485 };
 486
 487 /* UART1 */
 488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 489         .name           = "uart1",
 490         .mpu_irqs       = omap2_uart1_mpu_irqs,
 491         .sdma_reqs      = omap2_uart1_sdma_reqs,
 492         .main_clk       = "uart1_fck",
 493         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 494         .prcm           = {
 495                 .omap2 = {
 496                         .module_offs = CORE_MOD,
 497                         .prcm_reg_id = 1,
 498                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 499                         .idlest_reg_id = 1,
 500                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 501                 },
 502         },
 503         .class          = &omap2_uart_class,
 504 };
 505
 506 /* UART2 */
 507 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 508         .name           = "uart2",
 509         .mpu_irqs       = omap2_uart2_mpu_irqs,
 510         .sdma_reqs      = omap2_uart2_sdma_reqs,
 511         .main_clk       = "uart2_fck",
 512         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 513         .prcm           = {
 514                 .omap2 = {
 515                         .module_offs = CORE_MOD,
 516                         .prcm_reg_id = 1,
 517                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 518                         .idlest_reg_id = 1,
 519                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 520                 },
 521         },
 522         .class          = &omap2_uart_class,
 523 };
 524
 525 /* UART3 */
 526 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 527         .name           = "uart3",
 528         .mpu_irqs       = omap2_uart3_mpu_irqs,
 529         .sdma_reqs      = omap2_uart3_sdma_reqs,
 530         .main_clk       = "uart3_fck",
 531         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 532                                 HWMOD_SWSUP_SIDLE_ACT,
 533         .prcm           = {
 534                 .omap2 = {
 535                         .module_offs = OMAP3430_PER_MOD,
 536                         .prcm_reg_id = 1,
 537                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 538                         .idlest_reg_id = 1,
 539                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 540                 },
 541         },
 542         .class          = &omap2_uart_class,
 543 };
 544
 545 /* UART4 */
 546 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 547         { .irq = 80 + OMAP_INTC_START, },
 548         { .irq = -1 },
 549 };
 550
 551 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 552         { .name = "rx", .dma_req = 82, },
 553         { .name = "tx", .dma_req = 81, },
 554         { .dma_req = -1 }
 555 };
 556
 557 static struct omap_hwmod omap36xx_uart4_hwmod = {
 558         .name           = "uart4",
 559         .mpu_irqs       = uart4_mpu_irqs,
 560         .sdma_reqs      = uart4_sdma_reqs,
 561         .main_clk       = "uart4_fck",
 562         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 563         .prcm           = {
 564                 .omap2 = {
 565                         .module_offs = OMAP3430_PER_MOD,
 566                         .prcm_reg_id = 1,
 567                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 568                         .idlest_reg_id = 1,
 569                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 570                 },
 571         },
 572         .class          = &omap2_uart_class,
 573 };
 574
 575 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 576         { .irq = 84 + OMAP_INTC_START, },
 577         { .irq = -1 },
 578 };
 579
 580 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 581         { .name = "rx", .dma_req = 55, },
 582         { .name = "tx", .dma_req = 54, },
 583         { .dma_req = -1 }
 584 };
 585
 586 /*
 587  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 588  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 589  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 590  * should not be needed.  The functional clock structure of the AM35xx
 591  * UART4 is extremely unclear and opaque; it is unclear what the role
 592  * of uart1/2_fck is for the UART4.  Any clarification from either
 593  * empirical testing or the AM3505/3517 hardware designers would be
 594  * most welcome.
 595  */
 596 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 597         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 598 };
 599
 600 static struct omap_hwmod am35xx_uart4_hwmod = {
 601         .name           = "uart4",
 602         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 603         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 604         .main_clk       = "uart4_fck",
 605         .prcm           = {
 606                 .omap2 = {
 607                         .module_offs = CORE_MOD,
 608                         .prcm_reg_id = 1,
 609                         .module_bit = AM35XX_EN_UART4_SHIFT,
 610                         .idlest_reg_id = 1,
 611                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 612                 },
 613         },
 614         .opt_clks       = am35xx_uart4_opt_clks,
 615         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 616         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 617         .class          = &omap2_uart_class,
 618 };
 619
 620 static struct omap_hwmod_class i2c_class = {
 621         .name   = "i2c",
 622         .sysc   = &i2c_sysc,
 623         .rev    = OMAP_I2C_IP_VERSION_1,
 624         .reset  = &omap_i2c_reset,
 625 };
 626
 627 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 628         { .name = "dispc", .dma_req = 5 },
 629         { .name = "dsi1", .dma_req = 74 },
 630         { .dma_req = -1 }
 631 };
 632
 633 /* dss */
 634 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 635         /*
 636          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 637          * driver does not use these clocks.
 638          */
 639         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 640         { .role = "tv_clk", .clk = "dss_tv_fck" },
 641         /* required only on OMAP3430 */
 642         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 643 };
 644
 645 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 646         .name           = "dss_core",
 647         .class          = &omap2_dss_hwmod_class,
 648         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 649         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 650         .prcm           = {
 651                 .omap2 = {
 652                         .prcm_reg_id = 1,
 653                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 654                         .module_offs = OMAP3430_DSS_MOD,
 655                         .idlest_reg_id = 1,
 656                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 657                 },
 658         },
 659         .opt_clks       = dss_opt_clks,
 660         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 661         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 662 };
 663
 664 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 665         .name           = "dss_core",
 666         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 667         .class          = &omap2_dss_hwmod_class,
 668         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 669         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 670         .prcm           = {
 671                 .omap2 = {
 672                         .prcm_reg_id = 1,
 673                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 674                         .module_offs = OMAP3430_DSS_MOD,
 675                         .idlest_reg_id = 1,
 676                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 677                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 678                 },
 679         },
 680         .opt_clks       = dss_opt_clks,
 681         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 682 };
 683
 684 /*
 685  * 'dispc' class
 686  * display controller
 687  */
 688
 689 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 690         .rev_offs       = 0x0000,
 691         .sysc_offs      = 0x0010,
 692         .syss_offs      = 0x0014,
 693         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 694                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 695                            SYSC_HAS_ENAWAKEUP),
 696         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 697                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 698         .sysc_fields    = &omap_hwmod_sysc_type1,
 699 };
 700
 701 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 702         .name   = "dispc",
 703         .sysc   = &omap3_dispc_sysc,
 704 };
 705
 706 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 707         .name           = "dss_dispc",
 708         .class          = &omap3_dispc_hwmod_class,
 709         .mpu_irqs       = omap2_dispc_irqs,
 710         .main_clk       = "dss1_alwon_fck",
 711         .prcm           = {
 712                 .omap2 = {
 713                         .prcm_reg_id = 1,
 714                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 715                         .module_offs = OMAP3430_DSS_MOD,
 716                 },
 717         },
 718         .flags          = HWMOD_NO_IDLEST,
 719         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 720 };
 721
 722 /*
 723  * 'dsi' class
 724  * display serial interface controller
 725  */
 726
 727 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 728         .name = "dsi",
 729 };
 730
 731 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 732         { .irq = 25 + OMAP_INTC_START, },
 733         { .irq = -1 },
 734 };
 735
 736 /* dss_dsi1 */
 737 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 738         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 739 };
 740
 741 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 742         .name           = "dss_dsi1",
 743         .class          = &omap3xxx_dsi_hwmod_class,
 744         .mpu_irqs       = omap3xxx_dsi1_irqs,
 745         .main_clk       = "dss1_alwon_fck",
 746         .prcm           = {
 747                 .omap2 = {
 748                         .prcm_reg_id = 1,
 749                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 750                         .module_offs = OMAP3430_DSS_MOD,
 751                 },
 752         },
 753         .opt_clks       = dss_dsi1_opt_clks,
 754         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 755         .flags          = HWMOD_NO_IDLEST,
 756 };
 757
 758 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 759         { .role = "ick", .clk = "dss_ick" },
 760 };
 761
 762 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 763         .name           = "dss_rfbi",
 764         .class          = &omap2_rfbi_hwmod_class,
 765         .main_clk       = "dss1_alwon_fck",
 766         .prcm           = {
 767                 .omap2 = {
 768                         .prcm_reg_id = 1,
 769                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 770                         .module_offs = OMAP3430_DSS_MOD,
 771                 },
 772         },
 773         .opt_clks       = dss_rfbi_opt_clks,
 774         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 775         .flags          = HWMOD_NO_IDLEST,
 776 };
 777
 778 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 779         /* required only on OMAP3430 */
 780         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 781 };
 782
 783 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 784         .name           = "dss_venc",
 785         .class          = &omap2_venc_hwmod_class,
 786         .main_clk       = "dss_tv_fck",
 787         .prcm           = {
 788                 .omap2 = {
 789                         .prcm_reg_id = 1,
 790                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 791                         .module_offs = OMAP3430_DSS_MOD,
 792                 },
 793         },
 794         .opt_clks       = dss_venc_opt_clks,
 795         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 796         .flags          = HWMOD_NO_IDLEST,
 797 };
 798
 799 /* I2C1 */
 800 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 801         .fifo_depth     = 8, /* bytes */
 802         .flags          = OMAP_I2C_FLAG_BUS_SHIFT_2,
 803 };
 804
 805 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 806         .name           = "i2c1",
 807         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 808         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 809         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 810         .main_clk       = "i2c1_fck",
 811         .prcm           = {
 812                 .omap2 = {
 813                         .module_offs = CORE_MOD,
 814                         .prcm_reg_id = 1,
 815                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 816                         .idlest_reg_id = 1,
 817                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 818                 },
 819         },
 820         .class          = &i2c_class,
 821         .dev_attr       = &i2c1_dev_attr,
 822 };
 823
 824 /* I2C2 */
 825 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 826         .fifo_depth     = 8, /* bytes */
 827         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 828 };
 829
 830 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 831         .name           = "i2c2",
 832         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 833         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 834         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 835         .main_clk       = "i2c2_fck",
 836         .prcm           = {
 837                 .omap2 = {
 838                         .module_offs = CORE_MOD,
 839                         .prcm_reg_id = 1,
 840                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 841                         .idlest_reg_id = 1,
 842                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 843                 },
 844         },
 845         .class          = &i2c_class,
 846         .dev_attr       = &i2c2_dev_attr,
 847 };
 848
 849 /* I2C3 */
 850 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 851         .fifo_depth     = 64, /* bytes */
 852         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
 853 };
 854
 855 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 856         { .irq = 61 + OMAP_INTC_START, },
 857         { .irq = -1 },
 858 };
 859
 860 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 861         { .name = "tx", .dma_req = 25 },
 862         { .name = "rx", .dma_req = 26 },
 863         { .dma_req = -1 }
 864 };
 865
 866 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 867         .name           = "i2c3",
 868         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 869         .mpu_irqs       = i2c3_mpu_irqs,
 870         .sdma_reqs      = i2c3_sdma_reqs,
 871         .main_clk       = "i2c3_fck",
 872         .prcm           = {
 873                 .omap2 = {
 874                         .module_offs = CORE_MOD,
 875                         .prcm_reg_id = 1,
 876                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 877                         .idlest_reg_id = 1,
 878                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 879                 },
 880         },
 881         .class          = &i2c_class,
 882         .dev_attr       = &i2c3_dev_attr,
 883 };
 884
 885 /*
 886  * 'gpio' class
 887  * general purpose io module
 888  */
 889
 890 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 891         .rev_offs       = 0x0000,
 892         .sysc_offs      = 0x0010,
 893         .syss_offs      = 0x0014,
 894         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 895                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 896                            SYSS_HAS_RESET_STATUS),
 897         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 898         .sysc_fields    = &omap_hwmod_sysc_type1,
 899 };
 900
 901 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 902         .name = "gpio",
 903         .sysc = &omap3xxx_gpio_sysc,
 904         .rev = 1,
 905 };
 906
 907 /* gpio_dev_attr */
 908 static struct omap_gpio_dev_attr gpio_dev_attr = {
 909         .bank_width = 32,
 910         .dbck_flag = true,
 911 };
 912
 913 /* gpio1 */
 914 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 915         { .role = "dbclk", .clk = "gpio1_dbck", },
 916 };
 917
 918 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 919         .name           = "gpio1",
 920         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 921         .mpu_irqs       = omap2_gpio1_irqs,
 922         .main_clk       = "gpio1_ick",
 923         .opt_clks       = gpio1_opt_clks,
 924         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 925         .prcm           = {
 926                 .omap2 = {
 927                         .prcm_reg_id = 1,
 928                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 929                         .module_offs = WKUP_MOD,
 930                         .idlest_reg_id = 1,
 931                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 932                 },
 933         },
 934         .class          = &omap3xxx_gpio_hwmod_class,
 935         .dev_attr       = &gpio_dev_attr,
 936 };
 937
 938 /* gpio2 */
 939 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 940         { .role = "dbclk", .clk = "gpio2_dbck", },
 941 };
 942
 943 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 944         .name           = "gpio2",
 945         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 946         .mpu_irqs       = omap2_gpio2_irqs,
 947         .main_clk       = "gpio2_ick",
 948         .opt_clks       = gpio2_opt_clks,
 949         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 950         .prcm           = {
 951                 .omap2 = {
 952                         .prcm_reg_id = 1,
 953                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 954                         .module_offs = OMAP3430_PER_MOD,
 955                         .idlest_reg_id = 1,
 956                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 957                 },
 958         },
 959         .class          = &omap3xxx_gpio_hwmod_class,
 960         .dev_attr       = &gpio_dev_attr,
 961 };
 962
 963 /* gpio3 */
 964 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 965         { .role = "dbclk", .clk = "gpio3_dbck", },
 966 };
 967
 968 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 969         .name           = "gpio3",
 970         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 971         .mpu_irqs       = omap2_gpio3_irqs,
 972         .main_clk       = "gpio3_ick",
 973         .opt_clks       = gpio3_opt_clks,
 974         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 975         .prcm           = {
 976                 .omap2 = {
 977                         .prcm_reg_id = 1,
 978                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 979                         .module_offs = OMAP3430_PER_MOD,
 980                         .idlest_reg_id = 1,
 981                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 982                 },
 983         },
 984         .class          = &omap3xxx_gpio_hwmod_class,
 985         .dev_attr       = &gpio_dev_attr,
 986 };
 987
 988 /* gpio4 */
 989 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 990         { .role = "dbclk", .clk = "gpio4_dbck", },
 991 };
 992
 993 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 994         .name           = "gpio4",
 995         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 996         .mpu_irqs       = omap2_gpio4_irqs,
 997         .main_clk       = "gpio4_ick",
 998         .opt_clks       = gpio4_opt_clks,
 999         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1000         .prcm           = {
1001                 .omap2 = {
1002                         .prcm_reg_id = 1,
1003                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1004                         .module_offs = OMAP3430_PER_MOD,
1005                         .idlest_reg_id = 1,
1006                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1007                 },
1008         },
1009         .class          = &omap3xxx_gpio_hwmod_class,
1010         .dev_attr       = &gpio_dev_attr,
1011 };
1012
1013 /* gpio5 */
1014 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1015         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1016         { .irq = -1 },
1017 };
1018
1019 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1020         { .role = "dbclk", .clk = "gpio5_dbck", },
1021 };
1022
1023 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1024         .name           = "gpio5",
1025         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1026         .mpu_irqs       = omap3xxx_gpio5_irqs,
1027         .main_clk       = "gpio5_ick",
1028         .opt_clks       = gpio5_opt_clks,
1029         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1030         .prcm           = {
1031                 .omap2 = {
1032                         .prcm_reg_id = 1,
1033                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1034                         .module_offs = OMAP3430_PER_MOD,
1035                         .idlest_reg_id = 1,
1036                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1037                 },
1038         },
1039         .class          = &omap3xxx_gpio_hwmod_class,
1040         .dev_attr       = &gpio_dev_attr,
1041 };
1042
1043 /* gpio6 */
1044 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1045         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1046         { .irq = -1 },
1047 };
1048
1049 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1050         { .role = "dbclk", .clk = "gpio6_dbck", },
1051 };
1052
1053 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1054         .name           = "gpio6",
1055         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1056         .mpu_irqs       = omap3xxx_gpio6_irqs,
1057         .main_clk       = "gpio6_ick",
1058         .opt_clks       = gpio6_opt_clks,
1059         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1060         .prcm           = {
1061                 .omap2 = {
1062                         .prcm_reg_id = 1,
1063                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1064                         .module_offs = OMAP3430_PER_MOD,
1065                         .idlest_reg_id = 1,
1066                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1067                 },
1068         },
1069         .class          = &omap3xxx_gpio_hwmod_class,
1070         .dev_attr       = &gpio_dev_attr,
1071 };
1072
1073 /* dma attributes */
1074 static struct omap_dma_dev_attr dma_dev_attr = {
1075         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1076                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1077         .lch_count = 32,
1078 };
1079
1080 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1081         .rev_offs       = 0x0000,
1082         .sysc_offs      = 0x002c,
1083         .syss_offs      = 0x0028,
1084         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1085                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1086                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1087                            SYSS_HAS_RESET_STATUS),
1088         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1090         .sysc_fields    = &omap_hwmod_sysc_type1,
1091 };
1092
1093 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1094         .name = "dma",
1095         .sysc = &omap3xxx_dma_sysc,
1096 };
1097
1098 /* dma_system */
1099 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1100         .name           = "dma",
1101         .class          = &omap3xxx_dma_hwmod_class,
1102         .mpu_irqs       = omap2_dma_system_irqs,
1103         .main_clk       = "core_l3_ick",
1104         .prcm = {
1105                 .omap2 = {
1106                         .module_offs            = CORE_MOD,
1107                         .prcm_reg_id            = 1,
1108                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1109                         .idlest_reg_id          = 1,
1110                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1111                 },
1112         },
1113         .dev_attr       = &dma_dev_attr,
1114         .flags          = HWMOD_NO_IDLEST,
1115 };
1116
1117 /*
1118  * 'mcbsp' class
1119  * multi channel buffered serial port controller
1120  */
1121
1122 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1123         .sysc_offs      = 0x008c,
1124         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1125                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1126         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1127         .sysc_fields    = &omap_hwmod_sysc_type1,
1128         .clockact       = 0x2,
1129 };
1130
1131 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1132         .name = "mcbsp",
1133         .sysc = &omap3xxx_mcbsp_sysc,
1134         .rev  = MCBSP_CONFIG_TYPE3,
1135 };
1136
1137 /* McBSP functional clock mapping */
1138 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1139         { .role = "pad_fck", .clk = "mcbsp_clks" },
1140         { .role = "prcm_fck", .clk = "core_96m_fck" },
1141 };
1142
1143 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1144         { .role = "pad_fck", .clk = "mcbsp_clks" },
1145         { .role = "prcm_fck", .clk = "per_96m_fck" },
1146 };
1147
1148 /* mcbsp1 */
1149 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1150         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1151         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1152         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1153         { .irq = -1 },
1154 };
1155
1156 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1157         .name           = "mcbsp1",
1158         .class          = &omap3xxx_mcbsp_hwmod_class,
1159         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1160         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1161         .main_clk       = "mcbsp1_fck",
1162         .prcm           = {
1163                 .omap2 = {
1164                         .prcm_reg_id = 1,
1165                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1166                         .module_offs = CORE_MOD,
1167                         .idlest_reg_id = 1,
1168                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1169                 },
1170         },
1171         .opt_clks       = mcbsp15_opt_clks,
1172         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1173 };
1174
1175 /* mcbsp2 */
1176 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1177         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1178         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1179         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1180         { .irq = -1 },
1181 };
1182
1183 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1184         .sidetone       = "mcbsp2_sidetone",
1185 };
1186
1187 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1188         .name           = "mcbsp2",
1189         .class          = &omap3xxx_mcbsp_hwmod_class,
1190         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1191         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1192         .main_clk       = "mcbsp2_fck",
1193         .prcm           = {
1194                 .omap2 = {
1195                         .prcm_reg_id = 1,
1196                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1197                         .module_offs = OMAP3430_PER_MOD,
1198                         .idlest_reg_id = 1,
1199                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1200                 },
1201         },
1202         .opt_clks       = mcbsp234_opt_clks,
1203         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1204         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1205 };
1206
1207 /* mcbsp3 */
1208 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1209         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1210         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1211         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1212         { .irq = -1 },
1213 };
1214
1215 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1216         .sidetone       = "mcbsp3_sidetone",
1217 };
1218
1219 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1220         .name           = "mcbsp3",
1221         .class          = &omap3xxx_mcbsp_hwmod_class,
1222         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1223         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1224         .main_clk       = "mcbsp3_fck",
1225         .prcm           = {
1226                 .omap2 = {
1227                         .prcm_reg_id = 1,
1228                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1229                         .module_offs = OMAP3430_PER_MOD,
1230                         .idlest_reg_id = 1,
1231                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1232                 },
1233         },
1234         .opt_clks       = mcbsp234_opt_clks,
1235         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1236         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1237 };
1238
1239 /* mcbsp4 */
1240 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1241         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1242         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1243         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1244         { .irq = -1 },
1245 };
1246
1247 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1248         { .name = "rx", .dma_req = 20 },
1249         { .name = "tx", .dma_req = 19 },
1250         { .dma_req = -1 }
1251 };
1252
1253 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1254         .name           = "mcbsp4",
1255         .class          = &omap3xxx_mcbsp_hwmod_class,
1256         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1257         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1258         .main_clk       = "mcbsp4_fck",
1259         .prcm           = {
1260                 .omap2 = {
1261                         .prcm_reg_id = 1,
1262                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1263                         .module_offs = OMAP3430_PER_MOD,
1264                         .idlest_reg_id = 1,
1265                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1266                 },
1267         },
1268         .opt_clks       = mcbsp234_opt_clks,
1269         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1270 };
1271
1272 /* mcbsp5 */
1273 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1274         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1275         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1276         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1277         { .irq = -1 },
1278 };
1279
1280 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1281         { .name = "rx", .dma_req = 22 },
1282         { .name = "tx", .dma_req = 21 },
1283         { .dma_req = -1 }
1284 };
1285
1286 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1287         .name           = "mcbsp5",
1288         .class          = &omap3xxx_mcbsp_hwmod_class,
1289         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1290         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1291         .main_clk       = "mcbsp5_fck",
1292         .prcm           = {
1293                 .omap2 = {
1294                         .prcm_reg_id = 1,
1295                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1296                         .module_offs = CORE_MOD,
1297                         .idlest_reg_id = 1,
1298                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1299                 },
1300         },
1301         .opt_clks       = mcbsp15_opt_clks,
1302         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1303 };
1304
1305 /* 'mcbsp sidetone' class */
1306 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1307         .sysc_offs      = 0x0010,
1308         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1309         .sysc_fields    = &omap_hwmod_sysc_type1,
1310 };
1311
1312 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1313         .name = "mcbsp_sidetone",
1314         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1315 };
1316
1317 /* mcbsp2_sidetone */
1318 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1319         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1320         { .irq = -1 },
1321 };
1322
1323 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1324         .name           = "mcbsp2_sidetone",
1325         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1326         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1327         .main_clk       = "mcbsp2_fck",
1328         .prcm           = {
1329                 .omap2 = {
1330                         .prcm_reg_id = 1,
1331                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1332                         .module_offs = OMAP3430_PER_MOD,
1333                         .idlest_reg_id = 1,
1334                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1335                 },
1336         },
1337 };
1338
1339 /* mcbsp3_sidetone */
1340 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1341         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1342         { .irq = -1 },
1343 };
1344
1345 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1346         .name           = "mcbsp3_sidetone",
1347         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1348         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1349         .main_clk       = "mcbsp3_fck",
1350         .prcm           = {
1351                 .omap2 = {
1352                         .prcm_reg_id = 1,
1353                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1354                         .module_offs = OMAP3430_PER_MOD,
1355                         .idlest_reg_id = 1,
1356                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1357                 },
1358         },
1359 };
1360
1361 /* SR common */
1362 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1363         .clkact_shift   = 20,
1364 };
1365
1366 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1367         .sysc_offs      = 0x24,
1368         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1369         .clockact       = CLOCKACT_TEST_ICLK,
1370         .sysc_fields    = &omap34xx_sr_sysc_fields,
1371 };
1372
1373 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1374         .name = "smartreflex",
1375         .sysc = &omap34xx_sr_sysc,
1376         .rev  = 1,
1377 };
1378
1379 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1380         .sidle_shift    = 24,
1381         .enwkup_shift   = 26,
1382 };
1383
1384 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1385         .sysc_offs      = 0x38,
1386         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1387         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1388                         SYSC_NO_CACHE),
1389         .sysc_fields    = &omap36xx_sr_sysc_fields,
1390 };
1391
1392 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1393         .name = "smartreflex",
1394         .sysc = &omap36xx_sr_sysc,
1395         .rev  = 2,
1396 };
1397
1398 /* SR1 */
1399 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1400         .sensor_voltdm_name   = "mpu_iva",
1401 };
1402
1403 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1404         { .irq = 18 + OMAP_INTC_START, },
1405         { .irq = -1 },
1406 };
1407
1408 static struct omap_hwmod omap34xx_sr1_hwmod = {
1409         .name           = "smartreflex_mpu_iva",
1410         .class          = &omap34xx_smartreflex_hwmod_class,
1411         .main_clk       = "sr1_fck",
1412         .prcm           = {
1413                 .omap2 = {
1414                         .prcm_reg_id = 1,
1415                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1416                         .module_offs = WKUP_MOD,
1417                         .idlest_reg_id = 1,
1418                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1419                 },
1420         },
1421         .dev_attr       = &sr1_dev_attr,
1422         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1423         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1424 };
1425
1426 static struct omap_hwmod omap36xx_sr1_hwmod = {
1427         .name           = "smartreflex_mpu_iva",
1428         .class          = &omap36xx_smartreflex_hwmod_class,
1429         .main_clk       = "sr1_fck",
1430         .prcm           = {
1431                 .omap2 = {
1432                         .prcm_reg_id = 1,
1433                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1434                         .module_offs = WKUP_MOD,
1435                         .idlest_reg_id = 1,
1436                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1437                 },
1438         },
1439         .dev_attr       = &sr1_dev_attr,
1440         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1441 };
1442
1443 /* SR2 */
1444 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1445         .sensor_voltdm_name     = "core",
1446 };
1447
1448 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1449         { .irq = 19 + OMAP_INTC_START, },
1450         { .irq = -1 },
1451 };
1452
1453 static struct omap_hwmod omap34xx_sr2_hwmod = {
1454         .name           = "smartreflex_core",
1455         .class          = &omap34xx_smartreflex_hwmod_class,
1456         .main_clk       = "sr2_fck",
1457         .prcm           = {
1458                 .omap2 = {
1459                         .prcm_reg_id = 1,
1460                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1461                         .module_offs = WKUP_MOD,
1462                         .idlest_reg_id = 1,
1463                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1464                 },
1465         },
1466         .dev_attr       = &sr2_dev_attr,
1467         .mpu_irqs       = omap3_smartreflex_core_irqs,
1468         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1469 };
1470
1471 static struct omap_hwmod omap36xx_sr2_hwmod = {
1472         .name           = "smartreflex_core",
1473         .class          = &omap36xx_smartreflex_hwmod_class,
1474         .main_clk       = "sr2_fck",
1475         .prcm           = {
1476                 .omap2 = {
1477                         .prcm_reg_id = 1,
1478                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1479                         .module_offs = WKUP_MOD,
1480                         .idlest_reg_id = 1,
1481                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1482                 },
1483         },
1484         .dev_attr       = &sr2_dev_attr,
1485         .mpu_irqs       = omap3_smartreflex_core_irqs,
1486 };
1487
1488 /*
1489  * 'mailbox' class
1490  * mailbox module allowing communication between the on-chip processors
1491  * using a queued mailbox-interrupt mechanism.
1492  */
1493
1494 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1495         .rev_offs       = 0x000,
1496         .sysc_offs      = 0x010,
1497         .syss_offs      = 0x014,
1498         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1499                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1500         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1501         .sysc_fields    = &omap_hwmod_sysc_type1,
1502 };
1503
1504 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1505         .name = "mailbox",
1506         .sysc = &omap3xxx_mailbox_sysc,
1507 };
1508
1509 static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
1510         { .name = "dsp", .tx_id = 0, .rx_id = 1 },
1511 };
1512
1513 static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
1514         .num_users      = 2,
1515         .num_fifos      = 2,
1516         .info_cnt       = ARRAY_SIZE(omap3xxx_mailbox_info),
1517         .info           = omap3xxx_mailbox_info,
1518 };
1519
1520 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1521         { .irq = 26 + OMAP_INTC_START, },
1522         { .irq = -1 },
1523 };
1524
1525 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1526         .name           = "mailbox",
1527         .class          = &omap3xxx_mailbox_hwmod_class,
1528         .mpu_irqs       = omap3xxx_mailbox_irqs,
1529         .main_clk       = "mailboxes_ick",
1530         .prcm           = {
1531                 .omap2 = {
1532                         .prcm_reg_id = 1,
1533                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1534                         .module_offs = CORE_MOD,
1535                         .idlest_reg_id = 1,
1536                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1537                 },
1538         },
1539         .dev_attr       = &omap3xxx_mailbox_attrs,
1540 };
1541
1542 /*
1543  * 'mcspi' class
1544  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1545  * bus
1546  */
1547
1548 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1549         .rev_offs       = 0x0000,
1550         .sysc_offs      = 0x0010,
1551         .syss_offs      = 0x0014,
1552         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1553                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1554                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1555         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1556         .sysc_fields    = &omap_hwmod_sysc_type1,
1557 };
1558
1559 static struct omap_hwmod_class omap34xx_mcspi_class = {
1560         .name = "mcspi",
1561         .sysc = &omap34xx_mcspi_sysc,
1562         .rev = OMAP3_MCSPI_REV,
1563 };
1564
1565 /* mcspi1 */
1566 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1567         .num_chipselect = 4,
1568 };
1569
1570 static struct omap_hwmod omap34xx_mcspi1 = {
1571         .name           = "mcspi1",
1572         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1573         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1574         .main_clk       = "mcspi1_fck",
1575         .prcm           = {
1576                 .omap2 = {
1577                         .module_offs = CORE_MOD,
1578                         .prcm_reg_id = 1,
1579                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1580                         .idlest_reg_id = 1,
1581                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1582                 },
1583         },
1584         .class          = &omap34xx_mcspi_class,
1585         .dev_attr       = &omap_mcspi1_dev_attr,
1586 };
1587
1588 /* mcspi2 */
1589 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1590         .num_chipselect = 2,
1591 };
1592
1593 static struct omap_hwmod omap34xx_mcspi2 = {
1594         .name           = "mcspi2",
1595         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1596         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1597         .main_clk       = "mcspi2_fck",
1598         .prcm           = {
1599                 .omap2 = {
1600                         .module_offs = CORE_MOD,
1601                         .prcm_reg_id = 1,
1602                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1603                         .idlest_reg_id = 1,
1604                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1605                 },
1606         },
1607         .class          = &omap34xx_mcspi_class,
1608         .dev_attr       = &omap_mcspi2_dev_attr,
1609 };
1610
1611 /* mcspi3 */
1612 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1613         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1614         { .irq = -1 },
1615 };
1616
1617 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1618         { .name = "tx0", .dma_req = 15 },
1619         { .name = "rx0", .dma_req = 16 },
1620         { .name = "tx1", .dma_req = 23 },
1621         { .name = "rx1", .dma_req = 24 },
1622         { .dma_req = -1 }
1623 };
1624
1625 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1626         .num_chipselect = 2,
1627 };
1628
1629 static struct omap_hwmod omap34xx_mcspi3 = {
1630         .name           = "mcspi3",
1631         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1632         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1633         .main_clk       = "mcspi3_fck",
1634         .prcm           = {
1635                 .omap2 = {
1636                         .module_offs = CORE_MOD,
1637                         .prcm_reg_id = 1,
1638                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1639                         .idlest_reg_id = 1,
1640                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1641                 },
1642         },
1643         .class          = &omap34xx_mcspi_class,
1644         .dev_attr       = &omap_mcspi3_dev_attr,
1645 };
1646
1647 /* mcspi4 */
1648 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1649         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1650         { .irq = -1 },
1651 };
1652
1653 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1654         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1655         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1656         { .dma_req = -1 }
1657 };
1658
1659 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1660         .num_chipselect = 1,
1661 };
1662
1663 static struct omap_hwmod omap34xx_mcspi4 = {
1664         .name           = "mcspi4",
1665         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1666         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1667         .main_clk       = "mcspi4_fck",
1668         .prcm           = {
1669                 .omap2 = {
1670                         .module_offs = CORE_MOD,
1671                         .prcm_reg_id = 1,
1672                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1673                         .idlest_reg_id = 1,
1674                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1675                 },
1676         },
1677         .class          = &omap34xx_mcspi_class,
1678         .dev_attr       = &omap_mcspi4_dev_attr,
1679 };
1680
1681 /* usbhsotg */
1682 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1683         .rev_offs       = 0x0400,
1684         .sysc_offs      = 0x0404,
1685         .syss_offs      = 0x0408,
1686         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1687                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1688                           SYSC_HAS_AUTOIDLE),
1689         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1690                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1691         .sysc_fields    = &omap_hwmod_sysc_type1,
1692 };
1693
1694 static struct omap_hwmod_class usbotg_class = {
1695         .name = "usbotg",
1696         .sysc = &omap3xxx_usbhsotg_sysc,
1697 };
1698
1699 /* usb_otg_hs */
1700 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1701
1702         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1703         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1704         { .irq = -1 },
1705 };
1706
1707 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1708         .name           = "usb_otg_hs",
1709         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1710         .main_clk       = "hsotgusb_ick",
1711         .prcm           = {
1712                 .omap2 = {
1713                         .prcm_reg_id = 1,
1714                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1715                         .module_offs = CORE_MOD,
1716                         .idlest_reg_id = 1,
1717                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1718                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1719                 },
1720         },
1721         .class          = &usbotg_class,
1722
1723         /*
1724          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1725          * broken when autoidle is enabled
1726          * workaround is to disable the autoidle bit at module level.
1727          *
1728          * Enabling the device in any other MIDLEMODE setting but force-idle
1729          * causes core_pwrdm not enter idle states at least on OMAP3630.
1730          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1731          * signal when MIDLEMODE is set to force-idle.
1732          */
1733         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1734                                 | HWMOD_FORCE_MSTANDBY,
1735 };
1736
1737 /* usb_otg_hs */
1738 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1739         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1740         { .irq = -1 },
1741 };
1742
1743 static struct omap_hwmod_class am35xx_usbotg_class = {
1744         .name = "am35xx_usbotg",
1745 };
1746
1747 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1748         .name           = "am35x_otg_hs",
1749         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1750         .main_clk       = "hsotgusb_fck",
1751         .class          = &am35xx_usbotg_class,
1752         .flags          = HWMOD_NO_IDLEST,
1753 };
1754
1755 /* MMC/SD/SDIO common */
1756 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1757         .rev_offs       = 0x1fc,
1758         .sysc_offs      = 0x10,
1759         .syss_offs      = 0x14,
1760         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1761                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1762                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1763         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1764         .sysc_fields    = &omap_hwmod_sysc_type1,
1765 };
1766
1767 static struct omap_hwmod_class omap34xx_mmc_class = {
1768         .name = "mmc",
1769         .sysc = &omap34xx_mmc_sysc,
1770 };
1771
1772 /* MMC/SD/SDIO1 */
1773
1774 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1775         { .irq = 83 + OMAP_INTC_START, },
1776         { .irq = -1 },
1777 };
1778
1779 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1780         { .name = "tx", .dma_req = 61, },
1781         { .name = "rx", .dma_req = 62, },
1782         { .dma_req = -1 }
1783 };
1784
1785 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1786         { .role = "dbck", .clk = "omap_32k_fck", },
1787 };
1788
1789 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1790         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1791 };
1792
1793 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1794 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1795         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1796                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1797 };
1798
1799 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1800         .name           = "mmc1",
1801         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1802         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1803         .opt_clks       = omap34xx_mmc1_opt_clks,
1804         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1805         .main_clk       = "mmchs1_fck",
1806         .prcm           = {
1807                 .omap2 = {
1808                         .module_offs = CORE_MOD,
1809                         .prcm_reg_id = 1,
1810                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1811                         .idlest_reg_id = 1,
1812                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1813                 },
1814         },
1815         .dev_attr       = &mmc1_pre_es3_dev_attr,
1816         .class          = &omap34xx_mmc_class,
1817 };
1818
1819 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1820         .name           = "mmc1",
1821         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1822         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1823         .opt_clks       = omap34xx_mmc1_opt_clks,
1824         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1825         .main_clk       = "mmchs1_fck",
1826         .prcm           = {
1827                 .omap2 = {
1828                         .module_offs = CORE_MOD,
1829                         .prcm_reg_id = 1,
1830                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1831                         .idlest_reg_id = 1,
1832                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1833                 },
1834         },
1835         .dev_attr       = &mmc1_dev_attr,
1836         .class          = &omap34xx_mmc_class,
1837 };
1838
1839 /* MMC/SD/SDIO2 */
1840
1841 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1842         { .irq = 86 + OMAP_INTC_START, },
1843         { .irq = -1 },
1844 };
1845
1846 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1847         { .name = "tx", .dma_req = 47, },
1848         { .name = "rx", .dma_req = 48, },
1849         { .dma_req = -1 }
1850 };
1851
1852 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1853         { .role = "dbck", .clk = "omap_32k_fck", },
1854 };
1855
1856 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1857 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1858         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1859 };
1860
1861 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1862         .name           = "mmc2",
1863         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1864         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1865         .opt_clks       = omap34xx_mmc2_opt_clks,
1866         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1867         .main_clk       = "mmchs2_fck",
1868         .prcm           = {
1869                 .omap2 = {
1870                         .module_offs = CORE_MOD,
1871                         .prcm_reg_id = 1,
1872                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1873                         .idlest_reg_id = 1,
1874                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1875                 },
1876         },
1877         .dev_attr       = &mmc2_pre_es3_dev_attr,
1878         .class          = &omap34xx_mmc_class,
1879 };
1880
1881 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1882         .name           = "mmc2",
1883         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1884         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1885         .opt_clks       = omap34xx_mmc2_opt_clks,
1886         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1887         .main_clk       = "mmchs2_fck",
1888         .prcm           = {
1889                 .omap2 = {
1890                         .module_offs = CORE_MOD,
1891                         .prcm_reg_id = 1,
1892                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1893                         .idlest_reg_id = 1,
1894                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1895                 },
1896         },
1897         .class          = &omap34xx_mmc_class,
1898 };
1899
1900 /* MMC/SD/SDIO3 */
1901
1902 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1903         { .irq = 94 + OMAP_INTC_START, },
1904         { .irq = -1 },
1905 };
1906
1907 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1908         { .name = "tx", .dma_req = 77, },
1909         { .name = "rx", .dma_req = 78, },
1910         { .dma_req = -1 }
1911 };
1912
1913 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1914         { .role = "dbck", .clk = "omap_32k_fck", },
1915 };
1916
1917 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1918         .name           = "mmc3",
1919         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1920         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1921         .opt_clks       = omap34xx_mmc3_opt_clks,
1922         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1923         .main_clk       = "mmchs3_fck",
1924         .prcm           = {
1925                 .omap2 = {
1926                         .prcm_reg_id = 1,
1927                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1928                         .idlest_reg_id = 1,
1929                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1930                 },
1931         },
1932         .class          = &omap34xx_mmc_class,
1933 };
1934
1935 /*
1936  * 'usb_host_hs' class
1937  * high-speed multi-port usb host controller
1938  */
1939
1940 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1941         .rev_offs       = 0x0000,
1942         .sysc_offs      = 0x0010,
1943         .syss_offs      = 0x0014,
1944         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1945                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1946                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1947                            SYSS_HAS_RESET_STATUS),
1948         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1949                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1950         .sysc_fields    = &omap_hwmod_sysc_type1,
1951 };
1952
1953 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1954         .name = "usb_host_hs",
1955         .sysc = &omap3xxx_usb_host_hs_sysc,
1956 };
1957
1958 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1959           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1960 };
1961
1962 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1963         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1964         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1965         { .irq = -1 },
1966 };
1967
1968 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1969         .name           = "usb_host_hs",
1970         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1971         .clkdm_name     = "l3_init_clkdm",
1972         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1973         .main_clk       = "usbhost_48m_fck",
1974         .prcm = {
1975                 .omap2 = {
1976                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1977                         .prcm_reg_id = 1,
1978                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1979                         .idlest_reg_id = 1,
1980                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1981                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1982                 },
1983         },
1984         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1986
1987         /*
1988          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1989          * id: i660
1990          *
1991          * Description:
1992          * In the following configuration :
1993          * - USBHOST module is set to smart-idle mode
1994          * - PRCM asserts idle_req to the USBHOST module ( This typically
1995          *   happens when the system is going to a low power mode : all ports
1996          *   have been suspended, the master part of the USBHOST module has
1997          *   entered the standby state, and SW has cut the functional clocks)
1998          * - an USBHOST interrupt occurs before the module is able to answer
1999          *   idle_ack, typically a remote wakeup IRQ.
2000          * Then the USB HOST module will enter a deadlock situation where it
2001          * is no more accessible nor functional.
2002          *
2003          * Workaround:
2004          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2005          */
2006
2007         /*
2008          * Errata: USB host EHCI may stall when entering smart-standby mode
2009          * Id: i571
2010          *
2011          * Description:
2012          * When the USBHOST module is set to smart-standby mode, and when it is
2013          * ready to enter the standby state (i.e. all ports are suspended and
2014          * all attached devices are in suspend mode), then it can wrongly assert
2015          * the Mstandby signal too early while there are still some residual OCP
2016          * transactions ongoing. If this condition occurs, the internal state
2017          * machine may go to an undefined state and the USB link may be stuck
2018          * upon the next resume.
2019          *
2020          * Workaround:
2021          * Don't use smart standby; use only force standby,
2022          * hence HWMOD_SWSUP_MSTANDBY
2023          */
2024
2025         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2026 };
2027
2028 /*
2029  * 'usb_tll_hs' class
2030  * usb_tll_hs module is the adapter on the usb_host_hs ports
2031  */
2032 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2033         .rev_offs       = 0x0000,
2034         .sysc_offs      = 0x0010,
2035         .syss_offs      = 0x0014,
2036         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2037                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2038                            SYSC_HAS_AUTOIDLE),
2039         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2040         .sysc_fields    = &omap_hwmod_sysc_type1,
2041 };
2042
2043 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2044         .name = "usb_tll_hs",
2045         .sysc = &omap3xxx_usb_tll_hs_sysc,
2046 };
2047
2048 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2049         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2050         { .irq = -1 },
2051 };
2052
2053 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2054         .name           = "usb_tll_hs",
2055         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2056         .clkdm_name     = "l3_init_clkdm",
2057         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2058         .main_clk       = "usbtll_fck",
2059         .prcm = {
2060                 .omap2 = {
2061                         .module_offs = CORE_MOD,
2062                         .prcm_reg_id = 3,
2063                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2064                         .idlest_reg_id = 3,
2065                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2066                 },
2067         },
2068 };
2069
2070 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2071         .name           = "hdq1w",
2072         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2073         .main_clk       = "hdq_fck",
2074         .prcm           = {
2075                 .omap2 = {
2076                         .module_offs = CORE_MOD,
2077                         .prcm_reg_id = 1,
2078                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2079                         .idlest_reg_id = 1,
2080                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2081                 },
2082         },
2083         .class          = &omap2_hdq1w_class,
2084 };
2085
2086 /* SAD2D */
2087 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2088         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2089         { .name = "rst_modem_sw", .rst_shift = 1 },
2090 };
2091
2092 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2093         .name                   = "sad2d",
2094 };
2095
2096 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2097         .name           = "sad2d",
2098         .rst_lines      = omap3xxx_sad2d_resets,
2099         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2100         .main_clk       = "sad2d_ick",
2101         .prcm           = {
2102                 .omap2 = {
2103                         .module_offs = CORE_MOD,
2104                         .prcm_reg_id = 1,
2105                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2106                         .idlest_reg_id = 1,
2107                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2108                 },
2109         },
2110         .class          = &omap3xxx_sad2d_class,
2111 };
2112
2113 /*
2114  * '32K sync counter' class
2115  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2116  */
2117 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2118         .rev_offs       = 0x0000,
2119         .sysc_offs      = 0x0004,
2120         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2121         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2122         .sysc_fields    = &omap_hwmod_sysc_type1,
2123 };
2124
2125 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2126         .name   = "counter",
2127         .sysc   = &omap3xxx_counter_sysc,
2128 };
2129
2130 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2131         .name           = "counter_32k",
2132         .class          = &omap3xxx_counter_hwmod_class,
2133         .clkdm_name     = "wkup_clkdm",
2134         .flags          = HWMOD_SWSUP_SIDLE,
2135         .main_clk       = "wkup_32k_fck",
2136         .prcm           = {
2137                 .omap2  = {
2138                         .module_offs = WKUP_MOD,
2139                         .prcm_reg_id = 1,
2140                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2141                         .idlest_reg_id = 1,
2142                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2143                 },
2144         },
2145 };
2146
2147 /*
2148  * 'gpmc' class
2149  * general purpose memory controller
2150  */
2151
2152 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2153         .rev_offs       = 0x0000,
2154         .sysc_offs      = 0x0010,
2155         .syss_offs      = 0x0014,
2156         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2157                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2158         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2159         .sysc_fields    = &omap_hwmod_sysc_type1,
2160 };
2161
2162 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2163         .name   = "gpmc",
2164         .sysc   = &omap3xxx_gpmc_sysc,
2165 };
2166
2167 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2168         { .irq = 20 + OMAP_INTC_START, },
2169         { .irq = -1 }
2170 };
2171
2172 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2173         .name           = "gpmc",
2174         .class          = &omap3xxx_gpmc_hwmod_class,
2175         .clkdm_name     = "core_l3_clkdm",
2176         .mpu_irqs       = omap3xxx_gpmc_irqs,
2177         .main_clk       = "gpmc_fck",
2178         /*
2179          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2180          * block.  It is not being added due to any known bugs with
2181          * resetting the GPMC IP block, but rather because any timings
2182          * set by the bootloader are not being correctly programmed by
2183          * the kernel from the board file or DT data.
2184          * HWMOD_INIT_NO_RESET should be removed ASAP.
2185          */
2186         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2187                            HWMOD_NO_IDLEST),
2188 };
2189
2190 /*
2191  * interfaces
2192  */
2193
2194 /* L3 -> L4_CORE interface */
2195 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2196         .master = &omap3xxx_l3_main_hwmod,
2197         .slave  = &omap3xxx_l4_core_hwmod,
2198         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2199 };
2200
2201 /* L3 -> L4_PER interface */
2202 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2203         .master = &omap3xxx_l3_main_hwmod,
2204         .slave  = &omap3xxx_l4_per_hwmod,
2205         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2206 };
2207
2208 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2209         {
2210                 .pa_start       = 0x68000000,
2211                 .pa_end         = 0x6800ffff,
2212                 .flags          = ADDR_TYPE_RT,
2213         },
2214         { }
2215 };
2216
2217 /* MPU -> L3 interface */
2218 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2219         .master   = &omap3xxx_mpu_hwmod,
2220         .slave    = &omap3xxx_l3_main_hwmod,
2221         .addr     = omap3xxx_l3_main_addrs,
2222         .user   = OCP_USER_MPU,
2223 };
2224
2225 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2226         {
2227                 .pa_start       = 0x54000000,
2228                 .pa_end         = 0x547fffff,
2229                 .flags          = ADDR_TYPE_RT,
2230         },
2231         { }
2232 };
2233
2234 /* l3 -> debugss */
2235 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2236         .master         = &omap3xxx_l3_main_hwmod,
2237         .slave          = &omap3xxx_debugss_hwmod,
2238         .addr           = omap3xxx_l4_emu_addrs,
2239         .user           = OCP_USER_MPU,
2240 };
2241
2242 /* DSS -> l3 */
2243 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2244         .master         = &omap3430es1_dss_core_hwmod,
2245         .slave          = &omap3xxx_l3_main_hwmod,
2246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2247 };
2248
2249 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2250         .master         = &omap3xxx_dss_core_hwmod,
2251         .slave          = &omap3xxx_l3_main_hwmod,
2252         .fw = {
2253                 .omap2 = {
2254                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2255                         .flags  = OMAP_FIREWALL_L3,
2256                 }
2257         },
2258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261 /* l3_core -> usbhsotg interface */
2262 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2263         .master         = &omap3xxx_usbhsotg_hwmod,
2264         .slave          = &omap3xxx_l3_main_hwmod,
2265         .clk            = "core_l3_ick",
2266         .user           = OCP_USER_MPU,
2267 };
2268
2269 /* l3_core -> am35xx_usbhsotg interface */
2270 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2271         .master         = &am35xx_usbhsotg_hwmod,
2272         .slave          = &omap3xxx_l3_main_hwmod,
2273         .clk            = "hsotgusb_ick",
2274         .user           = OCP_USER_MPU,
2275 };
2276
2277 /* l3_core -> sad2d interface */
2278 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2279         .master         = &omap3xxx_sad2d_hwmod,
2280         .slave          = &omap3xxx_l3_main_hwmod,
2281         .clk            = "core_l3_ick",
2282         .user           = OCP_USER_MPU,
2283 };
2284
2285 /* L4_CORE -> L4_WKUP interface */
2286 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2287         .master = &omap3xxx_l4_core_hwmod,
2288         .slave  = &omap3xxx_l4_wkup_hwmod,
2289         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2290 };
2291
2292 /* L4 CORE -> MMC1 interface */
2293 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2294         .master         = &omap3xxx_l4_core_hwmod,
2295         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2296         .clk            = "mmchs1_ick",
2297         .addr           = omap2430_mmc1_addr_space,
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299         .flags          = OMAP_FIREWALL_L4
2300 };
2301
2302 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2303         .master         = &omap3xxx_l4_core_hwmod,
2304         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2305         .clk            = "mmchs1_ick",
2306         .addr           = omap2430_mmc1_addr_space,
2307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2308         .flags          = OMAP_FIREWALL_L4
2309 };
2310
2311 /* L4 CORE -> MMC2 interface */
2312 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2313         .master         = &omap3xxx_l4_core_hwmod,
2314         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2315         .clk            = "mmchs2_ick",
2316         .addr           = omap2430_mmc2_addr_space,
2317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2318         .flags          = OMAP_FIREWALL_L4
2319 };
2320
2321 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2322         .master         = &omap3xxx_l4_core_hwmod,
2323         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2324         .clk            = "mmchs2_ick",
2325         .addr           = omap2430_mmc2_addr_space,
2326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2327         .flags          = OMAP_FIREWALL_L4
2328 };
2329
2330 /* L4 CORE -> MMC3 interface */
2331 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2332         {
2333                 .pa_start       = 0x480ad000,
2334                 .pa_end         = 0x480ad1ff,
2335                 .flags          = ADDR_TYPE_RT,
2336         },
2337         { }
2338 };
2339
2340 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2341         .master         = &omap3xxx_l4_core_hwmod,
2342         .slave          = &omap3xxx_mmc3_hwmod,
2343         .clk            = "mmchs3_ick",
2344         .addr           = omap3xxx_mmc3_addr_space,
2345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2346         .flags          = OMAP_FIREWALL_L4
2347 };
2348
2349 /* L4 CORE -> UART1 interface */
2350 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2351         {
2352                 .pa_start       = OMAP3_UART1_BASE,
2353                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2354                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2355         },
2356         { }
2357 };
2358
2359 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2360         .master         = &omap3xxx_l4_core_hwmod,
2361         .slave          = &omap3xxx_uart1_hwmod,
2362         .clk            = "uart1_ick",
2363         .addr           = omap3xxx_uart1_addr_space,
2364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2365 };
2366
2367 /* L4 CORE -> UART2 interface */
2368 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2369         {
2370                 .pa_start       = OMAP3_UART2_BASE,
2371                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2372                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2373         },
2374         { }
2375 };
2376
2377 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2378         .master         = &omap3xxx_l4_core_hwmod,
2379         .slave          = &omap3xxx_uart2_hwmod,
2380         .clk            = "uart2_ick",
2381         .addr           = omap3xxx_uart2_addr_space,
2382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2383 };
2384
2385 /* L4 PER -> UART3 interface */
2386 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2387         {
2388                 .pa_start       = OMAP3_UART3_BASE,
2389                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2390                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2391         },
2392         { }
2393 };
2394
2395 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2396         .master         = &omap3xxx_l4_per_hwmod,
2397         .slave          = &omap3xxx_uart3_hwmod,
2398         .clk            = "uart3_ick",
2399         .addr           = omap3xxx_uart3_addr_space,
2400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2401 };
2402
2403 /* L4 PER -> UART4 interface */
2404 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2405         {
2406                 .pa_start       = OMAP3_UART4_BASE,
2407                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2408                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2409         },
2410         { }
2411 };
2412
2413 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2414         .master         = &omap3xxx_l4_per_hwmod,
2415         .slave          = &omap36xx_uart4_hwmod,
2416         .clk            = "uart4_ick",
2417         .addr           = omap36xx_uart4_addr_space,
2418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2419 };
2420
2421 /* AM35xx: L4 CORE -> UART4 interface */
2422 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2423         {
2424                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2425                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2426                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2427         },
2428         { }
2429 };
2430
2431 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2432         .master         = &omap3xxx_l4_core_hwmod,
2433         .slave          = &am35xx_uart4_hwmod,
2434         .clk            = "uart4_ick",
2435         .addr           = am35xx_uart4_addr_space,
2436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2437 };
2438
2439 /* L4 CORE -> I2C1 interface */
2440 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2441         .master         = &omap3xxx_l4_core_hwmod,
2442         .slave          = &omap3xxx_i2c1_hwmod,
2443         .clk            = "i2c1_ick",
2444         .addr           = omap2_i2c1_addr_space,
2445         .fw = {
2446                 .omap2 = {
2447                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2448                         .l4_prot_group = 7,
2449                         .flags  = OMAP_FIREWALL_L4,
2450                 }
2451         },
2452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2453 };
2454
2455 /* L4 CORE -> I2C2 interface */
2456 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2457         .master         = &omap3xxx_l4_core_hwmod,
2458         .slave          = &omap3xxx_i2c2_hwmod,
2459         .clk            = "i2c2_ick",
2460         .addr           = omap2_i2c2_addr_space,
2461         .fw = {
2462                 .omap2 = {
2463                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2464                         .l4_prot_group = 7,
2465                         .flags = OMAP_FIREWALL_L4,
2466                 }
2467         },
2468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2469 };
2470
2471 /* L4 CORE -> I2C3 interface */
2472 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2473         {
2474                 .pa_start       = 0x48060000,
2475                 .pa_end         = 0x48060000 + SZ_128 - 1,
2476                 .flags          = ADDR_TYPE_RT,
2477         },
2478         { }
2479 };
2480
2481 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2482         .master         = &omap3xxx_l4_core_hwmod,
2483         .slave          = &omap3xxx_i2c3_hwmod,
2484         .clk            = "i2c3_ick",
2485         .addr           = omap3xxx_i2c3_addr_space,
2486         .fw = {
2487                 .omap2 = {
2488                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2489                         .l4_prot_group = 7,
2490                         .flags = OMAP_FIREWALL_L4,
2491                 }
2492         },
2493         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2494 };
2495
2496 /* L4 CORE -> SR1 interface */
2497 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2498         {
2499                 .pa_start       = OMAP34XX_SR1_BASE,
2500                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2501                 .flags          = ADDR_TYPE_RT,
2502         },
2503         { }
2504 };
2505
2506 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2507         .master         = &omap3xxx_l4_core_hwmod,
2508         .slave          = &omap34xx_sr1_hwmod,
2509         .clk            = "sr_l4_ick",
2510         .addr           = omap3_sr1_addr_space,
2511         .user           = OCP_USER_MPU,
2512 };
2513
2514 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2515         .master         = &omap3xxx_l4_core_hwmod,
2516         .slave          = &omap36xx_sr1_hwmod,
2517         .clk            = "sr_l4_ick",
2518         .addr           = omap3_sr1_addr_space,
2519         .user           = OCP_USER_MPU,
2520 };
2521
2522 /* L4 CORE -> SR1 interface */
2523 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2524         {
2525                 .pa_start       = OMAP34XX_SR2_BASE,
2526                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2527                 .flags          = ADDR_TYPE_RT,
2528         },
2529         { }
2530 };
2531
2532 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2533         .master         = &omap3xxx_l4_core_hwmod,
2534         .slave          = &omap34xx_sr2_hwmod,
2535         .clk            = "sr_l4_ick",
2536         .addr           = omap3_sr2_addr_space,
2537         .user           = OCP_USER_MPU,
2538 };
2539
2540 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2541         .master         = &omap3xxx_l4_core_hwmod,
2542         .slave          = &omap36xx_sr2_hwmod,
2543         .clk            = "sr_l4_ick",
2544         .addr           = omap3_sr2_addr_space,
2545         .user           = OCP_USER_MPU,
2546 };
2547
2548 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2549         {
2550                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2551                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2552                 .flags          = ADDR_TYPE_RT
2553         },
2554         { }
2555 };
2556
2557 /* l4_core -> usbhsotg  */
2558 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2559         .master         = &omap3xxx_l4_core_hwmod,
2560         .slave          = &omap3xxx_usbhsotg_hwmod,
2561         .clk            = "l4_ick",
2562         .addr           = omap3xxx_usbhsotg_addrs,
2563         .user           = OCP_USER_MPU,
2564 };
2565
2566 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2567         {
2568                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2569                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2570                 .flags          = ADDR_TYPE_RT
2571         },
2572         { }
2573 };
2574
2575 /* l4_core -> usbhsotg  */
2576 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2577         .master         = &omap3xxx_l4_core_hwmod,
2578         .slave          = &am35xx_usbhsotg_hwmod,
2579         .clk            = "hsotgusb_ick",
2580         .addr           = am35xx_usbhsotg_addrs,
2581         .user           = OCP_USER_MPU,
2582 };
2583
2584 /* L4_WKUP -> L4_SEC interface */
2585 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2586         .master = &omap3xxx_l4_wkup_hwmod,
2587         .slave  = &omap3xxx_l4_sec_hwmod,
2588         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 /* IVA2 <- L3 interface */
2592 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2593         .master         = &omap3xxx_l3_main_hwmod,
2594         .slave          = &omap3xxx_iva_hwmod,
2595         .clk            = "core_l3_ick",
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2600         {
2601                 .pa_start       = 0x48318000,
2602                 .pa_end         = 0x48318000 + SZ_1K - 1,
2603                 .flags          = ADDR_TYPE_RT
2604         },
2605         { }
2606 };
2607
2608 /* l4_wkup -> timer1 */
2609 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2610         .master         = &omap3xxx_l4_wkup_hwmod,
2611         .slave          = &omap3xxx_timer1_hwmod,
2612         .clk            = "gpt1_ick",
2613         .addr           = omap3xxx_timer1_addrs,
2614         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2615 };
2616
2617 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2618         {
2619                 .pa_start       = 0x49032000,
2620                 .pa_end         = 0x49032000 + SZ_1K - 1,
2621                 .flags          = ADDR_TYPE_RT
2622         },
2623         { }
2624 };
2625
2626 /* l4_per -> timer2 */
2627 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2628         .master         = &omap3xxx_l4_per_hwmod,
2629         .slave          = &omap3xxx_timer2_hwmod,
2630         .clk            = "gpt2_ick",
2631         .addr           = omap3xxx_timer2_addrs,
2632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2633 };
2634
2635 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2636         {
2637                 .pa_start       = 0x49034000,
2638                 .pa_end         = 0x49034000 + SZ_1K - 1,
2639                 .flags          = ADDR_TYPE_RT
2640         },
2641         { }
2642 };
2643
2644 /* l4_per -> timer3 */
2645 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2646         .master         = &omap3xxx_l4_per_hwmod,
2647         .slave          = &omap3xxx_timer3_hwmod,
2648         .clk            = "gpt3_ick",
2649         .addr           = omap3xxx_timer3_addrs,
2650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2651 };
2652
2653 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2654         {
2655                 .pa_start       = 0x49036000,
2656                 .pa_end         = 0x49036000 + SZ_1K - 1,
2657                 .flags          = ADDR_TYPE_RT
2658         },
2659         { }
2660 };
2661
2662 /* l4_per -> timer4 */
2663 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2664         .master         = &omap3xxx_l4_per_hwmod,
2665         .slave          = &omap3xxx_timer4_hwmod,
2666         .clk            = "gpt4_ick",
2667         .addr           = omap3xxx_timer4_addrs,
2668         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2669 };
2670
2671 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2672         {
2673                 .pa_start       = 0x49038000,
2674                 .pa_end         = 0x49038000 + SZ_1K - 1,
2675                 .flags          = ADDR_TYPE_RT
2676         },
2677         { }
2678 };
2679
2680 /* l4_per -> timer5 */
2681 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2682         .master         = &omap3xxx_l4_per_hwmod,
2683         .slave          = &omap3xxx_timer5_hwmod,
2684         .clk            = "gpt5_ick",
2685         .addr           = omap3xxx_timer5_addrs,
2686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2687 };
2688
2689 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2690         {
2691                 .pa_start       = 0x4903A000,
2692                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2693                 .flags          = ADDR_TYPE_RT
2694         },
2695         { }
2696 };
2697
2698 /* l4_per -> timer6 */
2699 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2700         .master         = &omap3xxx_l4_per_hwmod,
2701         .slave          = &omap3xxx_timer6_hwmod,
2702         .clk            = "gpt6_ick",
2703         .addr           = omap3xxx_timer6_addrs,
2704         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2705 };
2706
2707 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2708         {
2709                 .pa_start       = 0x4903C000,
2710                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2711                 .flags          = ADDR_TYPE_RT
2712         },
2713         { }
2714 };
2715
2716 /* l4_per -> timer7 */
2717 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2718         .master         = &omap3xxx_l4_per_hwmod,
2719         .slave          = &omap3xxx_timer7_hwmod,
2720         .clk            = "gpt7_ick",
2721         .addr           = omap3xxx_timer7_addrs,
2722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2723 };
2724
2725 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2726         {
2727                 .pa_start       = 0x4903E000,
2728                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2729                 .flags          = ADDR_TYPE_RT
2730         },
2731         { }
2732 };
2733
2734 /* l4_per -> timer8 */
2735 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2736         .master         = &omap3xxx_l4_per_hwmod,
2737         .slave          = &omap3xxx_timer8_hwmod,
2738         .clk            = "gpt8_ick",
2739         .addr           = omap3xxx_timer8_addrs,
2740         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2741 };
2742
2743 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2744         {
2745                 .pa_start       = 0x49040000,
2746                 .pa_end         = 0x49040000 + SZ_1K - 1,
2747                 .flags          = ADDR_TYPE_RT
2748         },
2749         { }
2750 };
2751
2752 /* l4_per -> timer9 */
2753 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2754         .master         = &omap3xxx_l4_per_hwmod,
2755         .slave          = &omap3xxx_timer9_hwmod,
2756         .clk            = "gpt9_ick",
2757         .addr           = omap3xxx_timer9_addrs,
2758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2759 };
2760
2761 /* l4_core -> timer10 */
2762 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2763         .master         = &omap3xxx_l4_core_hwmod,
2764         .slave          = &omap3xxx_timer10_hwmod,
2765         .clk            = "gpt10_ick",
2766         .addr           = omap2_timer10_addrs,
2767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2768 };
2769
2770 /* l4_core -> timer11 */
2771 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2772         .master         = &omap3xxx_l4_core_hwmod,
2773         .slave          = &omap3xxx_timer11_hwmod,
2774         .clk            = "gpt11_ick",
2775         .addr           = omap2_timer11_addrs,
2776         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2777 };
2778
2779 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2780         {
2781                 .pa_start       = 0x48304000,
2782                 .pa_end         = 0x48304000 + SZ_1K - 1,
2783                 .flags          = ADDR_TYPE_RT
2784         },
2785         { }
2786 };
2787
2788 /* l4_core -> timer12 */
2789 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2790         .master         = &omap3xxx_l4_sec_hwmod,
2791         .slave          = &omap3xxx_timer12_hwmod,
2792         .clk            = "gpt12_ick",
2793         .addr           = omap3xxx_timer12_addrs,
2794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2795 };
2796
2797 /* l4_wkup -> wd_timer2 */
2798 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2799         {
2800                 .pa_start       = 0x48314000,
2801                 .pa_end         = 0x4831407f,
2802                 .flags          = ADDR_TYPE_RT
2803         },
2804         { }
2805 };
2806
2807 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2808         .master         = &omap3xxx_l4_wkup_hwmod,
2809         .slave          = &omap3xxx_wd_timer2_hwmod,
2810         .clk            = "wdt2_ick",
2811         .addr           = omap3xxx_wd_timer2_addrs,
2812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2813 };
2814
2815 /* l4_core -> dss */
2816 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2817         .master         = &omap3xxx_l4_core_hwmod,
2818         .slave          = &omap3430es1_dss_core_hwmod,
2819         .clk            = "dss_ick",
2820         .addr           = omap2_dss_addrs,
2821         .fw = {
2822                 .omap2 = {
2823                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2824                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2825                         .flags  = OMAP_FIREWALL_L4,
2826                 }
2827         },
2828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2829 };
2830
2831 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2832         .master         = &omap3xxx_l4_core_hwmod,
2833         .slave          = &omap3xxx_dss_core_hwmod,
2834         .clk            = "dss_ick",
2835         .addr           = omap2_dss_addrs,
2836         .fw = {
2837                 .omap2 = {
2838                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2839                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2840                         .flags  = OMAP_FIREWALL_L4,
2841                 }
2842         },
2843         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2844 };
2845
2846 /* l4_core -> dss_dispc */
2847 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2848         .master         = &omap3xxx_l4_core_hwmod,
2849         .slave          = &omap3xxx_dss_dispc_hwmod,
2850         .clk            = "dss_ick",
2851         .addr           = omap2_dss_dispc_addrs,
2852         .fw = {
2853                 .omap2 = {
2854                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2855                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2856                         .flags  = OMAP_FIREWALL_L4,
2857                 }
2858         },
2859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2860 };
2861
2862 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2863         {
2864                 .pa_start       = 0x4804FC00,
2865                 .pa_end         = 0x4804FFFF,
2866                 .flags          = ADDR_TYPE_RT
2867         },
2868         { }
2869 };
2870
2871 /* l4_core -> dss_dsi1 */
2872 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2873         .master         = &omap3xxx_l4_core_hwmod,
2874         .slave          = &omap3xxx_dss_dsi1_hwmod,
2875         .clk            = "dss_ick",
2876         .addr           = omap3xxx_dss_dsi1_addrs,
2877         .fw = {
2878                 .omap2 = {
2879                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2880                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2881                         .flags  = OMAP_FIREWALL_L4,
2882                 }
2883         },
2884         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2885 };
2886
2887 /* l4_core -> dss_rfbi */
2888 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2889         .master         = &omap3xxx_l4_core_hwmod,
2890         .slave          = &omap3xxx_dss_rfbi_hwmod,
2891         .clk            = "dss_ick",
2892         .addr           = omap2_dss_rfbi_addrs,
2893         .fw = {
2894                 .omap2 = {
2895                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2896                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2897                         .flags  = OMAP_FIREWALL_L4,
2898                 }
2899         },
2900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* l4_core -> dss_venc */
2904 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2905         .master         = &omap3xxx_l4_core_hwmod,
2906         .slave          = &omap3xxx_dss_venc_hwmod,
2907         .clk            = "dss_ick",
2908         .addr           = omap2_dss_venc_addrs,
2909         .fw = {
2910                 .omap2 = {
2911                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2912                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2913                         .flags  = OMAP_FIREWALL_L4,
2914                 }
2915         },
2916         .flags          = OCPIF_SWSUP_IDLE,
2917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2918 };
2919
2920 /* l4_wkup -> gpio1 */
2921 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2922         {
2923                 .pa_start       = 0x48310000,
2924                 .pa_end         = 0x483101ff,
2925                 .flags          = ADDR_TYPE_RT
2926         },
2927         { }
2928 };
2929
2930 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2931         .master         = &omap3xxx_l4_wkup_hwmod,
2932         .slave          = &omap3xxx_gpio1_hwmod,
2933         .addr           = omap3xxx_gpio1_addrs,
2934         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2935 };
2936
2937 /* l4_per -> gpio2 */
2938 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2939         {
2940                 .pa_start       = 0x49050000,
2941                 .pa_end         = 0x490501ff,
2942                 .flags          = ADDR_TYPE_RT
2943         },
2944         { }
2945 };
2946
2947 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2948         .master         = &omap3xxx_l4_per_hwmod,
2949         .slave          = &omap3xxx_gpio2_hwmod,
2950         .addr           = omap3xxx_gpio2_addrs,
2951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2952 };
2953
2954 /* l4_per -> gpio3 */
2955 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2956         {
2957                 .pa_start       = 0x49052000,
2958                 .pa_end         = 0x490521ff,
2959                 .flags          = ADDR_TYPE_RT
2960         },
2961         { }
2962 };
2963
2964 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2965         .master         = &omap3xxx_l4_per_hwmod,
2966         .slave          = &omap3xxx_gpio3_hwmod,
2967         .addr           = omap3xxx_gpio3_addrs,
2968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2969 };
2970
2971 /*
2972  * 'mmu' class
2973  * The memory management unit performs virtual to physical address translation
2974  * for its requestors.
2975  */
2976
2977 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2978         .rev_offs       = 0x000,
2979         .sysc_offs      = 0x010,
2980         .syss_offs      = 0x014,
2981         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2982                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2983         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2984         .sysc_fields    = &omap_hwmod_sysc_type1,
2985 };
2986
2987 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2988         .name = "mmu",
2989         .sysc = &mmu_sysc,
2990 };
2991
2992 /* mmu isp */
2993
2994 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2995         .da_start       = 0x0,
2996         .da_end         = 0xfffff000,
2997         .nr_tlb_entries = 8,
2998 };
2999
3000 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
3001 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
3002         { .irq = 24 + OMAP_INTC_START, },
3003         { .irq = -1 }
3004 };
3005
3006 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
3007         {
3008                 .pa_start       = 0x480bd400,
3009                 .pa_end         = 0x480bd47f,
3010                 .flags          = ADDR_TYPE_RT,
3011         },
3012         { }
3013 };
3014
3015 /* l4_core -> mmu isp */
3016 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3017         .master         = &omap3xxx_l4_core_hwmod,
3018         .slave          = &omap3xxx_mmu_isp_hwmod,
3019         .addr           = omap3xxx_mmu_isp_addrs,
3020         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3021 };
3022
3023 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3024         .name           = "mmu_isp",
3025         .class          = &omap3xxx_mmu_hwmod_class,
3026         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
3027         .main_clk       = "cam_ick",
3028         .dev_attr       = &mmu_isp_dev_attr,
3029         .flags          = HWMOD_NO_IDLEST,
3030 };
3031
3032 #ifdef CONFIG_OMAP_IOMMU_IVA2
3033
3034 /* mmu iva */
3035
3036 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3037         .da_start       = 0x11000000,
3038         .da_end         = 0xfffff000,
3039         .nr_tlb_entries = 32,
3040 };
3041
3042 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3043 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3044         { .irq = 28 + OMAP_INTC_START, },
3045         { .irq = -1 }
3046 };
3047
3048 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3049         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3050 };
3051
3052 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3053         {
3054                 .pa_start       = 0x5d000000,
3055                 .pa_end         = 0x5d00007f,
3056                 .flags          = ADDR_TYPE_RT,
3057         },
3058         { }
3059 };
3060
3061 /* l3_main -> iva mmu */
3062 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3063         .master         = &omap3xxx_l3_main_hwmod,
3064         .slave          = &omap3xxx_mmu_iva_hwmod,
3065         .addr           = omap3xxx_mmu_iva_addrs,
3066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3067 };
3068
3069 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3070         .name           = "mmu_iva",
3071         .class          = &omap3xxx_mmu_hwmod_class,
3072         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3073         .rst_lines      = omap3xxx_mmu_iva_resets,
3074         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3075         .main_clk       = "iva2_ck",
3076         .prcm = {
3077                 .omap2 = {
3078                         .module_offs = OMAP3430_IVA2_MOD,
3079                 },
3080         },
3081         .dev_attr       = &mmu_iva_dev_attr,
3082         .flags          = HWMOD_NO_IDLEST,
3083 };
3084
3085 #endif
3086
3087 /* l4_per -> gpio4 */
3088 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3089         {
3090                 .pa_start       = 0x49054000,
3091                 .pa_end         = 0x490541ff,
3092                 .flags          = ADDR_TYPE_RT
3093         },
3094         { }
3095 };
3096
3097 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3098         .master         = &omap3xxx_l4_per_hwmod,
3099         .slave          = &omap3xxx_gpio4_hwmod,
3100         .addr           = omap3xxx_gpio4_addrs,
3101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3102 };
3103
3104 /* l4_per -> gpio5 */
3105 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3106         {
3107                 .pa_start       = 0x49056000,
3108                 .pa_end         = 0x490561ff,
3109                 .flags          = ADDR_TYPE_RT
3110         },
3111         { }
3112 };
3113
3114 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3115         .master         = &omap3xxx_l4_per_hwmod,
3116         .slave          = &omap3xxx_gpio5_hwmod,
3117         .addr           = omap3xxx_gpio5_addrs,
3118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3119 };
3120
3121 /* l4_per -> gpio6 */
3122 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3123         {
3124                 .pa_start       = 0x49058000,
3125                 .pa_end         = 0x490581ff,
3126                 .flags          = ADDR_TYPE_RT
3127         },
3128         { }
3129 };
3130
3131 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3132         .master         = &omap3xxx_l4_per_hwmod,
3133         .slave          = &omap3xxx_gpio6_hwmod,
3134         .addr           = omap3xxx_gpio6_addrs,
3135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 /* dma_system -> L3 */
3139 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3140         .master         = &omap3xxx_dma_system_hwmod,
3141         .slave          = &omap3xxx_l3_main_hwmod,
3142         .clk            = "core_l3_ick",
3143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3144 };
3145
3146 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3147         {
3148                 .pa_start       = 0x48056000,
3149                 .pa_end         = 0x48056fff,
3150                 .flags          = ADDR_TYPE_RT
3151         },
3152         { }
3153 };
3154
3155 /* l4_cfg -> dma_system */
3156 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3157         .master         = &omap3xxx_l4_core_hwmod,
3158         .slave          = &omap3xxx_dma_system_hwmod,
3159         .clk            = "core_l4_ick",
3160         .addr           = omap3xxx_dma_system_addrs,
3161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3162 };
3163
3164 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3165         {
3166                 .name           = "mpu",
3167                 .pa_start       = 0x48074000,
3168                 .pa_end         = 0x480740ff,
3169                 .flags          = ADDR_TYPE_RT
3170         },
3171         { }
3172 };
3173
3174 /* l4_core -> mcbsp1 */
3175 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3176         .master         = &omap3xxx_l4_core_hwmod,
3177         .slave          = &omap3xxx_mcbsp1_hwmod,
3178         .clk            = "mcbsp1_ick",
3179         .addr           = omap3xxx_mcbsp1_addrs,
3180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3181 };
3182
3183 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3184         {
3185                 .name           = "mpu",
3186                 .pa_start       = 0x49022000,
3187                 .pa_end         = 0x490220ff,
3188                 .flags          = ADDR_TYPE_RT
3189         },
3190         { }
3191 };
3192
3193 /* l4_per -> mcbsp2 */
3194 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3195         .master         = &omap3xxx_l4_per_hwmod,
3196         .slave          = &omap3xxx_mcbsp2_hwmod,
3197         .clk            = "mcbsp2_ick",
3198         .addr           = omap3xxx_mcbsp2_addrs,
3199         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3200 };
3201
3202 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3203         {
3204                 .name           = "mpu",
3205                 .pa_start       = 0x49024000,
3206                 .pa_end         = 0x490240ff,
3207                 .flags          = ADDR_TYPE_RT
3208         },
3209         { }
3210 };
3211
3212 /* l4_per -> mcbsp3 */
3213 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3214         .master         = &omap3xxx_l4_per_hwmod,
3215         .slave          = &omap3xxx_mcbsp3_hwmod,
3216         .clk            = "mcbsp3_ick",
3217         .addr           = omap3xxx_mcbsp3_addrs,
3218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3219 };
3220
3221 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3222         {
3223                 .name           = "mpu",
3224                 .pa_start       = 0x49026000,
3225                 .pa_end         = 0x490260ff,
3226                 .flags          = ADDR_TYPE_RT
3227         },
3228         { }
3229 };
3230
3231 /* l4_per -> mcbsp4 */
3232 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3233         .master         = &omap3xxx_l4_per_hwmod,
3234         .slave          = &omap3xxx_mcbsp4_hwmod,
3235         .clk            = "mcbsp4_ick",
3236         .addr           = omap3xxx_mcbsp4_addrs,
3237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3238 };
3239
3240 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3241         {
3242                 .name           = "mpu",
3243                 .pa_start       = 0x48096000,
3244                 .pa_end         = 0x480960ff,
3245                 .flags          = ADDR_TYPE_RT
3246         },
3247         { }
3248 };
3249
3250 /* l4_core -> mcbsp5 */
3251 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3252         .master         = &omap3xxx_l4_core_hwmod,
3253         .slave          = &omap3xxx_mcbsp5_hwmod,
3254         .clk            = "mcbsp5_ick",
3255         .addr           = omap3xxx_mcbsp5_addrs,
3256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3258
3259 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3260         {
3261                 .name           = "sidetone",
3262                 .pa_start       = 0x49028000,
3263                 .pa_end         = 0x490280ff,
3264                 .flags          = ADDR_TYPE_RT
3265         },
3266         { }
3267 };
3268
3269 /* l4_per -> mcbsp2_sidetone */
3270 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3271         .master         = &omap3xxx_l4_per_hwmod,
3272         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3273         .clk            = "mcbsp2_ick",
3274         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3275         .user           = OCP_USER_MPU,
3276 };
3277
3278 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3279         {
3280                 .name           = "sidetone",
3281                 .pa_start       = 0x4902A000,
3282                 .pa_end         = 0x4902A0ff,
3283                 .flags          = ADDR_TYPE_RT
3284         },
3285         { }
3286 };
3287
3288 /* l4_per -> mcbsp3_sidetone */
3289 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3290         .master         = &omap3xxx_l4_per_hwmod,
3291         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3292         .clk            = "mcbsp3_ick",
3293         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3294         .user           = OCP_USER_MPU,
3295 };
3296
3297 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3298         {
3299                 .pa_start       = 0x48094000,
3300                 .pa_end         = 0x480941ff,
3301                 .flags          = ADDR_TYPE_RT,
3302         },
3303         { }
3304 };
3305
3306 /* l4_core -> mailbox */
3307 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3308         .master         = &omap3xxx_l4_core_hwmod,
3309         .slave          = &omap3xxx_mailbox_hwmod,
3310         .addr           = omap3xxx_mailbox_addrs,
3311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* l4 core -> mcspi1 interface */
3315 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3316         .master         = &omap3xxx_l4_core_hwmod,
3317         .slave          = &omap34xx_mcspi1,
3318         .clk            = "mcspi1_ick",
3319         .addr           = omap2_mcspi1_addr_space,
3320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3321 };
3322
3323 /* l4 core -> mcspi2 interface */
3324 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3325         .master         = &omap3xxx_l4_core_hwmod,
3326         .slave          = &omap34xx_mcspi2,
3327         .clk            = "mcspi2_ick",
3328         .addr           = omap2_mcspi2_addr_space,
3329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3330 };
3331
3332 /* l4 core -> mcspi3 interface */
3333 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3334         .master         = &omap3xxx_l4_core_hwmod,
3335         .slave          = &omap34xx_mcspi3,
3336         .clk            = "mcspi3_ick",
3337         .addr           = omap2430_mcspi3_addr_space,
3338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3339 };
3340
3341 /* l4 core -> mcspi4 interface */
3342 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3343         {
3344                 .pa_start       = 0x480ba000,
3345                 .pa_end         = 0x480ba0ff,
3346                 .flags          = ADDR_TYPE_RT,
3347         },
3348         { }
3349 };
3350
3351 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3352         .master         = &omap3xxx_l4_core_hwmod,
3353         .slave          = &omap34xx_mcspi4,
3354         .clk            = "mcspi4_ick",
3355         .addr           = omap34xx_mcspi4_addr_space,
3356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3357 };
3358
3359 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3360         .master         = &omap3xxx_usb_host_hs_hwmod,
3361         .slave          = &omap3xxx_l3_main_hwmod,
3362         .clk            = "core_l3_ick",
3363         .user           = OCP_USER_MPU,
3364 };
3365
3366 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3367         {
3368                 .name           = "uhh",
3369                 .pa_start       = 0x48064000,
3370                 .pa_end         = 0x480643ff,
3371                 .flags          = ADDR_TYPE_RT
3372         },
3373         {
3374                 .name           = "ohci",
3375                 .pa_start       = 0x48064400,
3376                 .pa_end         = 0x480647ff,
3377         },
3378         {
3379                 .name           = "ehci",
3380                 .pa_start       = 0x48064800,
3381                 .pa_end         = 0x48064cff,
3382         },
3383         {}
3384 };
3385
3386 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3387         .master         = &omap3xxx_l4_core_hwmod,
3388         .slave          = &omap3xxx_usb_host_hs_hwmod,
3389         .clk            = "usbhost_ick",
3390         .addr           = omap3xxx_usb_host_hs_addrs,
3391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3393
3394 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3395         {
3396                 .name           = "tll",
3397                 .pa_start       = 0x48062000,
3398                 .pa_end         = 0x48062fff,
3399                 .flags          = ADDR_TYPE_RT
3400         },
3401         {}
3402 };
3403
3404 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3405         .master         = &omap3xxx_l4_core_hwmod,
3406         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3407         .clk            = "usbtll_ick",
3408         .addr           = omap3xxx_usb_tll_hs_addrs,
3409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3410 };
3411
3412 /* l4_core -> hdq1w interface */
3413 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3414         .master         = &omap3xxx_l4_core_hwmod,
3415         .slave          = &omap3xxx_hdq1w_hwmod,
3416         .clk            = "hdq_ick",
3417         .addr           = omap2_hdq1w_addr_space,
3418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3419         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3420 };
3421
3422 /* l4_wkup -> 32ksync_counter */
3423 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3424         {
3425                 .pa_start       = 0x48320000,
3426                 .pa_end         = 0x4832001f,
3427                 .flags          = ADDR_TYPE_RT
3428         },
3429         { }
3430 };
3431
3432 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3433         {
3434                 .pa_start       = 0x6e000000,
3435                 .pa_end         = 0x6e000fff,
3436                 .flags          = ADDR_TYPE_RT
3437         },
3438         { }
3439 };
3440
3441 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3442         .master         = &omap3xxx_l4_wkup_hwmod,
3443         .slave          = &omap3xxx_counter_32k_hwmod,
3444         .clk            = "omap_32ksync_ick",
3445         .addr           = omap3xxx_counter_32k_addrs,
3446         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3447 };
3448
3449 /* am35xx has Davinci MDIO & EMAC */
3450 static struct omap_hwmod_class am35xx_mdio_class = {
3451         .name = "davinci_mdio",
3452 };
3453
3454 static struct omap_hwmod am35xx_mdio_hwmod = {
3455         .name           = "davinci_mdio",
3456         .class          = &am35xx_mdio_class,
3457         .flags          = HWMOD_NO_IDLEST,
3458 };
3459
3460 /*
3461  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3462  * but this will probably require some additional hwmod core support,
3463  * so is left as a future to-do item.
3464  */
3465 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3466         .master         = &am35xx_mdio_hwmod,
3467         .slave          = &omap3xxx_l3_main_hwmod,
3468         .clk            = "emac_fck",
3469         .user           = OCP_USER_MPU,
3470 };
3471
3472 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3473         {
3474                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3475                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3476                 .flags          = ADDR_TYPE_RT,
3477         },
3478         { }
3479 };
3480
3481 /* l4_core -> davinci mdio  */
3482 /*
3483  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3484  * but this will probably require some additional hwmod core support,
3485  * so is left as a future to-do item.
3486  */
3487 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3488         .master         = &omap3xxx_l4_core_hwmod,
3489         .slave          = &am35xx_mdio_hwmod,
3490         .clk            = "emac_fck",
3491         .addr           = am35xx_mdio_addrs,
3492         .user           = OCP_USER_MPU,
3493 };
3494
3495 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3496         { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
3497         { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
3498         { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
3499         { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3500         { .irq = -1 },
3501 };
3502
3503 static struct omap_hwmod_class am35xx_emac_class = {
3504         .name = "davinci_emac",
3505 };
3506
3507 static struct omap_hwmod am35xx_emac_hwmod = {
3508         .name           = "davinci_emac",
3509         .mpu_irqs       = am35xx_emac_mpu_irqs,
3510         .class          = &am35xx_emac_class,
3511         /*
3512          * According to Mark Greer, the MPU will not return from WFI
3513          * when the EMAC signals an interrupt.
3514          * http://www.spinics.net/lists/arm-kernel/msg174734.html
3515          */
3516         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3517 };
3518
3519 /* l3_core -> davinci emac interface */
3520 /*
3521  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3522  * but this will probably require some additional hwmod core support,
3523  * so is left as a future to-do item.
3524  */
3525 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3526         .master         = &am35xx_emac_hwmod,
3527         .slave          = &omap3xxx_l3_main_hwmod,
3528         .clk            = "emac_ick",
3529         .user           = OCP_USER_MPU,
3530 };
3531
3532 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3533         {
3534                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3535                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3536                 .flags          = ADDR_TYPE_RT,
3537         },
3538         { }
3539 };
3540
3541 /* l4_core -> davinci emac  */
3542 /*
3543  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3544  * but this will probably require some additional hwmod core support,
3545  * so is left as a future to-do item.
3546  */
3547 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3548         .master         = &omap3xxx_l4_core_hwmod,
3549         .slave          = &am35xx_emac_hwmod,
3550         .clk            = "emac_ick",
3551         .addr           = am35xx_emac_addrs,
3552         .user           = OCP_USER_MPU,
3553 };
3554
3555 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3556         .master         = &omap3xxx_l3_main_hwmod,
3557         .slave          = &omap3xxx_gpmc_hwmod,
3558         .clk            = "core_l3_ick",
3559         .addr           = omap3xxx_gpmc_addrs,
3560         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3561 };
3562
3563 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
3564 static struct omap_hwmod_sysc_fields omap3_sham_sysc_fields = {
3565         .sidle_shift    = 4,
3566         .srst_shift     = 1,
3567         .autoidle_shift = 0,
3568 };
3569
3570 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
3571         .rev_offs       = 0x5c,
3572         .sysc_offs      = 0x60,
3573         .syss_offs      = 0x64,
3574         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3575                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3576         .sysc_fields    = &omap3_sham_sysc_fields,
3577 };
3578
3579 static struct omap_hwmod_class omap3xxx_sham_class = {
3580         .name   = "sham",
3581         .sysc   = &omap3_sham_sysc,
3582 };
3583
3584 static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
3585         { .irq = 49 + OMAP_INTC_START, },
3586         { .irq = -1 }
3587 };
3588
3589 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
3590         { .name = "rx", .dma_req = 69, },
3591         { .dma_req = -1 }
3592 };
3593
3594 static struct omap_hwmod omap3xxx_sham_hwmod = {
3595         .name           = "sham",
3596         .mpu_irqs       = omap3_sham_mpu_irqs,
3597         .sdma_reqs      = omap3_sham_sdma_reqs,
3598         .main_clk       = "sha12_ick",
3599         .prcm           = {
3600                 .omap2 = {
3601                         .module_offs = CORE_MOD,
3602                         .prcm_reg_id = 1,
3603                         .module_bit = OMAP3430_EN_SHA12_SHIFT,
3604                         .idlest_reg_id = 1,
3605                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
3606                 },
3607         },
3608         .class          = &omap3xxx_sham_class,
3609 };
3610
3611 static struct omap_hwmod_addr_space omap3xxx_sham_addrs[] = {
3612         {
3613                 .pa_start       = 0x480c3000,
3614                 .pa_end         = 0x480c3000 + 0x64 - 1,
3615                 .flags          = ADDR_TYPE_RT
3616         },
3617         { }
3618 };
3619
3620 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
3621         .master         = &omap3xxx_l4_core_hwmod,
3622         .slave          = &omap3xxx_sham_hwmod,
3623         .clk            = "sha12_ick",
3624         .addr           = omap3xxx_sham_addrs,
3625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3626 };
3627
3628 /* l4_core -> AES */
3629 static struct omap_hwmod_sysc_fields omap3xxx_aes_sysc_fields = {
3630         .sidle_shift    = 6,
3631         .srst_shift     = 1,
3632         .autoidle_shift = 0,
3633 };
3634
3635 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
3636         .rev_offs       = 0x44,
3637         .sysc_offs      = 0x48,
3638         .syss_offs      = 0x4c,
3639         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3640                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3641         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3642         .sysc_fields    = &omap3xxx_aes_sysc_fields,
3643 };
3644
3645 static struct omap_hwmod_class omap3xxx_aes_class = {
3646         .name   = "aes",
3647         .sysc   = &omap3_aes_sysc,
3648 };
3649
3650 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
3651         { .name = "tx", .dma_req = 65, },
3652         { .name = "rx", .dma_req = 66, },
3653         { .dma_req = -1 }
3654 };
3655
3656 static struct omap_hwmod omap3xxx_aes_hwmod = {
3657         .name           = "aes",
3658         .sdma_reqs      = omap3_aes_sdma_reqs,
3659         .main_clk       = "aes2_ick",
3660         .prcm           = {
3661                 .omap2 = {
3662                         .module_offs = CORE_MOD,
3663                         .prcm_reg_id = 1,
3664                         .module_bit = OMAP3430_EN_AES2_SHIFT,
3665                         .idlest_reg_id = 1,
3666                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
3667                 },
3668         },
3669         .class          = &omap3xxx_aes_class,
3670 };
3671
3672 static struct omap_hwmod_addr_space omap3xxx_aes_addrs[] = {
3673         {
3674                 .pa_start       = 0x480c5000,
3675                 .pa_end         = 0x480c5000 + 0x50 - 1,
3676                 .flags          = ADDR_TYPE_RT
3677         },
3678         { }
3679 };
3680
3681 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
3682         .master         = &omap3xxx_l4_core_hwmod,
3683         .slave          = &omap3xxx_aes_hwmod,
3684         .clk            = "aes2_ick",
3685         .addr           = omap3xxx_aes_addrs,
3686         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3687 };
3688
3689 /*
3690  * 'ssi' class
3691  * synchronous serial interface (multichannel and full-duplex serial if)
3692  */
3693
3694 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
3695         .rev_offs       = 0x0000,
3696         .sysc_offs      = 0x0010,
3697         .syss_offs      = 0x0014,
3698         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
3699                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3700                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3701         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3702                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3703                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3704         .sysc_fields    = &omap_hwmod_sysc_type1,
3705 };
3706
3707 static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
3708         .name   = "ssi",
3709         .sysc   = &omap34xx_ssi_sysc,
3710 };
3711
3712 static struct omap_hwmod omap34xx_ssi_hwmod = {
3713         .name           = "ssi",
3714         .class          = &omap34xx_ssi_hwmod_class,
3715         .clkdm_name     = "core_l4_clkdm",
3716         .main_clk       = "ssi_ssr_fck",
3717         .prcm           = {
3718                 .omap2 = {
3719                         .prcm_reg_id            = 1,
3720                         .module_bit             = OMAP3430_EN_SSI_SHIFT,
3721                         .module_offs            = CORE_MOD,
3722                         .idlest_reg_id          = 1,
3723                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
3724                 },
3725         },
3726 };
3727
3728 /* L4 CORE -> SSI */
3729 static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
3730         .master         = &omap3xxx_l4_core_hwmod,
3731         .slave          = &omap34xx_ssi_hwmod,
3732         .clk            = "ssi_ick",
3733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3734 };
3735
3736 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3737         &omap3xxx_l3_main__l4_core,
3738         &omap3xxx_l3_main__l4_per,
3739         &omap3xxx_mpu__l3_main,
3740         &omap3xxx_l3_main__l4_debugss,
3741         &omap3xxx_l4_core__l4_wkup,
3742         &omap3xxx_l4_core__mmc3,
3743         &omap3_l4_core__uart1,
3744         &omap3_l4_core__uart2,
3745         &omap3_l4_per__uart3,
3746         &omap3_l4_core__i2c1,
3747         &omap3_l4_core__i2c2,
3748         &omap3_l4_core__i2c3,
3749         &omap3xxx_l4_wkup__l4_sec,
3750         &omap3xxx_l4_wkup__timer1,
3751         &omap3xxx_l4_per__timer2,
3752         &omap3xxx_l4_per__timer3,
3753         &omap3xxx_l4_per__timer4,
3754         &omap3xxx_l4_per__timer5,
3755         &omap3xxx_l4_per__timer6,
3756         &omap3xxx_l4_per__timer7,
3757         &omap3xxx_l4_per__timer8,
3758         &omap3xxx_l4_per__timer9,
3759         &omap3xxx_l4_core__timer10,
3760         &omap3xxx_l4_core__timer11,
3761         &omap3xxx_l4_wkup__wd_timer2,
3762         &omap3xxx_l4_wkup__gpio1,
3763         &omap3xxx_l4_per__gpio2,
3764         &omap3xxx_l4_per__gpio3,
3765         &omap3xxx_l4_per__gpio4,
3766         &omap3xxx_l4_per__gpio5,
3767         &omap3xxx_l4_per__gpio6,
3768         &omap3xxx_dma_system__l3,
3769         &omap3xxx_l4_core__dma_system,
3770         &omap3xxx_l4_core__mcbsp1,
3771         &omap3xxx_l4_per__mcbsp2,
3772         &omap3xxx_l4_per__mcbsp3,
3773         &omap3xxx_l4_per__mcbsp4,
3774         &omap3xxx_l4_core__mcbsp5,
3775         &omap3xxx_l4_per__mcbsp2_sidetone,
3776         &omap3xxx_l4_per__mcbsp3_sidetone,
3777         &omap34xx_l4_core__mcspi1,
3778         &omap34xx_l4_core__mcspi2,
3779         &omap34xx_l4_core__mcspi3,
3780         &omap34xx_l4_core__mcspi4,
3781         &omap3xxx_l4_wkup__counter_32k,
3782         &omap3xxx_l3_main__gpmc,
3783         NULL,
3784 };
3785
3786 /* GP-only hwmod links */
3787 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
3788         &omap3xxx_l4_sec__timer12,
3789         &omap3xxx_l4_core__sham,
3790         &omap3xxx_l4_core__aes,
3791         NULL
3792 };
3793
3794 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
3795         &omap3xxx_l4_sec__timer12,
3796         &omap3xxx_l4_core__sham,
3797         &omap3xxx_l4_core__aes,
3798         NULL
3799 };
3800
3801 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
3802         &omap3xxx_l4_sec__timer12,
3803         /*
3804          * Apparently the SHA/MD5 and AES accelerator IP blocks are
3805          * only present on some AM35xx chips, and no one knows which
3806          * ones.  See
3807          * http://www.spinics.net/lists/arm-kernel/msg215466.html So
3808          * if you need these IP blocks on an AM35xx, try uncommenting
3809          * the following lines.
3810          */
3811         /* &omap3xxx_l4_core__sham, */
3812         /* &omap3xxx_l4_core__aes, */
3813         NULL
3814 };
3815
3816 /* 3430ES1-only hwmod links */
3817 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3818         &omap3430es1_dss__l3,
3819         &omap3430es1_l4_core__dss,
3820         NULL
3821 };
3822
3823 /* 3430ES2+-only hwmod links */
3824 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3825         &omap3xxx_dss__l3,
3826         &omap3xxx_l4_core__dss,
3827         &omap3xxx_usbhsotg__l3,
3828         &omap3xxx_l4_core__usbhsotg,
3829         &omap3xxx_usb_host_hs__l3_main_2,
3830         &omap3xxx_l4_core__usb_host_hs,
3831         &omap3xxx_l4_core__usb_tll_hs,
3832         NULL
3833 };
3834
3835 /* <= 3430ES3-only hwmod links */
3836 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3837         &omap3xxx_l4_core__pre_es3_mmc1,
3838         &omap3xxx_l4_core__pre_es3_mmc2,
3839         NULL
3840 };
3841
3842 /* 3430ES3+-only hwmod links */
3843 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3844         &omap3xxx_l4_core__es3plus_mmc1,
3845         &omap3xxx_l4_core__es3plus_mmc2,
3846         NULL
3847 };
3848
3849 /* 34xx-only hwmod links (all ES revisions) */
3850 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3851         &omap3xxx_l3__iva,
3852         &omap34xx_l4_core__sr1,
3853         &omap34xx_l4_core__sr2,
3854         &omap3xxx_l4_core__mailbox,
3855         &omap3xxx_l4_core__hdq1w,
3856         &omap3xxx_sad2d__l3,
3857         &omap3xxx_l4_core__mmu_isp,
3858 #ifdef CONFIG_OMAP_IOMMU_IVA2
3859         &omap3xxx_l3_main__mmu_iva,
3860 #endif
3861         &omap34xx_l4_core__ssi,
3862         NULL
3863 };
3864
3865 /* 36xx-only hwmod links (all ES revisions) */
3866 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3867         &omap3xxx_l3__iva,
3868         &omap36xx_l4_per__uart4,
3869         &omap3xxx_dss__l3,
3870         &omap3xxx_l4_core__dss,
3871         &omap36xx_l4_core__sr1,
3872         &omap36xx_l4_core__sr2,
3873         &omap3xxx_usbhsotg__l3,
3874         &omap3xxx_l4_core__usbhsotg,
3875         &omap3xxx_l4_core__mailbox,
3876         &omap3xxx_usb_host_hs__l3_main_2,
3877         &omap3xxx_l4_core__usb_host_hs,
3878         &omap3xxx_l4_core__usb_tll_hs,
3879         &omap3xxx_l4_core__es3plus_mmc1,
3880         &omap3xxx_l4_core__es3plus_mmc2,
3881         &omap3xxx_l4_core__hdq1w,
3882         &omap3xxx_sad2d__l3,
3883         &omap3xxx_l4_core__mmu_isp,
3884 #ifdef CONFIG_OMAP_IOMMU_IVA2
3885         &omap3xxx_l3_main__mmu_iva,
3886 #endif
3887         NULL
3888 };
3889
3890 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3891         &omap3xxx_dss__l3,
3892         &omap3xxx_l4_core__dss,
3893         &am35xx_usbhsotg__l3,
3894         &am35xx_l4_core__usbhsotg,
3895         &am35xx_l4_core__uart4,
3896         &omap3xxx_usb_host_hs__l3_main_2,
3897         &omap3xxx_l4_core__usb_host_hs,
3898         &omap3xxx_l4_core__usb_tll_hs,
3899         &omap3xxx_l4_core__es3plus_mmc1,
3900         &omap3xxx_l4_core__es3plus_mmc2,
3901         &omap3xxx_l4_core__hdq1w,
3902         &am35xx_mdio__l3,
3903         &am35xx_l4_core__mdio,
3904         &am35xx_emac__l3,
3905         &am35xx_l4_core__emac,
3906         NULL
3907 };
3908
3909 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3910         &omap3xxx_l4_core__dss_dispc,
3911         &omap3xxx_l4_core__dss_dsi1,
3912         &omap3xxx_l4_core__dss_rfbi,
3913         &omap3xxx_l4_core__dss_venc,
3914         NULL
3915 };
3916
3917 int __init omap3xxx_hwmod_init(void)
3918 {
3919         int r;
3920         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL;
3921         unsigned int rev;
3922
3923         omap_hwmod_init();
3924
3925         /* Register hwmod links common to all OMAP3 */
3926         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3927         if (r < 0)
3928                 return r;
3929
3930         rev = omap_rev();
3931
3932         /*
3933          * Register hwmod links common to individual OMAP3 families, all
3934          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3935          * All possible revisions should be included in this conditional.
3936          */
3937         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3938             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3939             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3940                 h = omap34xx_hwmod_ocp_ifs;
3941                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
3942         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3943                 h = am35xx_hwmod_ocp_ifs;
3944                 h_gp = am35xx_gp_hwmod_ocp_ifs;
3945         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3946                    rev == OMAP3630_REV_ES1_2) {
3947                 h = omap36xx_hwmod_ocp_ifs;
3948                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
3949         } else {
3950                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3951                 return -EINVAL;
3952         }
3953
3954         r = omap_hwmod_register_links(h);
3955         if (r < 0)
3956                 return r;
3957
3958         /* Register GP-only hwmod links. */
3959         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
3960                 r = omap_hwmod_register_links(h_gp);
3961                 if (r < 0)
3962                         return r;
3963         }
3964
3965
3966         /*
3967          * Register hwmod links specific to certain ES levels of a
3968          * particular family of silicon (e.g., 34xx ES1.0)
3969          */
3970         h = NULL;
3971         if (rev == OMAP3430_REV_ES1_0) {
3972                 h = omap3430es1_hwmod_ocp_ifs;
3973         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3974                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3975                    rev == OMAP3430_REV_ES3_1_2) {
3976                 h = omap3430es2plus_hwmod_ocp_ifs;
3977         }
3978
3979         if (h) {
3980                 r = omap_hwmod_register_links(h);
3981                 if (r < 0)
3982                         return r;
3983         }
3984
3985         h = NULL;
3986         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3987             rev == OMAP3430_REV_ES2_1) {
3988                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3989         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3990                    rev == OMAP3430_REV_ES3_1_2) {
3991                 h = omap3430_es3plus_hwmod_ocp_ifs;
3992         }
3993
3994         if (h)
3995                 r = omap_hwmod_register_links(h);
3996         if (r < 0)
3997                 return r;
3998
3999         /*
4000          * DSS code presumes that dss_core hwmod is handled first,
4001          * _before_ any other DSS related hwmods so register common
4002          * DSS hwmod links last to ensure that dss_core is already
4003          * registered.  Otherwise some change things may happen, for
4004          * ex. if dispc is handled before dss_core and DSS is enabled
4005          * in bootloader DISPC will be reset with outputs enabled
4006          * which sometimes leads to unrecoverable L3 error.  XXX The
4007          * long-term fix to this is to ensure hwmods are set up in
4008          * dependency order in the hwmod core code.
4009          */
4010         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
4011
4012         return r;
4013 }