arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/cpu_pm.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21
  22 #include <asm/firmware.h>
  23 #include <asm/smp_scu.h>
  24 #include <asm/suspend.h>
  25 #include <asm/cacheflush.h>
  26
  27 #include <mach/map.h>
  28
  29 #include <plat/pm-common.h>
  30
  31 #include "common.h"
  32 #include "exynos-pmu.h"
  33 #include "regs-pmu.h"
  34
  35 static inline void __iomem *exynos_boot_vector_addr(void)
  36 {
  37         if (samsung_rev() == EXYNOS4210_REV_1_1)
  38                 return pmu_base_addr + S5P_INFORM7;
  39         else if (samsung_rev() == EXYNOS4210_REV_1_0)
  40                 return sysram_base_addr + 0x24;
  41         return pmu_base_addr + S5P_INFORM0;
  42 }
  43
  44 static inline void __iomem *exynos_boot_vector_flag(void)
  45 {
  46         if (samsung_rev() == EXYNOS4210_REV_1_1)
  47                 return pmu_base_addr + S5P_INFORM6;
  48         else if (samsung_rev() == EXYNOS4210_REV_1_0)
  49                 return sysram_base_addr + 0x20;
  50         return pmu_base_addr + S5P_INFORM1;
  51 }
  52
  53 #define S5P_CHECK_AFTR  0xFCBA0D10
  54
  55 /* For Cortex-A9 Diagnostic and Power control register */
  56 static unsigned int save_arm_register[2];
  57
  58 void exynos_cpu_save_register(void)
  59 {
  60         unsigned long tmp;
  61
  62         /* Save Power control register */
  63         asm ("mrc p15, 0, %0, c15, c0, 0"
  64              : "=r" (tmp) : : "cc");
  65
  66         save_arm_register[0] = tmp;
  67
  68         /* Save Diagnostic register */
  69         asm ("mrc p15, 0, %0, c15, c0, 1"
  70              : "=r" (tmp) : : "cc");
  71
  72         save_arm_register[1] = tmp;
  73 }
  74
  75 void exynos_cpu_restore_register(void)
  76 {
  77         unsigned long tmp;
  78
  79         /* Restore Power control register */
  80         tmp = save_arm_register[0];
  81
  82         asm volatile ("mcr p15, 0, %0, c15, c0, 0"
  83                       : : "r" (tmp)
  84                       : "cc");
  85
  86         /* Restore Diagnostic register */
  87         tmp = save_arm_register[1];
  88
  89         asm volatile ("mcr p15, 0, %0, c15, c0, 1"
  90                       : : "r" (tmp)
  91                       : "cc");
  92 }
  93
  94 void exynos_pm_central_suspend(void)
  95 {
  96         unsigned long tmp;
  97
  98         /* Setting Central Sequence Register for power down mode */
  99         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 100         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 101         pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 102 }
 103
 104 int exynos_pm_central_resume(void)
 105 {
 106         unsigned long tmp;
 107
 108         /*
 109          * If PMU failed while entering sleep mode, WFI will be
 110          * ignored by PMU and then exiting cpu_do_idle().
 111          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 112          * in this situation.
 113          */
 114         tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 115         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 116                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 117                 pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 118                 /* clear the wakeup state register */
 119                 pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
 120                 /* No need to perform below restore code */
 121                 return -1;
 122         }
 123
 124         return 0;
 125 }
 126
 127 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
 128 static void exynos_set_wakeupmask(long mask)
 129 {
 130         pmu_raw_writel(mask, S5P_WAKEUP_MASK);
 131         if (soc_is_exynos3250())
 132                 pmu_raw_writel(0x0, S5P_WAKEUP_MASK2);
 133 }
 134
 135 static void exynos_cpu_set_boot_vector(long flags)
 136 {
 137         __raw_writel(virt_to_phys(exynos_cpu_resume),
 138                      exynos_boot_vector_addr());
 139         __raw_writel(flags, exynos_boot_vector_flag());
 140 }
 141
 142 static int exynos_aftr_finisher(unsigned long flags)
 143 {
 144         int ret;
 145
 146         exynos_set_wakeupmask(soc_is_exynos3250() ? 0x40003ffe : 0x0000ff3e);
 147         /* Set value of power down register for aftr mode */
 148         exynos_sys_powerdown_conf(SYS_AFTR);
 149
 150         ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
 151         if (ret == -ENOSYS) {
 152                 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
 153                         exynos_cpu_save_register();
 154                 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
 155                 cpu_do_idle();
 156         }
 157
 158         return 1;
 159 }
 160
 161 void exynos_enter_aftr(void)
 162 {
 163         unsigned int cpuid = smp_processor_id();
 164
 165         cpu_pm_enter();
 166
 167         if (soc_is_exynos3250())
 168                 exynos_set_boot_flag(cpuid, C2_STATE);
 169
 170         exynos_pm_central_suspend();
 171
 172         if (of_machine_is_compatible("samsung,exynos4212") ||
 173             of_machine_is_compatible("samsung,exynos4412")) {
 174                 /* Setting SEQ_OPTION register */
 175                 pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
 176                                S5P_CENTRAL_SEQ_OPTION);
 177         }
 178
 179         cpu_suspend(0, exynos_aftr_finisher);
 180
 181         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
 182                 scu_enable(S5P_VA_SCU);
 183                 if (call_firmware_op(resume) == -ENOSYS)
 184                         exynos_cpu_restore_register();
 185         }
 186
 187         exynos_pm_central_resume();
 188
 189         if (soc_is_exynos3250())
 190                 exynos_clear_boot_flag(cpuid, C2_STATE);
 191
 192         cpu_pm_exit();
 193 }
 194
 195 #if defined(CONFIG_SMP) && defined(CONFIG_ARM_EXYNOS_CPUIDLE)
 196 static atomic_t cpu1_wakeup = ATOMIC_INIT(0);
 197
 198 static int exynos_cpu0_enter_aftr(void)
 199 {
 200         int ret = -1;
 201
 202         /*
 203          * If the other cpu is powered on, we have to power it off, because
 204          * the AFTR state won't work otherwise
 205          */
 206         if (cpu_online(1)) {
 207                 /*
 208                  * We reach a sync point with the coupled idle state, we know
 209                  * the other cpu will power down itself or will abort the
 210                  * sequence, let's wait for one of these to happen
 211                  */
 212                 while (exynos_cpu_power_state(1)) {
 213                         unsigned long boot_addr;
 214
 215                         /*
 216                          * The other cpu may skip idle and boot back
 217                          * up again
 218                          */
 219                         if (atomic_read(&cpu1_wakeup))
 220                                 goto abort;
 221
 222                         /*
 223                          * The other cpu may bounce through idle and
 224                          * boot back up again, getting stuck in the
 225                          * boot rom code
 226                          */
 227                         ret = exynos_get_boot_addr(1, &boot_addr);
 228                         if (ret)
 229                                 goto fail;
 230                         ret = -1;
 231                         if (boot_addr == 0)
 232                                 goto abort;
 233
 234                         cpu_relax();
 235                 }
 236         }
 237
 238         exynos_enter_aftr();
 239         ret = 0;
 240
 241 abort:
 242         if (cpu_online(1)) {
 243                 unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
 244
 245                 /*
 246                  * Set the boot vector to something non-zero
 247                  */
 248                 ret = exynos_set_boot_addr(1, boot_addr);
 249                 if (ret)
 250                         goto fail;
 251                 dsb();
 252
 253                 /*
 254                  * Turn on cpu1 and wait for it to be on
 255                  */
 256                 exynos_cpu_power_up(1);
 257                 while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN)
 258                         cpu_relax();
 259
 260                 if (soc_is_exynos3250()) {
 261                         while (!pmu_raw_readl(S5P_PMU_SPARE2) &&
 262                                !atomic_read(&cpu1_wakeup))
 263                                 cpu_relax();
 264
 265                         if (!atomic_read(&cpu1_wakeup))
 266                                 exynos_core_restart(1);
 267                 }
 268
 269                 while (!atomic_read(&cpu1_wakeup)) {
 270                         smp_rmb();
 271
 272                         /*
 273                          * Poke cpu1 out of the boot rom
 274                          */
 275
 276                         ret = exynos_set_boot_addr(1, boot_addr);
 277                         if (ret)
 278                                 goto fail;
 279
 280                         call_firmware_op(cpu_boot, 1);
 281
 282                         if (soc_is_exynos3250())
 283                                 dsb_sev();
 284                         else
 285                                 arch_send_wakeup_ipi_mask(cpumask_of(1));
 286                 }
 287         }
 288 fail:
 289         return ret;
 290 }
 291
 292 static int exynos_wfi_finisher(unsigned long flags)
 293 {
 294         if (soc_is_exynos3250())
 295                 flush_cache_all();
 296         cpu_do_idle();
 297
 298         return -1;
 299 }
 300
 301 static int exynos_cpu1_powerdown(void)
 302 {
 303         int ret = -1;
 304
 305         /*
 306          * Idle sequence for cpu1
 307          */
 308         if (cpu_pm_enter())
 309                 goto cpu1_aborted;
 310
 311         /*
 312          * Turn off cpu 1
 313          */
 314         exynos_cpu_power_down(1);
 315
 316         if (soc_is_exynos3250())
 317                 pmu_raw_writel(0, S5P_PMU_SPARE2);
 318
 319         ret = cpu_suspend(0, exynos_wfi_finisher);
 320
 321         cpu_pm_exit();
 322
 323 cpu1_aborted:
 324         dsb();
 325         /*
 326          * Notify cpu 0 that cpu 1 is awake
 327          */
 328         atomic_set(&cpu1_wakeup, 1);
 329
 330         return ret;
 331 }
 332
 333 static void exynos_pre_enter_aftr(void)
 334 {
 335         unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
 336
 337         (void)exynos_set_boot_addr(1, boot_addr);
 338 }
 339
 340 static void exynos_post_enter_aftr(void)
 341 {
 342         atomic_set(&cpu1_wakeup, 0);
 343 }
 344
 345 struct cpuidle_exynos_data cpuidle_coupled_exynos_data = {
 346         .cpu0_enter_aftr                = exynos_cpu0_enter_aftr,
 347         .cpu1_powerdown         = exynos_cpu1_powerdown,
 348         .pre_enter_aftr         = exynos_pre_enter_aftr,
 349         .post_enter_aftr                = exynos_post_enter_aftr,
 350 };
 351 #endif /* CONFIG_SMP && CONFIG_ARM_EXYNOS_CPUIDLE */