arch/arm/mach-exynos/include/mach/regs-pmu.h

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power management unit definition
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #ifndef __ASM_ARCH_REGS_PMU_H
  13 #define __ASM_ARCH_REGS_PMU_H __FILE__
  14
  15 #include <mach/map.h>
  16
  17 #define S5P_PMUREG(x)                           (S5P_VA_PMU + (x))
  18 #define S5P_SYSREG(x)                           (S3C_VA_SYS + (x))
  19
  20 #define S5P_CENTRAL_SEQ_CONFIGURATION           S5P_PMUREG(0x0200)
  21
  22 #define S5P_CENTRAL_LOWPWR_CFG                  (1 << 16)
  23
  24 #define S5P_CENTRAL_SEQ_OPTION                  S5P_PMUREG(0x0208)
  25
  26 #define S5P_USE_STANDBY_WFI0                    (1 << 16)
  27 #define S5P_USE_STANDBY_WFI1                    (1 << 17)
  28 #define S5P_USE_STANDBYWFI_ISP_ARM              (1 << 18)
  29 #define S5P_USE_STANDBY_WFE0                    (1 << 24)
  30 #define S5P_USE_STANDBY_WFE1                    (1 << 25)
  31 #define S5P_USE_STANDBYWFE_ISP_ARM              (1 << 26)
  32
  33 #define S5P_SWRESET                             S5P_PMUREG(0x0400)
  34 #define EXYNOS_SWRESET                          S5P_PMUREG(0x0400)
  35 #define EXYNOS5440_SWRESET                      S5P_PMUREG(0x00C4)
  36
  37 #define S5P_WAKEUP_STAT                         S5P_PMUREG(0x0600)
  38 #define S5P_EINT_WAKEUP_MASK                    S5P_PMUREG(0x0604)
  39 #define S5P_WAKEUP_MASK                         S5P_PMUREG(0x0608)
  40
  41 #define S5P_HDMI_PHY_CONTROL                    S5P_PMUREG(0x0700)
  42 #define S5P_HDMI_PHY_ENABLE                     (1 << 0)
  43
  44 #define S5P_DAC_PHY_CONTROL                     S5P_PMUREG(0x070C)
  45 #define S5P_DAC_PHY_ENABLE                      (1 << 0)
  46
  47 #define S5P_INFORM0                             S5P_PMUREG(0x0800)
  48 #define S5P_INFORM1                             S5P_PMUREG(0x0804)
  49 #define S5P_INFORM2                             S5P_PMUREG(0x0808)
  50 #define S5P_INFORM3                             S5P_PMUREG(0x080C)
  51 #define S5P_INFORM4                             S5P_PMUREG(0x0810)
  52 #define S5P_INFORM5                             S5P_PMUREG(0x0814)
  53 #define S5P_INFORM6                             S5P_PMUREG(0x0818)
  54 #define S5P_INFORM7                             S5P_PMUREG(0x081C)
  55
  56 #define S5P_ARM_CORE0_LOWPWR                    S5P_PMUREG(0x1000)
  57 #define S5P_DIS_IRQ_CORE0                       S5P_PMUREG(0x1004)
  58 #define S5P_DIS_IRQ_CENTRAL0                    S5P_PMUREG(0x1008)
  59 #define S5P_ARM_CORE1_LOWPWR                    S5P_PMUREG(0x1010)
  60 #define S5P_DIS_IRQ_CORE1                       S5P_PMUREG(0x1014)
  61 #define S5P_DIS_IRQ_CENTRAL1                    S5P_PMUREG(0x1018)
  62 #define S5P_ARM_COMMON_LOWPWR                   S5P_PMUREG(0x1080)
  63 #define S5P_L2_0_LOWPWR                         S5P_PMUREG(0x10C0)
  64 #define S5P_L2_1_LOWPWR                         S5P_PMUREG(0x10C4)
  65 #define S5P_CMU_ACLKSTOP_LOWPWR                 S5P_PMUREG(0x1100)
  66 #define S5P_CMU_SCLKSTOP_LOWPWR                 S5P_PMUREG(0x1104)
  67 #define S5P_CMU_RESET_LOWPWR                    S5P_PMUREG(0x110C)
  68 #define S5P_APLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1120)
  69 #define S5P_MPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1124)
  70 #define S5P_VPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x1128)
  71 #define S5P_EPLL_SYSCLK_LOWPWR                  S5P_PMUREG(0x112C)
  72 #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR        S5P_PMUREG(0x1138)
  73 #define S5P_CMU_RESET_GPSALIVE_LOWPWR           S5P_PMUREG(0x113C)
  74 #define S5P_CMU_CLKSTOP_CAM_LOWPWR              S5P_PMUREG(0x1140)
  75 #define S5P_CMU_CLKSTOP_TV_LOWPWR               S5P_PMUREG(0x1144)
  76 #define S5P_CMU_CLKSTOP_MFC_LOWPWR              S5P_PMUREG(0x1148)
  77 #define S5P_CMU_CLKSTOP_G3D_LOWPWR              S5P_PMUREG(0x114C)
  78 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR             S5P_PMUREG(0x1150)
  79 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR           S5P_PMUREG(0x1158)
  80 #define S5P_CMU_CLKSTOP_GPS_LOWPWR              S5P_PMUREG(0x115C)
  81 #define S5P_CMU_RESET_CAM_LOWPWR                S5P_PMUREG(0x1160)
  82 #define S5P_CMU_RESET_TV_LOWPWR                 S5P_PMUREG(0x1164)
  83 #define S5P_CMU_RESET_MFC_LOWPWR                S5P_PMUREG(0x1168)
  84 #define S5P_CMU_RESET_G3D_LOWPWR                S5P_PMUREG(0x116C)
  85 #define S5P_CMU_RESET_LCD0_LOWPWR               S5P_PMUREG(0x1170)
  86 #define S5P_CMU_RESET_MAUDIO_LOWPWR             S5P_PMUREG(0x1178)
  87 #define S5P_CMU_RESET_GPS_LOWPWR                S5P_PMUREG(0x117C)
  88 #define S5P_TOP_BUS_LOWPWR                      S5P_PMUREG(0x1180)
  89 #define S5P_TOP_RETENTION_LOWPWR                S5P_PMUREG(0x1184)
  90 #define S5P_TOP_PWR_LOWPWR                      S5P_PMUREG(0x1188)
  91 #define S5P_LOGIC_RESET_LOWPWR                  S5P_PMUREG(0x11A0)
  92 #define S5P_ONENAND_MEM_LOWPWR                  S5P_PMUREG(0x11C0)
  93 #define S5P_G2D_ACP_MEM_LOWPWR                  S5P_PMUREG(0x11C8)
  94 #define S5P_USBOTG_MEM_LOWPWR                   S5P_PMUREG(0x11CC)
  95 #define S5P_HSMMC_MEM_LOWPWR                    S5P_PMUREG(0x11D0)
  96 #define S5P_CSSYS_MEM_LOWPWR                    S5P_PMUREG(0x11D4)
  97 #define S5P_SECSS_MEM_LOWPWR                    S5P_PMUREG(0x11D8)
  98 #define S5P_PAD_RETENTION_DRAM_LOWPWR           S5P_PMUREG(0x1200)
  99 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR         S5P_PMUREG(0x1204)
 100 #define S5P_PAD_RETENTION_GPIO_LOWPWR           S5P_PMUREG(0x1220)
 101 #define S5P_PAD_RETENTION_UART_LOWPWR           S5P_PMUREG(0x1224)
 102 #define S5P_PAD_RETENTION_MMCA_LOWPWR           S5P_PMUREG(0x1228)
 103 #define S5P_PAD_RETENTION_MMCB_LOWPWR           S5P_PMUREG(0x122C)
 104 #define S5P_PAD_RETENTION_EBIA_LOWPWR           S5P_PMUREG(0x1230)
 105 #define S5P_PAD_RETENTION_EBIB_LOWPWR           S5P_PMUREG(0x1234)
 106 #define S5P_PAD_RETENTION_ISOLATION_LOWPWR      S5P_PMUREG(0x1240)
 107 #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR        S5P_PMUREG(0x1260)
 108 #define S5P_XUSBXTI_LOWPWR                      S5P_PMUREG(0x1280)
 109 #define S5P_XXTI_LOWPWR                         S5P_PMUREG(0x1284)
 110 #define S5P_EXT_REGULATOR_LOWPWR                S5P_PMUREG(0x12C0)
 111 #define S5P_GPIO_MODE_LOWPWR                    S5P_PMUREG(0x1300)
 112 #define S5P_GPIO_MODE_MAUDIO_LOWPWR             S5P_PMUREG(0x1340)
 113 #define S5P_CAM_LOWPWR                          S5P_PMUREG(0x1380)
 114 #define S5P_TV_LOWPWR                           S5P_PMUREG(0x1384)
 115 #define S5P_MFC_LOWPWR                          S5P_PMUREG(0x1388)
 116 #define S5P_G3D_LOWPWR                          S5P_PMUREG(0x138C)
 117 #define S5P_LCD0_LOWPWR                         S5P_PMUREG(0x1390)
 118 #define S5P_MAUDIO_LOWPWR                       S5P_PMUREG(0x1398)
 119 #define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
 120 #define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
 121
 122 #define S5P_ARM_CORE0_CONFIGURATION             S5P_PMUREG(0x2000)
 123 #define S5P_ARM_CORE0_OPTION                    S5P_PMUREG(0x2008)
 124 #define S5P_ARM_CORE1_CONFIGURATION             S5P_PMUREG(0x2080)
 125 #define S5P_ARM_CORE1_STATUS                    S5P_PMUREG(0x2084)
 126 #define S5P_ARM_CORE1_OPTION                    S5P_PMUREG(0x2088)
 127
 128 #define S5P_ARM_COMMON_OPTION                   S5P_PMUREG(0x2408)
 129 #define S5P_TOP_PWR_OPTION                      S5P_PMUREG(0x2C48)
 130 #define S5P_CAM_OPTION                          S5P_PMUREG(0x3C08)
 131 #define S5P_TV_OPTION                           S5P_PMUREG(0x3C28)
 132 #define S5P_MFC_OPTION                          S5P_PMUREG(0x3C48)
 133 #define S5P_G3D_OPTION                          S5P_PMUREG(0x3C68)
 134 #define S5P_LCD0_OPTION                         S5P_PMUREG(0x3C88)
 135 #define S5P_LCD1_OPTION                         S5P_PMUREG(0x3CA8)
 136 #define S5P_MAUDIO_OPTION                       S5P_PMUREG(0x3CC8)
 137 #define S5P_GPS_OPTION                          S5P_PMUREG(0x3CE8)
 138 #define S5P_GPS_ALIVE_OPTION                    S5P_PMUREG(0x3D08)
 139
 140 #define S5P_PAD_RET_MAUDIO_OPTION               S5P_PMUREG(0x3028)
 141 #define S5P_PAD_RET_GPIO_OPTION                 S5P_PMUREG(0x3108)
 142 #define S5P_PAD_RET_UART_OPTION                 S5P_PMUREG(0x3128)
 143 #define S5P_PAD_RET_MMCA_OPTION                 S5P_PMUREG(0x3148)
 144 #define S5P_PAD_RET_MMCB_OPTION                 S5P_PMUREG(0x3168)
 145 #define S5P_PAD_RET_EBIA_OPTION                 S5P_PMUREG(0x3188)
 146 #define S5P_PAD_RET_EBIB_OPTION                 S5P_PMUREG(0x31A8)
 147
 148 #define S5P_PMU_CAM_CONF                        S5P_PMUREG(0x3C00)
 149 #define S5P_PMU_TV_CONF                         S5P_PMUREG(0x3C20)
 150 #define S5P_PMU_MFC_CONF                        S5P_PMUREG(0x3C40)
 151 #define S5P_PMU_G3D_CONF                        S5P_PMUREG(0x3C60)
 152 #define S5P_PMU_LCD0_CONF                       S5P_PMUREG(0x3C80)
 153 #define S5P_PMU_GPS_CONF                        S5P_PMUREG(0x3CE0)
 154
 155 #define S5P_PMU_SATA_PHY_CONTROL_EN             0x1
 156 #define S5P_CORE_LOCAL_PWR_EN                   0x3
 157 #define S5P_INT_LOCAL_PWR_EN                    0x7
 158
 159 #define S5P_CHECK_SLEEP                         0x00000BAD
 160
 161 /* Only for EXYNOS4210 */
 162 #define S5P_USBDEVICE_PHY_CONTROL       S5P_PMUREG(0x0704)
 163 #define S5P_USBDEVICE_PHY_ENABLE        (1 << 0)
 164
 165 #define S5P_USBHOST_PHY_CONTROL         S5P_PMUREG(0x0708)
 166 #define S5P_USBHOST_PHY_ENABLE          (1 << 0)
 167
 168 #define S5P_PMU_SATA_PHY_CONTROL        S5P_PMUREG(0x0720)
 169
 170 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
 171 #define S5P_CMU_RESET_LCD1_LOWPWR       S5P_PMUREG(0x1174)
 172 #define S5P_MODIMIF_MEM_LOWPWR          S5P_PMUREG(0x11C4)
 173 #define S5P_PCIE_MEM_LOWPWR             S5P_PMUREG(0x11E0)
 174 #define S5P_SATA_MEM_LOWPWR             S5P_PMUREG(0x11E4)
 175 #define S5P_LCD1_LOWPWR                 S5P_PMUREG(0x1394)
 176
 177 #define S5P_PMU_LCD1_CONF               S5P_PMUREG(0x3CA0)
 178
 179 /* Only for EXYNOS4x12 */
 180 #define S5P_ISP_ARM_LOWPWR                      S5P_PMUREG(0x1050)
 181 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR        S5P_PMUREG(0x1054)
 182 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR      S5P_PMUREG(0x1058)
 183 #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1110)
 184 #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR         S5P_PMUREG(0x1114)
 185 #define S5P_CMU_RESET_COREBLK_LOWPWR            S5P_PMUREG(0x111C)
 186 #define S5P_MPLLUSER_SYSCLK_LOWPWR              S5P_PMUREG(0x1130)
 187 #define S5P_CMU_CLKSTOP_ISP_LOWPWR              S5P_PMUREG(0x1154)
 188 #define S5P_CMU_RESET_ISP_LOWPWR                S5P_PMUREG(0x1174)
 189 #define S5P_TOP_BUS_COREBLK_LOWPWR              S5P_PMUREG(0x1190)
 190 #define S5P_TOP_RETENTION_COREBLK_LOWPWR        S5P_PMUREG(0x1194)
 191 #define S5P_TOP_PWR_COREBLK_LOWPWR              S5P_PMUREG(0x1198)
 192 #define S5P_OSCCLK_GATE_LOWPWR                  S5P_PMUREG(0x11A4)
 193 #define S5P_LOGIC_RESET_COREBLK_LOWPWR          S5P_PMUREG(0x11B0)
 194 #define S5P_OSCCLK_GATE_COREBLK_LOWPWR          S5P_PMUREG(0x11B4)
 195 #define S5P_HSI_MEM_LOWPWR                      S5P_PMUREG(0x11C4)
 196 #define S5P_ROTATOR_MEM_LOWPWR                  S5P_PMUREG(0x11DC)
 197 #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR   S5P_PMUREG(0x123C)
 198 #define S5P_PAD_ISOLATION_COREBLK_LOWPWR        S5P_PMUREG(0x1250)
 199 #define S5P_GPIO_MODE_COREBLK_LOWPWR            S5P_PMUREG(0x1320)
 200 #define S5P_TOP_ASB_RESET_LOWPWR                S5P_PMUREG(0x1344)
 201 #define S5P_TOP_ASB_ISOLATION_LOWPWR            S5P_PMUREG(0x1348)
 202 #define S5P_ISP_LOWPWR                          S5P_PMUREG(0x1394)
 203 #define S5P_DRAM_FREQ_DOWN_LOWPWR               S5P_PMUREG(0x13B0)
 204 #define S5P_DDRPHY_DLLOFF_LOWPWR                S5P_PMUREG(0x13B4)
 205 #define S5P_CMU_SYSCLK_ISP_LOWPWR               S5P_PMUREG(0x13B8)
 206 #define S5P_CMU_SYSCLK_GPS_LOWPWR               S5P_PMUREG(0x13BC)
 207 #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR           S5P_PMUREG(0x13C0)
 208
 209 #define S5P_ARM_L2_0_OPTION                     S5P_PMUREG(0x2608)
 210 #define S5P_ARM_L2_1_OPTION                     S5P_PMUREG(0x2628)
 211 #define S5P_ONENAND_MEM_OPTION                  S5P_PMUREG(0x2E08)
 212 #define S5P_HSI_MEM_OPTION                      S5P_PMUREG(0x2E28)
 213 #define S5P_G2D_ACP_MEM_OPTION                  S5P_PMUREG(0x2E48)
 214 #define S5P_USBOTG_MEM_OPTION                   S5P_PMUREG(0x2E68)
 215 #define S5P_HSMMC_MEM_OPTION                    S5P_PMUREG(0x2E88)
 216 #define S5P_CSSYS_MEM_OPTION                    S5P_PMUREG(0x2EA8)
 217 #define S5P_SECSS_MEM_OPTION                    S5P_PMUREG(0x2EC8)
 218 #define S5P_ROTATOR_MEM_OPTION                  S5P_PMUREG(0x2F48)
 219
 220 /* Only for EXYNOS4412 */
 221 #define S5P_ARM_CORE2_LOWPWR                    S5P_PMUREG(0x1020)
 222 #define S5P_DIS_IRQ_CORE2                       S5P_PMUREG(0x1024)
 223 #define S5P_DIS_IRQ_CENTRAL2                    S5P_PMUREG(0x1028)
 224 #define S5P_ARM_CORE3_LOWPWR                    S5P_PMUREG(0x1030)
 225 #define S5P_DIS_IRQ_CORE3                       S5P_PMUREG(0x1034)
 226 #define S5P_DIS_IRQ_CENTRAL3                    S5P_PMUREG(0x1038)
 227
 228 /* For EXYNOS5 */
 229
 230 #define EXYNOS5_SYS_I2C_CFG                                     S5P_SYSREG(0x0234)
 231
 232 #define EXYNOS5_AUTO_WDTRESET_DISABLE                           S5P_PMUREG(0x0408)
 233 #define EXYNOS5_MASK_WDTRESET_REQUEST                           S5P_PMUREG(0x040C)
 234
 235 #define EXYNOS5_SYS_WDTRESET                                    (1 << 20)
 236
 237 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           S5P_PMUREG(0x1000)
 238 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1004)
 239 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1008)
 240 #define EXYNOS5_ARM_CORE1_SYS_PWR_REG                           S5P_PMUREG(0x1010)
 241 #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1014)
 242 #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1018)
 243 #define EXYNOS5_FSYS_ARM_SYS_PWR_REG                            S5P_PMUREG(0x1040)
 244 #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG            S5P_PMUREG(0x1048)
 245 #define EXYNOS5_ISP_ARM_SYS_PWR_REG                             S5P_PMUREG(0x1050)
 246 #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG               S5P_PMUREG(0x1054)
 247 #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG             S5P_PMUREG(0x1058)
 248 #define EXYNOS5_ARM_COMMON_SYS_PWR_REG                          S5P_PMUREG(0x1080)
 249 #define EXYNOS5_ARM_L2_SYS_PWR_REG                              S5P_PMUREG(0x10C0)
 250 #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG                        S5P_PMUREG(0x1100)
 251 #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG                        S5P_PMUREG(0x1104)
 252 #define EXYNOS5_CMU_RESET_SYS_PWR_REG                           S5P_PMUREG(0x110C)
 253 #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG                 S5P_PMUREG(0x1120)
 254 #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG                 S5P_PMUREG(0x1124)
 255 #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG                    S5P_PMUREG(0x112C)
 256 #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG                      S5P_PMUREG(0x1130)
 257 #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG                       S5P_PMUREG(0x1134)
 258 #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG                      S5P_PMUREG(0x1138)
 259 #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1140)
 260 #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1144)
 261 #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1148)
 262 #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x114C)
 263 #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1150)
 264 #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG                         S5P_PMUREG(0x1154)
 265 #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG                     S5P_PMUREG(0x1164)
 266 #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG                     S5P_PMUREG(0x1170)
 267 #define EXYNOS5_TOP_BUS_SYS_PWR_REG                             S5P_PMUREG(0x1180)
 268 #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG                       S5P_PMUREG(0x1184)
 269 #define EXYNOS5_TOP_PWR_SYS_PWR_REG                             S5P_PMUREG(0x1188)
 270 #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG                      S5P_PMUREG(0x1190)
 271 #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x1194)
 272 #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG                      S5P_PMUREG(0x1198)
 273 #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG                         S5P_PMUREG(0x11A0)
 274 #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG                         S5P_PMUREG(0x11A4)
 275 #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG                  S5P_PMUREG(0x11B0)
 276 #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG                  S5P_PMUREG(0x11B4)
 277 #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11C0)
 278 #define EXYNOS5_G2D_MEM_SYS_PWR_REG                             S5P_PMUREG(0x11C8)
 279 #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11CC)
 280 #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D0)
 281 #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D4)
 282 #define EXYNOS5_SECSS_MEM_SYS_PWR_REG                           S5P_PMUREG(0x11D8)
 283 #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG                         S5P_PMUREG(0x11DC)
 284 #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11E0)
 285 #define EXYNOS5_INTROM_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11E4)
 286 #define EXYNOS5_JPEG_MEM_SYS_PWR_REG                            S5P_PMUREG(0x11E8)
 287 #define EXYNOS5_HSI_MEM_SYS_PWR_REG                             S5P_PMUREG(0x11EC)
 288 #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG                          S5P_PMUREG(0x11F4)
 289 #define EXYNOS5_SATA_MEM_SYS_PWR_REG                            S5P_PMUREG(0x11FC)
 290 #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG                  S5P_PMUREG(0x1200)
 291 #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG                   S5P_PMUREG(0x1204)
 292 #define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG                S5P_PMUREG(0x1208)
 293 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG                  S5P_PMUREG(0x1220)
 294 #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG                  S5P_PMUREG(0x1224)
 295 #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG                  S5P_PMUREG(0x1228)
 296 #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG                  S5P_PMUREG(0x122C)
 297 #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG                  S5P_PMUREG(0x1230)
 298 #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG                  S5P_PMUREG(0x1234)
 299 #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG                   S5P_PMUREG(0x1238)
 300 #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG           S5P_PMUREG(0x123C)
 301 #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG                       S5P_PMUREG(0x1240)
 302 #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG                S5P_PMUREG(0x1250)
 303 #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG                         S5P_PMUREG(0x1260)
 304 #define EXYNOS5_XUSBXTI_SYS_PWR_REG                             S5P_PMUREG(0x1280)
 305 #define EXYNOS5_XXTI_SYS_PWR_REG                                S5P_PMUREG(0x1284)
 306 #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG                       S5P_PMUREG(0x12C0)
 307 #define EXYNOS5_GPIO_MODE_SYS_PWR_REG                           S5P_PMUREG(0x1300)
 308 #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG                    S5P_PMUREG(0x1320)
 309 #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG                       S5P_PMUREG(0x1340)
 310 #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG                       S5P_PMUREG(0x1344)
 311 #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG                   S5P_PMUREG(0x1348)
 312 #define EXYNOS5_GSCL_SYS_PWR_REG                                S5P_PMUREG(0x1400)
 313 #define EXYNOS5_ISP_SYS_PWR_REG                                 S5P_PMUREG(0x1404)
 314 #define EXYNOS5_MFC_SYS_PWR_REG                                 S5P_PMUREG(0x1408)
 315 #define EXYNOS5_G3D_SYS_PWR_REG                                 S5P_PMUREG(0x140C)
 316 #define EXYNOS5_DISP1_SYS_PWR_REG                               S5P_PMUREG(0x1414)
 317 #define EXYNOS5_MAU_SYS_PWR_REG                                 S5P_PMUREG(0x1418)
 318 #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG                    S5P_PMUREG(0x1480)
 319 #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG                     S5P_PMUREG(0x1484)
 320 #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG                     S5P_PMUREG(0x1488)
 321 #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG                     S5P_PMUREG(0x148C)
 322 #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG                   S5P_PMUREG(0x1494)
 323 #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG                     S5P_PMUREG(0x1498)
 324 #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG                     S5P_PMUREG(0x14C0)
 325 #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG                      S5P_PMUREG(0x14C4)
 326 #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG                      S5P_PMUREG(0x14C8)
 327 #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG                      S5P_PMUREG(0x14CC)
 328 #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG                    S5P_PMUREG(0x14D4)
 329 #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG                      S5P_PMUREG(0x14D8)
 330 #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG                      S5P_PMUREG(0x1580)
 331 #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG                       S5P_PMUREG(0x1584)
 332 #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG                       S5P_PMUREG(0x1588)
 333 #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG                       S5P_PMUREG(0x158C)
 334 #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG                     S5P_PMUREG(0x1594)
 335 #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG                       S5P_PMUREG(0x1598)
 336
 337 #define EXYNOS5_ARM_CORE0_OPTION                                S5P_PMUREG(0x2008)
 338 #define EXYNOS5_ARM_CORE1_OPTION                                S5P_PMUREG(0x2088)
 339 #define EXYNOS5_FSYS_ARM_OPTION                                 S5P_PMUREG(0x2208)
 340 #define EXYNOS5_ISP_ARM_OPTION                                  S5P_PMUREG(0x2288)
 341 #define EXYNOS5_ARM_COMMON_OPTION                               S5P_PMUREG(0x2408)
 342 #define EXYNOS5_ARM_L2_OPTION                                   S5P_PMUREG(0x2608)
 343 #define EXYNOS5_TOP_PWR_OPTION                                  S5P_PMUREG(0x2C48)
 344 #define EXYNOS5_TOP_PWR_SYSMEM_OPTION                           S5P_PMUREG(0x2CC8)
 345 #define EXYNOS5_JPEG_MEM_OPTION                                 S5P_PMUREG(0x2F48)
 346 #define EXYNOS5_GSCL_STATUS                                     S5P_PMUREG(0x4004)
 347 #define EXYNOS5_ISP_STATUS                                      S5P_PMUREG(0x4024)
 348 #define EXYNOS5_GSCL_OPTION                                     S5P_PMUREG(0x4008)
 349 #define EXYNOS5_ISP_OPTION                                      S5P_PMUREG(0x4028)
 350 #define EXYNOS5_MFC_OPTION                                      S5P_PMUREG(0x4048)
 351 #define EXYNOS5_G3D_CONFIGURATION                               S5P_PMUREG(0x4060)
 352 #define EXYNOS5_G3D_STATUS                                      S5P_PMUREG(0x4064)
 353 #define EXYNOS5_G3D_OPTION                                      S5P_PMUREG(0x4068)
 354 #define EXYNOS5_DISP1_OPTION                                    S5P_PMUREG(0x40A8)
 355 #define EXYNOS5_MAU_OPTION                                      S5P_PMUREG(0x40C8)
 356
 357 #define EXYNOS5_USE_SC_FEEDBACK                                 (1 << 1)
 358 #define EXYNOS5_USE_SC_COUNTER                                  (1 << 0)
 359
 360 #define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL                     (1 << 2)
 361 #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN                  (1 << 7)
 362
 363 #define EXYNOS5_OPTION_USE_STANDBYWFE                           (1 << 24)
 364 #define EXYNOS5_OPTION_USE_STANDBYWFI                           (1 << 16)
 365
 366 #define EXYNOS5_OPTION_USE_RETENTION                            (1 << 4)
 367
 368 #endif /* __ASM_ARCH_REGS_PMU_H */