arch/arm/mach-davinci/dm365.c

   1 /*
   2  * TI DaVinci DM365 chip specific setup
   3  *
   4  * Copyright (C) 2009 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/clk.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/platform_data/edma.h>
  22 #include <linux/platform_data/gpio-davinci.h>
  23 #include <linux/platform_data/keyscan-davinci.h>
  24 #include <linux/platform_data/spi-davinci.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <mach/cputype.h>
  29 #include <mach/psc.h>
  30 #include <mach/mux.h>
  31 #include <mach/irqs.h>
  32 #include <mach/time.h>
  33 #include <mach/serial.h>
  34 #include <mach/common.h>
  35
  36 #include "davinci.h"
  37 #include "clock.h"
  38 #include "mux.h"
  39 #include "asp.h"
  40
  41 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
  42 #define DM365_RTC_BASE                  0x01c69000
  43 #define DM365_KEYSCAN_BASE              0x01c69400
  44 #define DM365_OSD_BASE                  0x01c71c00
  45 #define DM365_VENC_BASE                 0x01c71e00
  46 #define DAVINCI_DM365_VC_BASE           0x01d0c000
  47 #define DAVINCI_DMA_VC_TX               2
  48 #define DAVINCI_DMA_VC_RX               3
  49 #define DM365_EMAC_BASE                 0x01d07000
  50 #define DM365_EMAC_MDIO_BASE            (DM365_EMAC_BASE + 0x4000)
  51 #define DM365_EMAC_CNTRL_OFFSET         0x0000
  52 #define DM365_EMAC_CNTRL_MOD_OFFSET     0x3000
  53 #define DM365_EMAC_CNTRL_RAM_OFFSET     0x1000
  54 #define DM365_EMAC_CNTRL_RAM_SIZE       0x2000
  55
  56 static struct pll_data pll1_data = {
  57         .num            = 1,
  58         .phys_base      = DAVINCI_PLL1_BASE,
  59         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  60 };
  61
  62 static struct pll_data pll2_data = {
  63         .num            = 2,
  64         .phys_base      = DAVINCI_PLL2_BASE,
  65         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
  66 };
  67
  68 static struct clk ref_clk = {
  69         .name           = "ref_clk",
  70         .rate           = DM365_REF_FREQ,
  71 };
  72
  73 static struct clk pll1_clk = {
  74         .name           = "pll1",
  75         .parent         = &ref_clk,
  76         .flags          = CLK_PLL,
  77         .pll_data       = &pll1_data,
  78 };
  79
  80 static struct clk pll1_aux_clk = {
  81         .name           = "pll1_aux_clk",
  82         .parent         = &pll1_clk,
  83         .flags          = CLK_PLL | PRE_PLL,
  84 };
  85
  86 static struct clk pll1_sysclkbp = {
  87         .name           = "pll1_sysclkbp",
  88         .parent         = &pll1_clk,
  89         .flags          = CLK_PLL | PRE_PLL,
  90         .div_reg        = BPDIV
  91 };
  92
  93 static struct clk clkout0_clk = {
  94         .name           = "clkout0",
  95         .parent         = &pll1_clk,
  96         .flags          = CLK_PLL | PRE_PLL,
  97 };
  98
  99 static struct clk pll1_sysclk1 = {
 100         .name           = "pll1_sysclk1",
 101         .parent         = &pll1_clk,
 102         .flags          = CLK_PLL,
 103         .div_reg        = PLLDIV1,
 104 };
 105
 106 static struct clk pll1_sysclk2 = {
 107         .name           = "pll1_sysclk2",
 108         .parent         = &pll1_clk,
 109         .flags          = CLK_PLL,
 110         .div_reg        = PLLDIV2,
 111 };
 112
 113 static struct clk pll1_sysclk3 = {
 114         .name           = "pll1_sysclk3",
 115         .parent         = &pll1_clk,
 116         .flags          = CLK_PLL,
 117         .div_reg        = PLLDIV3,
 118 };
 119
 120 static struct clk pll1_sysclk4 = {
 121         .name           = "pll1_sysclk4",
 122         .parent         = &pll1_clk,
 123         .flags          = CLK_PLL,
 124         .div_reg        = PLLDIV4,
 125 };
 126
 127 static struct clk pll1_sysclk5 = {
 128         .name           = "pll1_sysclk5",
 129         .parent         = &pll1_clk,
 130         .flags          = CLK_PLL,
 131         .div_reg        = PLLDIV5,
 132 };
 133
 134 static struct clk pll1_sysclk6 = {
 135         .name           = "pll1_sysclk6",
 136         .parent         = &pll1_clk,
 137         .flags          = CLK_PLL,
 138         .div_reg        = PLLDIV6,
 139 };
 140
 141 static struct clk pll1_sysclk7 = {
 142         .name           = "pll1_sysclk7",
 143         .parent         = &pll1_clk,
 144         .flags          = CLK_PLL,
 145         .div_reg        = PLLDIV7,
 146 };
 147
 148 static struct clk pll1_sysclk8 = {
 149         .name           = "pll1_sysclk8",
 150         .parent         = &pll1_clk,
 151         .flags          = CLK_PLL,
 152         .div_reg        = PLLDIV8,
 153 };
 154
 155 static struct clk pll1_sysclk9 = {
 156         .name           = "pll1_sysclk9",
 157         .parent         = &pll1_clk,
 158         .flags          = CLK_PLL,
 159         .div_reg        = PLLDIV9,
 160 };
 161
 162 static struct clk pll2_clk = {
 163         .name           = "pll2",
 164         .parent         = &ref_clk,
 165         .flags          = CLK_PLL,
 166         .pll_data       = &pll2_data,
 167 };
 168
 169 static struct clk pll2_aux_clk = {
 170         .name           = "pll2_aux_clk",
 171         .parent         = &pll2_clk,
 172         .flags          = CLK_PLL | PRE_PLL,
 173 };
 174
 175 static struct clk clkout1_clk = {
 176         .name           = "clkout1",
 177         .parent         = &pll2_clk,
 178         .flags          = CLK_PLL | PRE_PLL,
 179 };
 180
 181 static struct clk pll2_sysclk1 = {
 182         .name           = "pll2_sysclk1",
 183         .parent         = &pll2_clk,
 184         .flags          = CLK_PLL,
 185         .div_reg        = PLLDIV1,
 186 };
 187
 188 static struct clk pll2_sysclk2 = {
 189         .name           = "pll2_sysclk2",
 190         .parent         = &pll2_clk,
 191         .flags          = CLK_PLL,
 192         .div_reg        = PLLDIV2,
 193 };
 194
 195 static struct clk pll2_sysclk3 = {
 196         .name           = "pll2_sysclk3",
 197         .parent         = &pll2_clk,
 198         .flags          = CLK_PLL,
 199         .div_reg        = PLLDIV3,
 200 };
 201
 202 static struct clk pll2_sysclk4 = {
 203         .name           = "pll2_sysclk4",
 204         .parent         = &pll2_clk,
 205         .flags          = CLK_PLL,
 206         .div_reg        = PLLDIV4,
 207 };
 208
 209 static struct clk pll2_sysclk5 = {
 210         .name           = "pll2_sysclk5",
 211         .parent         = &pll2_clk,
 212         .flags          = CLK_PLL,
 213         .div_reg        = PLLDIV5,
 214 };
 215
 216 static struct clk pll2_sysclk6 = {
 217         .name           = "pll2_sysclk6",
 218         .parent         = &pll2_clk,
 219         .flags          = CLK_PLL,
 220         .div_reg        = PLLDIV6,
 221 };
 222
 223 static struct clk pll2_sysclk7 = {
 224         .name           = "pll2_sysclk7",
 225         .parent         = &pll2_clk,
 226         .flags          = CLK_PLL,
 227         .div_reg        = PLLDIV7,
 228 };
 229
 230 static struct clk pll2_sysclk8 = {
 231         .name           = "pll2_sysclk8",
 232         .parent         = &pll2_clk,
 233         .flags          = CLK_PLL,
 234         .div_reg        = PLLDIV8,
 235 };
 236
 237 static struct clk pll2_sysclk9 = {
 238         .name           = "pll2_sysclk9",
 239         .parent         = &pll2_clk,
 240         .flags          = CLK_PLL,
 241         .div_reg        = PLLDIV9,
 242 };
 243
 244 static struct clk vpss_dac_clk = {
 245         .name           = "vpss_dac",
 246         .parent         = &pll1_sysclk3,
 247         .lpsc           = DM365_LPSC_DAC_CLK,
 248 };
 249
 250 static struct clk vpss_master_clk = {
 251         .name           = "vpss_master",
 252         .parent         = &pll1_sysclk5,
 253         .lpsc           = DM365_LPSC_VPSSMSTR,
 254         .flags          = CLK_PSC,
 255 };
 256
 257 static struct clk vpss_slave_clk = {
 258         .name           = "vpss_slave",
 259         .parent         = &pll1_sysclk5,
 260         .lpsc           = DAVINCI_LPSC_VPSSSLV,
 261 };
 262
 263 static struct clk arm_clk = {
 264         .name           = "arm_clk",
 265         .parent         = &pll2_sysclk2,
 266         .lpsc           = DAVINCI_LPSC_ARM,
 267         .flags          = ALWAYS_ENABLED,
 268 };
 269
 270 static struct clk uart0_clk = {
 271         .name           = "uart0",
 272         .parent         = &pll1_aux_clk,
 273         .lpsc           = DAVINCI_LPSC_UART0,
 274 };
 275
 276 static struct clk uart1_clk = {
 277         .name           = "uart1",
 278         .parent         = &pll1_sysclk4,
 279         .lpsc           = DAVINCI_LPSC_UART1,
 280 };
 281
 282 static struct clk i2c_clk = {
 283         .name           = "i2c",
 284         .parent         = &pll1_aux_clk,
 285         .lpsc           = DAVINCI_LPSC_I2C,
 286 };
 287
 288 static struct clk mmcsd0_clk = {
 289         .name           = "mmcsd0",
 290         .parent         = &pll1_sysclk8,
 291         .lpsc           = DAVINCI_LPSC_MMC_SD,
 292 };
 293
 294 static struct clk mmcsd1_clk = {
 295         .name           = "mmcsd1",
 296         .parent         = &pll1_sysclk4,
 297         .lpsc           = DM365_LPSC_MMC_SD1,
 298 };
 299
 300 static struct clk spi0_clk = {
 301         .name           = "spi0",
 302         .parent         = &pll1_sysclk4,
 303         .lpsc           = DAVINCI_LPSC_SPI,
 304 };
 305
 306 static struct clk spi1_clk = {
 307         .name           = "spi1",
 308         .parent         = &pll1_sysclk4,
 309         .lpsc           = DM365_LPSC_SPI1,
 310 };
 311
 312 static struct clk spi2_clk = {
 313         .name           = "spi2",
 314         .parent         = &pll1_sysclk4,
 315         .lpsc           = DM365_LPSC_SPI2,
 316 };
 317
 318 static struct clk spi3_clk = {
 319         .name           = "spi3",
 320         .parent         = &pll1_sysclk4,
 321         .lpsc           = DM365_LPSC_SPI3,
 322 };
 323
 324 static struct clk spi4_clk = {
 325         .name           = "spi4",
 326         .parent         = &pll1_aux_clk,
 327         .lpsc           = DM365_LPSC_SPI4,
 328 };
 329
 330 static struct clk gpio_clk = {
 331         .name           = "gpio",
 332         .parent         = &pll1_sysclk4,
 333         .lpsc           = DAVINCI_LPSC_GPIO,
 334 };
 335
 336 static struct clk aemif_clk = {
 337         .name           = "aemif",
 338         .parent         = &pll1_sysclk4,
 339         .lpsc           = DAVINCI_LPSC_AEMIF,
 340 };
 341
 342 static struct clk pwm0_clk = {
 343         .name           = "pwm0",
 344         .parent         = &pll1_aux_clk,
 345         .lpsc           = DAVINCI_LPSC_PWM0,
 346 };
 347
 348 static struct clk pwm1_clk = {
 349         .name           = "pwm1",
 350         .parent         = &pll1_aux_clk,
 351         .lpsc           = DAVINCI_LPSC_PWM1,
 352 };
 353
 354 static struct clk pwm2_clk = {
 355         .name           = "pwm2",
 356         .parent         = &pll1_aux_clk,
 357         .lpsc           = DAVINCI_LPSC_PWM2,
 358 };
 359
 360 static struct clk pwm3_clk = {
 361         .name           = "pwm3",
 362         .parent         = &ref_clk,
 363         .lpsc           = DM365_LPSC_PWM3,
 364 };
 365
 366 static struct clk timer0_clk = {
 367         .name           = "timer0",
 368         .parent         = &pll1_aux_clk,
 369         .lpsc           = DAVINCI_LPSC_TIMER0,
 370 };
 371
 372 static struct clk timer1_clk = {
 373         .name           = "timer1",
 374         .parent         = &pll1_aux_clk,
 375         .lpsc           = DAVINCI_LPSC_TIMER1,
 376 };
 377
 378 static struct clk timer2_clk = {
 379         .name           = "timer2",
 380         .parent         = &pll1_aux_clk,
 381         .lpsc           = DAVINCI_LPSC_TIMER2,
 382         .usecount       = 1,
 383 };
 384
 385 static struct clk timer3_clk = {
 386         .name           = "timer3",
 387         .parent         = &pll1_aux_clk,
 388         .lpsc           = DM365_LPSC_TIMER3,
 389 };
 390
 391 static struct clk usb_clk = {
 392         .name           = "usb",
 393         .parent         = &pll1_aux_clk,
 394         .lpsc           = DAVINCI_LPSC_USB,
 395 };
 396
 397 static struct clk emac_clk = {
 398         .name           = "emac",
 399         .parent         = &pll1_sysclk4,
 400         .lpsc           = DM365_LPSC_EMAC,
 401 };
 402
 403 static struct clk voicecodec_clk = {
 404         .name           = "voice_codec",
 405         .parent         = &pll2_sysclk4,
 406         .lpsc           = DM365_LPSC_VOICE_CODEC,
 407 };
 408
 409 static struct clk asp0_clk = {
 410         .name           = "asp0",
 411         .parent         = &pll1_sysclk4,
 412         .lpsc           = DM365_LPSC_McBSP1,
 413 };
 414
 415 static struct clk rto_clk = {
 416         .name           = "rto",
 417         .parent         = &pll1_sysclk4,
 418         .lpsc           = DM365_LPSC_RTO,
 419 };
 420
 421 static struct clk mjcp_clk = {
 422         .name           = "mjcp",
 423         .parent         = &pll1_sysclk3,
 424         .lpsc           = DM365_LPSC_MJCP,
 425 };
 426
 427 static struct clk_lookup dm365_clks[] = {
 428         CLK(NULL, "ref", &ref_clk),
 429         CLK(NULL, "pll1", &pll1_clk),
 430         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 431         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 432         CLK(NULL, "clkout0", &clkout0_clk),
 433         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 434         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 435         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 436         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 437         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 438         CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
 439         CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
 440         CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
 441         CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
 442         CLK(NULL, "pll2", &pll2_clk),
 443         CLK(NULL, "pll2_aux", &pll2_aux_clk),
 444         CLK(NULL, "clkout1", &clkout1_clk),
 445         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 446         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 447         CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
 448         CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
 449         CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
 450         CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
 451         CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
 452         CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
 453         CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
 454         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 455         CLK("vpss", "master", &vpss_master_clk),
 456         CLK("vpss", "slave", &vpss_slave_clk),
 457         CLK(NULL, "arm", &arm_clk),
 458         CLK("serial8250.0", NULL, &uart0_clk),
 459         CLK("serial8250.1", NULL, &uart1_clk),
 460         CLK("i2c_davinci.1", NULL, &i2c_clk),
 461         CLK("da830-mmc.0", NULL, &mmcsd0_clk),
 462         CLK("da830-mmc.1", NULL, &mmcsd1_clk),
 463         CLK("spi_davinci.0", NULL, &spi0_clk),
 464         CLK("spi_davinci.1", NULL, &spi1_clk),
 465         CLK("spi_davinci.2", NULL, &spi2_clk),
 466         CLK("spi_davinci.3", NULL, &spi3_clk),
 467         CLK("spi_davinci.4", NULL, &spi4_clk),
 468         CLK(NULL, "gpio", &gpio_clk),
 469         CLK(NULL, "aemif", &aemif_clk),
 470         CLK(NULL, "pwm0", &pwm0_clk),
 471         CLK(NULL, "pwm1", &pwm1_clk),
 472         CLK(NULL, "pwm2", &pwm2_clk),
 473         CLK(NULL, "pwm3", &pwm3_clk),
 474         CLK(NULL, "timer0", &timer0_clk),
 475         CLK(NULL, "timer1", &timer1_clk),
 476         CLK("watchdog", NULL, &timer2_clk),
 477         CLK(NULL, "timer3", &timer3_clk),
 478         CLK(NULL, "usb", &usb_clk),
 479         CLK("davinci_emac.1", NULL, &emac_clk),
 480         CLK("davinci_mdio.0", "fck", &emac_clk),
 481         CLK("davinci_voicecodec", NULL, &voicecodec_clk),
 482         CLK("davinci-mcbsp", NULL, &asp0_clk),
 483         CLK(NULL, "rto", &rto_clk),
 484         CLK(NULL, "mjcp", &mjcp_clk),
 485         CLK(NULL, NULL, NULL),
 486 };
 487
 488 /*----------------------------------------------------------------------*/
 489
 490 #define INTMUX          0x18
 491 #define EVTMUX          0x1c
 492
 493
 494 static const struct mux_config dm365_pins[] = {
 495 #ifdef CONFIG_DAVINCI_MUX
 496 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
 497
 498 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
 499 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
 500 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
 501 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
 502 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
 503 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
 504
 505 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
 506 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
 507
 508 MUX_CFG(DM365,  AEMIF_AR_A14,   2,   0,     3,    1,     false)
 509 MUX_CFG(DM365,  AEMIF_AR_BA0,   2,   0,     3,    2,     false)
 510 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
 511 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
 512 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
 513 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
 514 MUX_CFG(DM365,  AEMIF_CE1,      2,   8,     1,    0,     false)
 515 MUX_CFG(DM365,  AEMIF_WE_OE,    2,   9,     1,    0,     false)
 516
 517 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
 518 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
 519 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
 520 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
 521 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
 522 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
 523
 524 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
 525 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
 526 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
 527 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
 528 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
 529
 530 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
 531 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
 532 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
 533 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
 534 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
 535 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
 536
 537 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
 538 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
 539 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
 540 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
 541 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
 542 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
 543 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
 544 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
 545 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
 546 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
 547 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
 548 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
 549 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
 550 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
 551 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
 552 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
 553 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
 554
 555 MUX_CFG(DM365,  KEYSCAN,        2,   0,     0x3f, 0x3f,  false)
 556
 557 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
 558 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
 559 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
 560 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
 561 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
 562 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
 563 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
 564 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
 565 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
 566 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
 567 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
 568 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
 569
 570 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
 571 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
 572 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
 573 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
 574 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
 575
 576 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
 577 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
 578 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
 579 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
 580 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
 581
 582 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
 583 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
 584 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
 585 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
 586 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
 587
 588 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
 589 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
 590 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
 591 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
 592 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
 593
 594 MUX_CFG(DM365,  CLKOUT0,        4,   20,    3,    3,     false)
 595 MUX_CFG(DM365,  CLKOUT1,        4,   16,    3,    3,     false)
 596 MUX_CFG(DM365,  CLKOUT2,        4,   8,     3,    3,     false)
 597
 598 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
 599 MUX_CFG(DM365,  GPIO30,         4,   6,     3,    0,     false)
 600 MUX_CFG(DM365,  GPIO31,         4,   8,     3,    0,     false)
 601 MUX_CFG(DM365,  GPIO32,         4,   10,    3,    0,     false)
 602 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
 603 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
 604 MUX_CFG(DM365,  GPIO64_57,      2,   6,     1,    0,     false)
 605
 606 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
 607 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
 608 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 609 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 610 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 611 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
 612 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
 613 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
 614 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
 615 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
 616
 617 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
 618 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
 619 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
 620 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
 621 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
 622 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
 623 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
 624 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
 625 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
 626 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
 627 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
 628 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
 629 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
 630 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
 631 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
 632 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
 633 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
 634 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
 635
 636 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
 637 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
 638 EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
 639 EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
 640 #endif
 641 };
 642
 643 static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
 644
 645 static struct davinci_spi_platform_data dm365_spi0_pdata = {
 646         .version        = SPI_VERSION_1,
 647         .num_chipselect = 2,
 648         .dma_event_q    = EVENTQ_3,
 649 };
 650
 651 static struct resource dm365_spi0_resources[] = {
 652         {
 653                 .start = 0x01c66000,
 654                 .end   = 0x01c667ff,
 655                 .flags = IORESOURCE_MEM,
 656         },
 657         {
 658                 .start = IRQ_DM365_SPIINT0_0,
 659                 .flags = IORESOURCE_IRQ,
 660         },
 661         {
 662                 .start = 17,
 663                 .flags = IORESOURCE_DMA,
 664         },
 665         {
 666                 .start = 16,
 667                 .flags = IORESOURCE_DMA,
 668         },
 669 };
 670
 671 static struct platform_device dm365_spi0_device = {
 672         .name = "spi_davinci",
 673         .id = 0,
 674         .dev = {
 675                 .dma_mask = &dm365_spi0_dma_mask,
 676                 .coherent_dma_mask = DMA_BIT_MASK(32),
 677                 .platform_data = &dm365_spi0_pdata,
 678         },
 679         .num_resources = ARRAY_SIZE(dm365_spi0_resources),
 680         .resource = dm365_spi0_resources,
 681 };
 682
 683 void __init dm365_init_spi0(unsigned chipselect_mask,
 684                 const struct spi_board_info *info, unsigned len)
 685 {
 686         davinci_cfg_reg(DM365_SPI0_SCLK);
 687         davinci_cfg_reg(DM365_SPI0_SDI);
 688         davinci_cfg_reg(DM365_SPI0_SDO);
 689
 690         /* not all slaves will be wired up */
 691         if (chipselect_mask & BIT(0))
 692                 davinci_cfg_reg(DM365_SPI0_SDENA0);
 693         if (chipselect_mask & BIT(1))
 694                 davinci_cfg_reg(DM365_SPI0_SDENA1);
 695
 696         spi_register_board_info(info, len);
 697
 698         platform_device_register(&dm365_spi0_device);
 699 }
 700
 701 static struct resource dm365_gpio_resources[] = {
 702         {       /* registers */
 703                 .start  = DAVINCI_GPIO_BASE,
 704                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 705                 .flags  = IORESOURCE_MEM,
 706         },
 707         {       /* interrupt */
 708                 .start  = IRQ_DM365_GPIO0,
 709                 .end    = IRQ_DM365_GPIO7,
 710                 .flags  = IORESOURCE_IRQ,
 711         },
 712 };
 713
 714 static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
 715         .ngpio          = 104,
 716         .intc_irq_num   = DAVINCI_N_AINTC_IRQ,
 717         .gpio_unbanked  = 8,
 718 };
 719
 720 int __init dm365_gpio_register(void)
 721 {
 722         return davinci_gpio_register(dm365_gpio_resources,
 723                                      ARRAY_SIZE(dm365_gpio_resources),
 724                                      &dm365_gpio_platform_data);
 725 }
 726
 727 static struct emac_platform_data dm365_emac_pdata = {
 728         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
 729         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
 730         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
 731         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
 732         .version                = EMAC_VERSION_2,
 733 };
 734
 735 static struct resource dm365_emac_resources[] = {
 736         {
 737                 .start  = DM365_EMAC_BASE,
 738                 .end    = DM365_EMAC_BASE + SZ_16K - 1,
 739                 .flags  = IORESOURCE_MEM,
 740         },
 741         {
 742                 .start  = IRQ_DM365_EMAC_RXTHRESH,
 743                 .end    = IRQ_DM365_EMAC_RXTHRESH,
 744                 .flags  = IORESOURCE_IRQ,
 745         },
 746         {
 747                 .start  = IRQ_DM365_EMAC_RXPULSE,
 748                 .end    = IRQ_DM365_EMAC_RXPULSE,
 749                 .flags  = IORESOURCE_IRQ,
 750         },
 751         {
 752                 .start  = IRQ_DM365_EMAC_TXPULSE,
 753                 .end    = IRQ_DM365_EMAC_TXPULSE,
 754                 .flags  = IORESOURCE_IRQ,
 755         },
 756         {
 757                 .start  = IRQ_DM365_EMAC_MISCPULSE,
 758                 .end    = IRQ_DM365_EMAC_MISCPULSE,
 759                 .flags  = IORESOURCE_IRQ,
 760         },
 761 };
 762
 763 static struct platform_device dm365_emac_device = {
 764         .name           = "davinci_emac",
 765         .id             = 1,
 766         .dev = {
 767                 .platform_data  = &dm365_emac_pdata,
 768         },
 769         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
 770         .resource       = dm365_emac_resources,
 771 };
 772
 773 static struct resource dm365_mdio_resources[] = {
 774         {
 775                 .start  = DM365_EMAC_MDIO_BASE,
 776                 .end    = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
 777                 .flags  = IORESOURCE_MEM,
 778         },
 779 };
 780
 781 static struct platform_device dm365_mdio_device = {
 782         .name           = "davinci_mdio",
 783         .id             = 0,
 784         .num_resources  = ARRAY_SIZE(dm365_mdio_resources),
 785         .resource       = dm365_mdio_resources,
 786 };
 787
 788 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 789         [IRQ_VDINT0]                    = 2,
 790         [IRQ_VDINT1]                    = 6,
 791         [IRQ_VDINT2]                    = 6,
 792         [IRQ_HISTINT]                   = 6,
 793         [IRQ_H3AINT]                    = 6,
 794         [IRQ_PRVUINT]                   = 6,
 795         [IRQ_RSZINT]                    = 6,
 796         [IRQ_DM365_INSFINT]             = 7,
 797         [IRQ_VENCINT]                   = 6,
 798         [IRQ_ASQINT]                    = 6,
 799         [IRQ_IMXINT]                    = 6,
 800         [IRQ_DM365_IMCOPINT]            = 4,
 801         [IRQ_USBINT]                    = 4,
 802         [IRQ_DM365_RTOINT]              = 7,
 803         [IRQ_DM365_TINT5]               = 7,
 804         [IRQ_DM365_TINT6]               = 5,
 805         [IRQ_CCINT0]                    = 5,
 806         [IRQ_CCERRINT]                  = 5,
 807         [IRQ_TCERRINT0]                 = 5,
 808         [IRQ_TCERRINT]                  = 7,
 809         [IRQ_PSCIN]                     = 4,
 810         [IRQ_DM365_SPINT2_1]            = 7,
 811         [IRQ_DM365_TINT7]               = 7,
 812         [IRQ_DM365_SDIOINT0]            = 7,
 813         [IRQ_MBXINT]                    = 7,
 814         [IRQ_MBRINT]                    = 7,
 815         [IRQ_MMCINT]                    = 7,
 816         [IRQ_DM365_MMCINT1]             = 7,
 817         [IRQ_DM365_PWMINT3]             = 7,
 818         [IRQ_AEMIFINT]                  = 2,
 819         [IRQ_DM365_SDIOINT1]            = 2,
 820         [IRQ_TINT0_TINT12]              = 7,
 821         [IRQ_TINT0_TINT34]              = 7,
 822         [IRQ_TINT1_TINT12]              = 7,
 823         [IRQ_TINT1_TINT34]              = 7,
 824         [IRQ_PWMINT0]                   = 7,
 825         [IRQ_PWMINT1]                   = 3,
 826         [IRQ_PWMINT2]                   = 3,
 827         [IRQ_I2C]                       = 3,
 828         [IRQ_UARTINT0]                  = 3,
 829         [IRQ_UARTINT1]                  = 3,
 830         [IRQ_DM365_RTCINT]              = 3,
 831         [IRQ_DM365_SPIINT0_0]           = 3,
 832         [IRQ_DM365_SPIINT3_0]           = 3,
 833         [IRQ_DM365_GPIO0]               = 3,
 834         [IRQ_DM365_GPIO1]               = 7,
 835         [IRQ_DM365_GPIO2]               = 4,
 836         [IRQ_DM365_GPIO3]               = 4,
 837         [IRQ_DM365_GPIO4]               = 7,
 838         [IRQ_DM365_GPIO5]               = 7,
 839         [IRQ_DM365_GPIO6]               = 7,
 840         [IRQ_DM365_GPIO7]               = 7,
 841         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
 842         [IRQ_DM365_EMAC_RXPULSE]        = 7,
 843         [IRQ_DM365_EMAC_TXPULSE]        = 7,
 844         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
 845         [IRQ_DM365_GPIO12]              = 7,
 846         [IRQ_DM365_GPIO13]              = 7,
 847         [IRQ_DM365_GPIO14]              = 7,
 848         [IRQ_DM365_GPIO15]              = 7,
 849         [IRQ_DM365_KEYINT]              = 7,
 850         [IRQ_DM365_TCERRINT2]           = 7,
 851         [IRQ_DM365_TCERRINT3]           = 7,
 852         [IRQ_DM365_EMUINT]              = 7,
 853 };
 854
 855 /* Four Transfer Controllers on DM365 */
 856 static s8
 857 dm365_queue_tc_mapping[][2] = {
 858         /* {event queue no, TC no} */
 859         {0, 0},
 860         {1, 1},
 861         {2, 2},
 862         {3, 3},
 863         {-1, -1},
 864 };
 865
 866 static s8
 867 dm365_queue_priority_mapping[][2] = {
 868         /* {event queue no, Priority} */
 869         {0, 7},
 870         {1, 7},
 871         {2, 7},
 872         {3, 0},
 873         {-1, -1},
 874 };
 875
 876 static struct edma_soc_info edma_cc0_info = {
 877         .n_channel              = 64,
 878         .n_region               = 4,
 879         .n_slot                 = 256,
 880         .n_tc                   = 4,
 881         .n_cc                   = 1,
 882         .queue_tc_mapping       = dm365_queue_tc_mapping,
 883         .queue_priority_mapping = dm365_queue_priority_mapping,
 884         .default_queue          = EVENTQ_3,
 885 };
 886
 887 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
 888         &edma_cc0_info,
 889 };
 890
 891 static struct resource edma_resources[] = {
 892         {
 893                 .name   = "edma_cc0",
 894                 .start  = 0x01c00000,
 895                 .end    = 0x01c00000 + SZ_64K - 1,
 896                 .flags  = IORESOURCE_MEM,
 897         },
 898         {
 899                 .name   = "edma_tc0",
 900                 .start  = 0x01c10000,
 901                 .end    = 0x01c10000 + SZ_1K - 1,
 902                 .flags  = IORESOURCE_MEM,
 903         },
 904         {
 905                 .name   = "edma_tc1",
 906                 .start  = 0x01c10400,
 907                 .end    = 0x01c10400 + SZ_1K - 1,
 908                 .flags  = IORESOURCE_MEM,
 909         },
 910         {
 911                 .name   = "edma_tc2",
 912                 .start  = 0x01c10800,
 913                 .end    = 0x01c10800 + SZ_1K - 1,
 914                 .flags  = IORESOURCE_MEM,
 915         },
 916         {
 917                 .name   = "edma_tc3",
 918                 .start  = 0x01c10c00,
 919                 .end    = 0x01c10c00 + SZ_1K - 1,
 920                 .flags  = IORESOURCE_MEM,
 921         },
 922         {
 923                 .name   = "edma0",
 924                 .start  = IRQ_CCINT0,
 925                 .flags  = IORESOURCE_IRQ,
 926         },
 927         {
 928                 .name   = "edma0_err",
 929                 .start  = IRQ_CCERRINT,
 930                 .flags  = IORESOURCE_IRQ,
 931         },
 932         /* not using TC*_ERR */
 933 };
 934
 935 static struct platform_device dm365_edma_device = {
 936         .name                   = "edma",
 937         .id                     = 0,
 938         .dev.platform_data      = dm365_edma_info,
 939         .num_resources          = ARRAY_SIZE(edma_resources),
 940         .resource               = edma_resources,
 941 };
 942
 943 static struct resource dm365_asp_resources[] = {
 944         {
 945                 .name   = "mpu",
 946                 .start  = DAVINCI_DM365_ASP0_BASE,
 947                 .end    = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
 948                 .flags  = IORESOURCE_MEM,
 949         },
 950         {
 951                 .start  = DAVINCI_DMA_ASP0_TX,
 952                 .end    = DAVINCI_DMA_ASP0_TX,
 953                 .flags  = IORESOURCE_DMA,
 954         },
 955         {
 956                 .start  = DAVINCI_DMA_ASP0_RX,
 957                 .end    = DAVINCI_DMA_ASP0_RX,
 958                 .flags  = IORESOURCE_DMA,
 959         },
 960 };
 961
 962 static struct platform_device dm365_asp_device = {
 963         .name           = "davinci-mcbsp",
 964         .id             = -1,
 965         .num_resources  = ARRAY_SIZE(dm365_asp_resources),
 966         .resource       = dm365_asp_resources,
 967 };
 968
 969 static struct resource dm365_vc_resources[] = {
 970         {
 971                 .start  = DAVINCI_DM365_VC_BASE,
 972                 .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
 973                 .flags  = IORESOURCE_MEM,
 974         },
 975         {
 976                 .start  = DAVINCI_DMA_VC_TX,
 977                 .end    = DAVINCI_DMA_VC_TX,
 978                 .flags  = IORESOURCE_DMA,
 979         },
 980         {
 981                 .start  = DAVINCI_DMA_VC_RX,
 982                 .end    = DAVINCI_DMA_VC_RX,
 983                 .flags  = IORESOURCE_DMA,
 984         },
 985 };
 986
 987 static struct platform_device dm365_vc_device = {
 988         .name           = "davinci_voicecodec",
 989         .id             = -1,
 990         .num_resources  = ARRAY_SIZE(dm365_vc_resources),
 991         .resource       = dm365_vc_resources,
 992 };
 993
 994 static struct resource dm365_rtc_resources[] = {
 995         {
 996                 .start = DM365_RTC_BASE,
 997                 .end = DM365_RTC_BASE + SZ_1K - 1,
 998                 .flags = IORESOURCE_MEM,
 999         },
1000         {
1001                 .start = IRQ_DM365_RTCINT,
1002                 .flags = IORESOURCE_IRQ,
1003         },
1004 };
1005
1006 static struct platform_device dm365_rtc_device = {
1007         .name = "rtc_davinci",
1008         .id = 0,
1009         .num_resources = ARRAY_SIZE(dm365_rtc_resources),
1010         .resource = dm365_rtc_resources,
1011 };
1012
1013 static struct map_desc dm365_io_desc[] = {
1014         {
1015                 .virtual        = IO_VIRT,
1016                 .pfn            = __phys_to_pfn(IO_PHYS),
1017                 .length         = IO_SIZE,
1018                 .type           = MT_DEVICE
1019         },
1020 };
1021
1022 static struct resource dm365_ks_resources[] = {
1023         {
1024                 /* registers */
1025                 .start = DM365_KEYSCAN_BASE,
1026                 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
1027                 .flags = IORESOURCE_MEM,
1028         },
1029         {
1030                 /* interrupt */
1031                 .start = IRQ_DM365_KEYINT,
1032                 .end = IRQ_DM365_KEYINT,
1033                 .flags = IORESOURCE_IRQ,
1034         },
1035 };
1036
1037 static struct platform_device dm365_ks_device = {
1038         .name           = "davinci_keyscan",
1039         .id             = 0,
1040         .num_resources  = ARRAY_SIZE(dm365_ks_resources),
1041         .resource       = dm365_ks_resources,
1042 };
1043
1044 /* Contents of JTAG ID register used to identify exact cpu type */
1045 static struct davinci_id dm365_ids[] = {
1046         {
1047                 .variant        = 0x0,
1048                 .part_no        = 0xb83e,
1049                 .manufacturer   = 0x017,
1050                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1051                 .name           = "dm365_rev1.1",
1052         },
1053         {
1054                 .variant        = 0x8,
1055                 .part_no        = 0xb83e,
1056                 .manufacturer   = 0x017,
1057                 .cpu_id         = DAVINCI_CPU_ID_DM365,
1058                 .name           = "dm365_rev1.2",
1059         },
1060 };
1061
1062 static u32 dm365_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
1063
1064 static struct davinci_timer_info dm365_timer_info = {
1065         .timers         = davinci_timer_instance,
1066         .clockevent_id  = T0_BOT,
1067         .clocksource_id = T0_TOP,
1068 };
1069
1070 #define DM365_UART1_BASE        (IO_PHYS + 0x106000)
1071
1072 static struct plat_serial8250_port dm365_serial0_platform_data[] = {
1073         {
1074                 .mapbase        = DAVINCI_UART0_BASE,
1075                 .irq            = IRQ_UARTINT0,
1076                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1077                                   UPF_IOREMAP,
1078                 .iotype         = UPIO_MEM,
1079                 .regshift       = 2,
1080         },
1081         {
1082                 .flags  = 0,
1083         }
1084 };
1085 static struct plat_serial8250_port dm365_serial1_platform_data[] = {
1086         {
1087                 .mapbase        = DM365_UART1_BASE,
1088                 .irq            = IRQ_UARTINT1,
1089                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
1090                                   UPF_IOREMAP,
1091                 .iotype         = UPIO_MEM,
1092                 .regshift       = 2,
1093         },
1094         {
1095                 .flags  = 0,
1096         }
1097 };
1098
1099 struct platform_device dm365_serial_device[] = {
1100         {
1101                 .name                   = "serial8250",
1102                 .id                     = PLAT8250_DEV_PLATFORM,
1103                 .dev                    = {
1104                         .platform_data  = dm365_serial0_platform_data,
1105                 }
1106         },
1107         {
1108                 .name                   = "serial8250",
1109                 .id                     = PLAT8250_DEV_PLATFORM1,
1110                 .dev                    = {
1111                         .platform_data  = dm365_serial1_platform_data,
1112                 }
1113         },
1114         {
1115         }
1116 };
1117
1118 static struct davinci_soc_info davinci_soc_info_dm365 = {
1119         .io_desc                = dm365_io_desc,
1120         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
1121         .jtag_id_reg            = 0x01c40028,
1122         .ids                    = dm365_ids,
1123         .ids_num                = ARRAY_SIZE(dm365_ids),
1124         .cpu_clks               = dm365_clks,
1125         .psc_bases              = dm365_psc_bases,
1126         .psc_bases_num          = ARRAY_SIZE(dm365_psc_bases),
1127         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
1128         .pinmux_pins            = dm365_pins,
1129         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
1130         .intc_base              = DAVINCI_ARM_INTC_BASE,
1131         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
1132         .intc_irq_prios         = dm365_default_priorities,
1133         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
1134         .timer_info             = &dm365_timer_info,
1135         .emac_pdata             = &dm365_emac_pdata,
1136         .sram_dma               = 0x00010000,
1137         .sram_len               = SZ_32K,
1138 };
1139
1140 void __init dm365_init_asp(struct snd_platform_data *pdata)
1141 {
1142         davinci_cfg_reg(DM365_MCBSP0_BDX);
1143         davinci_cfg_reg(DM365_MCBSP0_X);
1144         davinci_cfg_reg(DM365_MCBSP0_BFSX);
1145         davinci_cfg_reg(DM365_MCBSP0_BDR);
1146         davinci_cfg_reg(DM365_MCBSP0_R);
1147         davinci_cfg_reg(DM365_MCBSP0_BFSR);
1148         davinci_cfg_reg(DM365_EVT2_ASP_TX);
1149         davinci_cfg_reg(DM365_EVT3_ASP_RX);
1150         dm365_asp_device.dev.platform_data = pdata;
1151         platform_device_register(&dm365_asp_device);
1152 }
1153
1154 void __init dm365_init_vc(struct snd_platform_data *pdata)
1155 {
1156         davinci_cfg_reg(DM365_EVT2_VC_TX);
1157         davinci_cfg_reg(DM365_EVT3_VC_RX);
1158         dm365_vc_device.dev.platform_data = pdata;
1159         platform_device_register(&dm365_vc_device);
1160 }
1161
1162 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
1163 {
1164         dm365_ks_device.dev.platform_data = pdata;
1165         platform_device_register(&dm365_ks_device);
1166 }
1167
1168 void __init dm365_init_rtc(void)
1169 {
1170         davinci_cfg_reg(DM365_INT_PRTCSS);
1171         platform_device_register(&dm365_rtc_device);
1172 }
1173
1174 void __init dm365_init(void)
1175 {
1176         davinci_common_init(&davinci_soc_info_dm365);
1177         davinci_map_sysmod();
1178 }
1179
1180 static struct resource dm365_vpss_resources[] = {
1181         {
1182                 /* VPSS ISP5 Base address */
1183                 .name           = "isp5",
1184                 .start          = 0x01c70000,
1185                 .end            = 0x01c70000 + 0xff,
1186                 .flags          = IORESOURCE_MEM,
1187         },
1188         {
1189                 /* VPSS CLK Base address */
1190                 .name           = "vpss",
1191                 .start          = 0x01c70200,
1192                 .end            = 0x01c70200 + 0xff,
1193                 .flags          = IORESOURCE_MEM,
1194         },
1195 };
1196
1197 static struct platform_device dm365_vpss_device = {
1198        .name                   = "vpss",
1199        .id                     = -1,
1200        .dev.platform_data      = "dm365_vpss",
1201        .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
1202        .resource               = dm365_vpss_resources,
1203 };
1204
1205 static struct resource vpfe_resources[] = {
1206         {
1207                 .start          = IRQ_VDINT0,
1208                 .end            = IRQ_VDINT0,
1209                 .flags          = IORESOURCE_IRQ,
1210         },
1211         {
1212                 .start          = IRQ_VDINT1,
1213                 .end            = IRQ_VDINT1,
1214                 .flags          = IORESOURCE_IRQ,
1215         },
1216 };
1217
1218 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
1219 static struct platform_device vpfe_capture_dev = {
1220         .name           = CAPTURE_DRV_NAME,
1221         .id             = -1,
1222         .num_resources  = ARRAY_SIZE(vpfe_resources),
1223         .resource       = vpfe_resources,
1224         .dev = {
1225                 .dma_mask               = &vpfe_capture_dma_mask,
1226                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1227         },
1228 };
1229
1230 static void dm365_isif_setup_pinmux(void)
1231 {
1232         davinci_cfg_reg(DM365_VIN_CAM_WEN);
1233         davinci_cfg_reg(DM365_VIN_CAM_VD);
1234         davinci_cfg_reg(DM365_VIN_CAM_HD);
1235         davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
1236         davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
1237 }
1238
1239 static struct resource isif_resource[] = {
1240         /* ISIF Base address */
1241         {
1242                 .start          = 0x01c71000,
1243                 .end            = 0x01c71000 + 0x1ff,
1244                 .flags          = IORESOURCE_MEM,
1245         },
1246         /* ISIF Linearization table 0 */
1247         {
1248                 .start          = 0x1C7C000,
1249                 .end            = 0x1C7C000 + 0x2ff,
1250                 .flags          = IORESOURCE_MEM,
1251         },
1252         /* ISIF Linearization table 1 */
1253         {
1254                 .start          = 0x1C7C400,
1255                 .end            = 0x1C7C400 + 0x2ff,
1256                 .flags          = IORESOURCE_MEM,
1257         },
1258 };
1259 static struct platform_device dm365_isif_dev = {
1260         .name           = "isif",
1261         .id             = -1,
1262         .num_resources  = ARRAY_SIZE(isif_resource),
1263         .resource       = isif_resource,
1264         .dev = {
1265                 .dma_mask               = &vpfe_capture_dma_mask,
1266                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1267                 .platform_data          = dm365_isif_setup_pinmux,
1268         },
1269 };
1270
1271 static struct resource dm365_osd_resources[] = {
1272         {
1273                 .start = DM365_OSD_BASE,
1274                 .end   = DM365_OSD_BASE + 0xff,
1275                 .flags = IORESOURCE_MEM,
1276         },
1277 };
1278
1279 static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
1280
1281 static struct platform_device dm365_osd_dev = {
1282         .name           = DM365_VPBE_OSD_SUBDEV_NAME,
1283         .id             = -1,
1284         .num_resources  = ARRAY_SIZE(dm365_osd_resources),
1285         .resource       = dm365_osd_resources,
1286         .dev            = {
1287                 .dma_mask               = &dm365_video_dma_mask,
1288                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1289         },
1290 };
1291
1292 static struct resource dm365_venc_resources[] = {
1293         {
1294                 .start = IRQ_VENCINT,
1295                 .end   = IRQ_VENCINT,
1296                 .flags = IORESOURCE_IRQ,
1297         },
1298         /* venc registers io space */
1299         {
1300                 .start = DM365_VENC_BASE,
1301                 .end   = DM365_VENC_BASE + 0x177,
1302                 .flags = IORESOURCE_MEM,
1303         },
1304         /* vdaccfg registers io space */
1305         {
1306                 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
1307                 .end   = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
1308                 .flags = IORESOURCE_MEM,
1309         },
1310 };
1311
1312 static struct resource dm365_v4l2_disp_resources[] = {
1313         {
1314                 .start = IRQ_VENCINT,
1315                 .end   = IRQ_VENCINT,
1316                 .flags = IORESOURCE_IRQ,
1317         },
1318         /* venc registers io space */
1319         {
1320                 .start = DM365_VENC_BASE,
1321                 .end   = DM365_VENC_BASE + 0x177,
1322                 .flags = IORESOURCE_MEM,
1323         },
1324 };
1325
1326 static int dm365_vpbe_setup_pinmux(enum v4l2_mbus_pixelcode if_type,
1327                             int field)
1328 {
1329         switch (if_type) {
1330         case V4L2_MBUS_FMT_SGRBG8_1X8:
1331                 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1332                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1333                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1334                 break;
1335         case V4L2_MBUS_FMT_YUYV10_1X20:
1336                 if (field)
1337                         davinci_cfg_reg(DM365_VOUT_FIELD);
1338                 else
1339                         davinci_cfg_reg(DM365_VOUT_FIELD_G81);
1340                 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
1341                 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
1342                 break;
1343         default:
1344                 return -EINVAL;
1345         }
1346
1347         return 0;
1348 }
1349
1350 static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
1351                                   unsigned int pclock)
1352 {
1353         void __iomem *vpss_clkctl_reg;
1354         u32 val;
1355
1356         vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
1357
1358         switch (type) {
1359         case VPBE_ENC_STD:
1360                 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1361                 break;
1362         case VPBE_ENC_DV_TIMINGS:
1363                 if (pclock <= 27000000) {
1364                         val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
1365                 } else {
1366                         /* set sysclk4 to output 74.25 MHz from pll1 */
1367                         val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
1368                               VPSS_VENCCLKEN_ENABLE;
1369                 }
1370                 break;
1371         default:
1372                 return -EINVAL;
1373         }
1374         writel(val, vpss_clkctl_reg);
1375
1376         return 0;
1377 }
1378
1379 static struct platform_device dm365_vpbe_display = {
1380         .name           = "vpbe-v4l2",
1381         .id             = -1,
1382         .num_resources  = ARRAY_SIZE(dm365_v4l2_disp_resources),
1383         .resource       = dm365_v4l2_disp_resources,
1384         .dev            = {
1385                 .dma_mask               = &dm365_video_dma_mask,
1386                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1387         },
1388 };
1389
1390 static struct venc_platform_data dm365_venc_pdata = {
1391         .setup_pinmux   = dm365_vpbe_setup_pinmux,
1392         .setup_clock    = dm365_venc_setup_clock,
1393 };
1394
1395 static struct platform_device dm365_venc_dev = {
1396         .name           = DM365_VPBE_VENC_SUBDEV_NAME,
1397         .id             = -1,
1398         .num_resources  = ARRAY_SIZE(dm365_venc_resources),
1399         .resource       = dm365_venc_resources,
1400         .dev            = {
1401                 .dma_mask               = &dm365_video_dma_mask,
1402                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1403                 .platform_data          = (void *)&dm365_venc_pdata,
1404         },
1405 };
1406
1407 static struct platform_device dm365_vpbe_dev = {
1408         .name           = "vpbe_controller",
1409         .id             = -1,
1410         .dev            = {
1411                 .dma_mask               = &dm365_video_dma_mask,
1412                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1413         },
1414 };
1415
1416 int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1417                                 struct vpbe_config *vpbe_cfg)
1418 {
1419         if (vpfe_cfg || vpbe_cfg)
1420                 platform_device_register(&dm365_vpss_device);
1421
1422         if (vpfe_cfg) {
1423                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1424                 platform_device_register(&dm365_isif_dev);
1425                 platform_device_register(&vpfe_capture_dev);
1426         }
1427         if (vpbe_cfg) {
1428                 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1429                 platform_device_register(&dm365_osd_dev);
1430                 platform_device_register(&dm365_venc_dev);
1431                 platform_device_register(&dm365_vpbe_dev);
1432                 platform_device_register(&dm365_vpbe_display);
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int __init dm365_init_devices(void)
1439 {
1440         if (!cpu_is_davinci_dm365())
1441                 return 0;
1442
1443         davinci_cfg_reg(DM365_INT_EDMA_CC);
1444         platform_device_register(&dm365_edma_device);
1445
1446         platform_device_register(&dm365_mdio_device);
1447         platform_device_register(&dm365_emac_device);
1448
1449         return 0;
1450 }
1451 postcore_initcall(dm365_init_devices);