arch/arm/mach-at91/at91sam9261.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9261.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91sam9261.h>
  22 #include <mach/at91_pmc.h>
  23
  24 #include "at91_aic.h"
  25 #include "at91_rstc.h"
  26 #include "soc.h"
  27 #include "generic.h"
  28 #include "clock.h"
  29 #include "sam9_smc.h"
  30 #include "pm.h"
  31
  32 /* --------------------------------------------------------------------
  33  *  Clocks
  34  * -------------------------------------------------------------------- */
  35
  36 /*
  37  * The peripheral clocks.
  38  */
  39 static struct clk pioA_clk = {
  40         .name           = "pioA_clk",
  41         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
  42         .type           = CLK_TYPE_PERIPHERAL,
  43 };
  44 static struct clk pioB_clk = {
  45         .name           = "pioB_clk",
  46         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
  47         .type           = CLK_TYPE_PERIPHERAL,
  48 };
  49 static struct clk pioC_clk = {
  50         .name           = "pioC_clk",
  51         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
  52         .type           = CLK_TYPE_PERIPHERAL,
  53 };
  54 static struct clk usart0_clk = {
  55         .name           = "usart0_clk",
  56         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
  57         .type           = CLK_TYPE_PERIPHERAL,
  58 };
  59 static struct clk usart1_clk = {
  60         .name           = "usart1_clk",
  61         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
  62         .type           = CLK_TYPE_PERIPHERAL,
  63 };
  64 static struct clk usart2_clk = {
  65         .name           = "usart2_clk",
  66         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
  67         .type           = CLK_TYPE_PERIPHERAL,
  68 };
  69 static struct clk mmc_clk = {
  70         .name           = "mci_clk",
  71         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
  72         .type           = CLK_TYPE_PERIPHERAL,
  73 };
  74 static struct clk udc_clk = {
  75         .name           = "udc_clk",
  76         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
  77         .type           = CLK_TYPE_PERIPHERAL,
  78 };
  79 static struct clk twi_clk = {
  80         .name           = "twi_clk",
  81         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
  82         .type           = CLK_TYPE_PERIPHERAL,
  83 };
  84 static struct clk spi0_clk = {
  85         .name           = "spi0_clk",
  86         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
  87         .type           = CLK_TYPE_PERIPHERAL,
  88 };
  89 static struct clk spi1_clk = {
  90         .name           = "spi1_clk",
  91         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
  92         .type           = CLK_TYPE_PERIPHERAL,
  93 };
  94 static struct clk ssc0_clk = {
  95         .name           = "ssc0_clk",
  96         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
  97         .type           = CLK_TYPE_PERIPHERAL,
  98 };
  99 static struct clk ssc1_clk = {
 100         .name           = "ssc1_clk",
 101         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
 102         .type           = CLK_TYPE_PERIPHERAL,
 103 };
 104 static struct clk ssc2_clk = {
 105         .name           = "ssc2_clk",
 106         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
 107         .type           = CLK_TYPE_PERIPHERAL,
 108 };
 109 static struct clk tc0_clk = {
 110         .name           = "tc0_clk",
 111         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
 112         .type           = CLK_TYPE_PERIPHERAL,
 113 };
 114 static struct clk tc1_clk = {
 115         .name           = "tc1_clk",
 116         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
 117         .type           = CLK_TYPE_PERIPHERAL,
 118 };
 119 static struct clk tc2_clk = {
 120         .name           = "tc2_clk",
 121         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
 122         .type           = CLK_TYPE_PERIPHERAL,
 123 };
 124 static struct clk ohci_clk = {
 125         .name           = "ohci_clk",
 126         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
 127         .type           = CLK_TYPE_PERIPHERAL,
 128 };
 129 static struct clk lcdc_clk = {
 130         .name           = "lcdc_clk",
 131         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
 132         .type           = CLK_TYPE_PERIPHERAL,
 133 };
 134
 135 /* HClocks */
 136 static struct clk hck0 = {
 137         .name           = "hck0",
 138         .pmc_mask       = AT91_PMC_HCK0,
 139         .type           = CLK_TYPE_SYSTEM,
 140         .id             = 0,
 141 };
 142 static struct clk hck1 = {
 143         .name           = "hck1",
 144         .pmc_mask       = AT91_PMC_HCK1,
 145         .type           = CLK_TYPE_SYSTEM,
 146         .id             = 1,
 147 };
 148
 149 static struct clk *periph_clocks[] __initdata = {
 150         &pioA_clk,
 151         &pioB_clk,
 152         &pioC_clk,
 153         &usart0_clk,
 154         &usart1_clk,
 155         &usart2_clk,
 156         &mmc_clk,
 157         &udc_clk,
 158         &twi_clk,
 159         &spi0_clk,
 160         &spi1_clk,
 161         &ssc0_clk,
 162         &ssc1_clk,
 163         &ssc2_clk,
 164         &tc0_clk,
 165         &tc1_clk,
 166         &tc2_clk,
 167         &ohci_clk,
 168         &lcdc_clk,
 169         // irq0 .. irq2
 170 };
 171
 172 static struct clk_lookup periph_clocks_lookups[] = {
 173         CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
 174         CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
 175         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 176         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 177         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 178         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 179         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 180         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
 181         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
 182         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
 183         CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
 184         CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
 185         CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
 186         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
 187         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
 188         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
 189         CLKDEV_CON_ID("pioA", &pioA_clk),
 190         CLKDEV_CON_ID("pioB", &pioB_clk),
 191         CLKDEV_CON_ID("pioC", &pioC_clk),
 192 };
 193
 194 static struct clk_lookup usart_clocks_lookups[] = {
 195         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 196         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 197         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 198         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 199 };
 200
 201 /*
 202  * The four programmable clocks.
 203  * You must configure pin multiplexing to bring these signals out.
 204  */
 205 static struct clk pck0 = {
 206         .name           = "pck0",
 207         .pmc_mask       = AT91_PMC_PCK0,
 208         .type           = CLK_TYPE_PROGRAMMABLE,
 209         .id             = 0,
 210 };
 211 static struct clk pck1 = {
 212         .name           = "pck1",
 213         .pmc_mask       = AT91_PMC_PCK1,
 214         .type           = CLK_TYPE_PROGRAMMABLE,
 215         .id             = 1,
 216 };
 217 static struct clk pck2 = {
 218         .name           = "pck2",
 219         .pmc_mask       = AT91_PMC_PCK2,
 220         .type           = CLK_TYPE_PROGRAMMABLE,
 221         .id             = 2,
 222 };
 223 static struct clk pck3 = {
 224         .name           = "pck3",
 225         .pmc_mask       = AT91_PMC_PCK3,
 226         .type           = CLK_TYPE_PROGRAMMABLE,
 227         .id             = 3,
 228 };
 229
 230 static void __init at91sam9261_register_clocks(void)
 231 {
 232         int i;
 233
 234         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 235                 clk_register(periph_clocks[i]);
 236
 237         clkdev_add_table(periph_clocks_lookups,
 238                          ARRAY_SIZE(periph_clocks_lookups));
 239         clkdev_add_table(usart_clocks_lookups,
 240                          ARRAY_SIZE(usart_clocks_lookups));
 241
 242         clk_register(&pck0);
 243         clk_register(&pck1);
 244         clk_register(&pck2);
 245         clk_register(&pck3);
 246
 247         clk_register(&hck0);
 248         clk_register(&hck1);
 249 }
 250
 251 /* --------------------------------------------------------------------
 252  *  GPIO
 253  * -------------------------------------------------------------------- */
 254
 255 static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
 256         {
 257                 .id             = AT91SAM9261_ID_PIOA,
 258                 .regbase        = AT91SAM9261_BASE_PIOA,
 259         }, {
 260                 .id             = AT91SAM9261_ID_PIOB,
 261                 .regbase        = AT91SAM9261_BASE_PIOB,
 262         }, {
 263                 .id             = AT91SAM9261_ID_PIOC,
 264                 .regbase        = AT91SAM9261_BASE_PIOC,
 265         }
 266 };
 267
 268 /* --------------------------------------------------------------------
 269  *  AT91SAM9261 processor initialization
 270  * -------------------------------------------------------------------- */
 271
 272 static void __init at91sam9261_map_io(void)
 273 {
 274         if (cpu_is_at91sam9g10())
 275                 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
 276         else
 277                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 278 }
 279
 280 static void __init at91sam9261_ioremap_registers(void)
 281 {
 282         at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
 283         at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
 284         at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
 285         at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
 286         at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
 287         at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
 288         at91_pm_set_standby(at91sam9_sdram_standby);
 289 }
 290
 291 static void __init at91sam9261_initialize(void)
 292 {
 293         arm_pm_idle = at91sam9_idle;
 294         arm_pm_restart = at91sam9_alt_restart;
 295
 296         at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
 297
 298         /* Register GPIO subsystem */
 299         at91_gpio_init(at91sam9261_gpio, 3);
 300 }
 301
 302 /* --------------------------------------------------------------------
 303  *  Interrupt initialization
 304  * -------------------------------------------------------------------- */
 305
 306 /*
 307  * The default interrupt priority levels (0 = lowest, 7 = highest).
 308  */
 309 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 310         7,      /* Advanced Interrupt Controller */
 311         7,      /* System Peripherals */
 312         1,      /* Parallel IO Controller A */
 313         1,      /* Parallel IO Controller B */
 314         1,      /* Parallel IO Controller C */
 315         0,
 316         5,      /* USART 0 */
 317         5,      /* USART 1 */
 318         5,      /* USART 2 */
 319         0,      /* Multimedia Card Interface */
 320         2,      /* USB Device Port */
 321         6,      /* Two-Wire Interface */
 322         5,      /* Serial Peripheral Interface 0 */
 323         5,      /* Serial Peripheral Interface 1 */
 324         4,      /* Serial Synchronous Controller 0 */
 325         4,      /* Serial Synchronous Controller 1 */
 326         4,      /* Serial Synchronous Controller 2 */
 327         0,      /* Timer Counter 0 */
 328         0,      /* Timer Counter 1 */
 329         0,      /* Timer Counter 2 */
 330         2,      /* USB Host port */
 331         3,      /* LCD Controller */
 332         0,
 333         0,
 334         0,
 335         0,
 336         0,
 337         0,
 338         0,
 339         0,      /* Advanced Interrupt Controller */
 340         0,      /* Advanced Interrupt Controller */
 341         0,      /* Advanced Interrupt Controller */
 342 };
 343
 344 AT91_SOC_START(at91sam9261)
 345         .map_io = at91sam9261_map_io,
 346         .default_irq_priority = at91sam9261_default_irq_priority,
 347         .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
 348                     | (1 << AT91SAM9261_ID_IRQ2),
 349         .ioremap_registers = at91sam9261_ioremap_registers,
 350         .register_clocks = at91sam9261_register_clocks,
 351         .init = at91sam9261_initialize,
 352 AT91_SOC_END