arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91_dbgu.h>
  22 #include <mach/at91sam9260.h>
  23 #include <mach/at91_pmc.h>
  24
  25 #include "at91_aic.h"
  26 #include "at91_rstc.h"
  27 #include "soc.h"
  28 #include "generic.h"
  29 #include "clock.h"
  30 #include "sam9_smc.h"
  31 #include "pm.h"
  32
  33 /* --------------------------------------------------------------------
  34  *  Clocks
  35  * -------------------------------------------------------------------- */
  36
  37 /*
  38  * The peripheral clocks.
  39  */
  40 static struct clk pioA_clk = {
  41         .name           = "pioA_clk",
  42         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  43         .type           = CLK_TYPE_PERIPHERAL,
  44 };
  45 static struct clk pioB_clk = {
  46         .name           = "pioB_clk",
  47         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  48         .type           = CLK_TYPE_PERIPHERAL,
  49 };
  50 static struct clk pioC_clk = {
  51         .name           = "pioC_clk",
  52         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk adc_clk = {
  56         .name           = "adc_clk",
  57         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60
  61 static struct clk adc_op_clk = {
  62         .name           = "adc_op_clk",
  63         .type           = CLK_TYPE_PERIPHERAL,
  64         .rate_hz        = 5000000,
  65 };
  66
  67 static struct clk usart0_clk = {
  68         .name           = "usart0_clk",
  69         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  70         .type           = CLK_TYPE_PERIPHERAL,
  71 };
  72 static struct clk usart1_clk = {
  73         .name           = "usart1_clk",
  74         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
  75         .type           = CLK_TYPE_PERIPHERAL,
  76 };
  77 static struct clk usart2_clk = {
  78         .name           = "usart2_clk",
  79         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
  80         .type           = CLK_TYPE_PERIPHERAL,
  81 };
  82 static struct clk mmc_clk = {
  83         .name           = "mci_clk",
  84         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
  85         .type           = CLK_TYPE_PERIPHERAL,
  86 };
  87 static struct clk udc_clk = {
  88         .name           = "udc_clk",
  89         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
  90         .type           = CLK_TYPE_PERIPHERAL,
  91 };
  92 static struct clk twi_clk = {
  93         .name           = "twi_clk",
  94         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
  95         .type           = CLK_TYPE_PERIPHERAL,
  96 };
  97 static struct clk spi0_clk = {
  98         .name           = "spi0_clk",
  99         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
 100         .type           = CLK_TYPE_PERIPHERAL,
 101 };
 102 static struct clk spi1_clk = {
 103         .name           = "spi1_clk",
 104         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 105         .type           = CLK_TYPE_PERIPHERAL,
 106 };
 107 static struct clk ssc_clk = {
 108         .name           = "ssc_clk",
 109         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 110         .type           = CLK_TYPE_PERIPHERAL,
 111 };
 112 static struct clk tc0_clk = {
 113         .name           = "tc0_clk",
 114         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 115         .type           = CLK_TYPE_PERIPHERAL,
 116 };
 117 static struct clk tc1_clk = {
 118         .name           = "tc1_clk",
 119         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 120         .type           = CLK_TYPE_PERIPHERAL,
 121 };
 122 static struct clk tc2_clk = {
 123         .name           = "tc2_clk",
 124         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 125         .type           = CLK_TYPE_PERIPHERAL,
 126 };
 127 static struct clk ohci_clk = {
 128         .name           = "ohci_clk",
 129         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 130         .type           = CLK_TYPE_PERIPHERAL,
 131 };
 132 static struct clk macb_clk = {
 133         .name           = "pclk",
 134         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 135         .type           = CLK_TYPE_PERIPHERAL,
 136 };
 137 static struct clk isi_clk = {
 138         .name           = "isi_clk",
 139         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 140         .type           = CLK_TYPE_PERIPHERAL,
 141 };
 142 static struct clk usart3_clk = {
 143         .name           = "usart3_clk",
 144         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 145         .type           = CLK_TYPE_PERIPHERAL,
 146 };
 147 static struct clk usart4_clk = {
 148         .name           = "usart4_clk",
 149         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 150         .type           = CLK_TYPE_PERIPHERAL,
 151 };
 152 static struct clk usart5_clk = {
 153         .name           = "usart5_clk",
 154         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 155         .type           = CLK_TYPE_PERIPHERAL,
 156 };
 157 static struct clk tc3_clk = {
 158         .name           = "tc3_clk",
 159         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 160         .type           = CLK_TYPE_PERIPHERAL,
 161 };
 162 static struct clk tc4_clk = {
 163         .name           = "tc4_clk",
 164         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 165         .type           = CLK_TYPE_PERIPHERAL,
 166 };
 167 static struct clk tc5_clk = {
 168         .name           = "tc5_clk",
 169         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 170         .type           = CLK_TYPE_PERIPHERAL,
 171 };
 172
 173 static struct clk *periph_clocks[] __initdata = {
 174         &pioA_clk,
 175         &pioB_clk,
 176         &pioC_clk,
 177         &adc_clk,
 178         &adc_op_clk,
 179         &usart0_clk,
 180         &usart1_clk,
 181         &usart2_clk,
 182         &mmc_clk,
 183         &udc_clk,
 184         &twi_clk,
 185         &spi0_clk,
 186         &spi1_clk,
 187         &ssc_clk,
 188         &tc0_clk,
 189         &tc1_clk,
 190         &tc2_clk,
 191         &ohci_clk,
 192         &macb_clk,
 193         &isi_clk,
 194         &usart3_clk,
 195         &usart4_clk,
 196         &usart5_clk,
 197         &tc3_clk,
 198         &tc4_clk,
 199         &tc5_clk,
 200         // irq0 .. irq2
 201 };
 202
 203 static struct clk_lookup periph_clocks_lookups[] = {
 204         /* One additional fake clock for macb_hclk */
 205         CLKDEV_CON_ID("hclk", &macb_clk),
 206         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 207         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 208         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 209         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 210         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 211         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 212         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 213         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 214         CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk),
 215         CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk),
 216         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
 217         CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk),
 218         /* more usart lookup table for DT entries */
 219         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 220         CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 221         CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
 222         CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
 223         CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
 224         CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
 225         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
 226         CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
 227         /* more tc lookup table for DT entries */
 228         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 229         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 230         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 231         CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
 232         CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 233         CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 234         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
 235         CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
 236         CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
 237         CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
 238         /* fake hclk clock */
 239         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 240         CLKDEV_CON_ID("pioA", &pioA_clk),
 241         CLKDEV_CON_ID("pioB", &pioB_clk),
 242         CLKDEV_CON_ID("pioC", &pioC_clk),
 243         CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
 244         CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
 245         CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
 246 };
 247
 248 static struct clk_lookup usart_clocks_lookups[] = {
 249         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 250         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 251         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 252         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 253         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 254         CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
 255         CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
 256 };
 257
 258 /*
 259  * The two programmable clocks.
 260  * You must configure pin multiplexing to bring these signals out.
 261  */
 262 static struct clk pck0 = {
 263         .name           = "pck0",
 264         .pmc_mask       = AT91_PMC_PCK0,
 265         .type           = CLK_TYPE_PROGRAMMABLE,
 266         .id             = 0,
 267 };
 268 static struct clk pck1 = {
 269         .name           = "pck1",
 270         .pmc_mask       = AT91_PMC_PCK1,
 271         .type           = CLK_TYPE_PROGRAMMABLE,
 272         .id             = 1,
 273 };
 274
 275 static void __init at91sam9260_register_clocks(void)
 276 {
 277         int i;
 278
 279         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 280                 clk_register(periph_clocks[i]);
 281
 282         clkdev_add_table(periph_clocks_lookups,
 283                          ARRAY_SIZE(periph_clocks_lookups));
 284         clkdev_add_table(usart_clocks_lookups,
 285                          ARRAY_SIZE(usart_clocks_lookups));
 286
 287         clk_register(&pck0);
 288         clk_register(&pck1);
 289 }
 290
 291 /* --------------------------------------------------------------------
 292  *  GPIO
 293  * -------------------------------------------------------------------- */
 294
 295 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
 296         {
 297                 .id             = AT91SAM9260_ID_PIOA,
 298                 .regbase        = AT91SAM9260_BASE_PIOA,
 299         }, {
 300                 .id             = AT91SAM9260_ID_PIOB,
 301                 .regbase        = AT91SAM9260_BASE_PIOB,
 302         }, {
 303                 .id             = AT91SAM9260_ID_PIOC,
 304                 .regbase        = AT91SAM9260_BASE_PIOC,
 305         }
 306 };
 307
 308 /* --------------------------------------------------------------------
 309  *  AT91SAM9260 processor initialization
 310  * -------------------------------------------------------------------- */
 311
 312 static void __init at91sam9xe_map_io(void)
 313 {
 314         unsigned long sram_size;
 315
 316         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 317                 case AT91_CIDR_SRAMSIZ_32K:
 318                         sram_size = 2 * SZ_16K;
 319                         break;
 320                 case AT91_CIDR_SRAMSIZ_16K:
 321                 default:
 322                         sram_size = SZ_16K;
 323         }
 324
 325         at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
 326 }
 327
 328 static void __init at91sam9260_map_io(void)
 329 {
 330         if (cpu_is_at91sam9xe())
 331                 at91sam9xe_map_io();
 332         else if (cpu_is_at91sam9g20())
 333                 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
 334         else
 335                 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 336 }
 337
 338 static void __init at91sam9260_ioremap_registers(void)
 339 {
 340         at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
 341         at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
 342         at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
 343         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
 344         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 345         at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 346         at91_pm_set_standby(at91sam9_sdram_standby);
 347 }
 348
 349 static void __init at91sam9260_initialize(void)
 350 {
 351         arm_pm_idle = at91sam9_idle;
 352         arm_pm_restart = at91sam9_alt_restart;
 353
 354         at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
 355
 356         /* Register GPIO subsystem */
 357         at91_gpio_init(at91sam9260_gpio, 3);
 358 }
 359
 360 /* --------------------------------------------------------------------
 361  *  Interrupt initialization
 362  * -------------------------------------------------------------------- */
 363
 364 /*
 365  * The default interrupt priority levels (0 = lowest, 7 = highest).
 366  */
 367 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 368         7,      /* Advanced Interrupt Controller */
 369         7,      /* System Peripherals */
 370         1,      /* Parallel IO Controller A */
 371         1,      /* Parallel IO Controller B */
 372         1,      /* Parallel IO Controller C */
 373         0,      /* Analog-to-Digital Converter */
 374         5,      /* USART 0 */
 375         5,      /* USART 1 */
 376         5,      /* USART 2 */
 377         0,      /* Multimedia Card Interface */
 378         2,      /* USB Device Port */
 379         6,      /* Two-Wire Interface */
 380         5,      /* Serial Peripheral Interface 0 */
 381         5,      /* Serial Peripheral Interface 1 */
 382         5,      /* Serial Synchronous Controller */
 383         0,
 384         0,
 385         0,      /* Timer Counter 0 */
 386         0,      /* Timer Counter 1 */
 387         0,      /* Timer Counter 2 */
 388         2,      /* USB Host port */
 389         3,      /* Ethernet */
 390         0,      /* Image Sensor Interface */
 391         5,      /* USART 3 */
 392         5,      /* USART 4 */
 393         5,      /* USART 5 */
 394         0,      /* Timer Counter 3 */
 395         0,      /* Timer Counter 4 */
 396         0,      /* Timer Counter 5 */
 397         0,      /* Advanced Interrupt Controller */
 398         0,      /* Advanced Interrupt Controller */
 399         0,      /* Advanced Interrupt Controller */
 400 };
 401
 402 AT91_SOC_START(at91sam9260)
 403         .map_io = at91sam9260_map_io,
 404         .default_irq_priority = at91sam9260_default_irq_priority,
 405         .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 406                     | (1 << AT91SAM9260_ID_IRQ2),
 407         .ioremap_registers = at91sam9260_ioremap_registers,
 408         .register_clocks = at91sam9260_register_clocks,
 409         .init = at91sam9260_initialize,
 410 AT91_SOC_END