arch/arm/boot/dts/vf610-twr.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 /dts-v1/;
  11 #include "vf610.dtsi"
  12
  13 / {
  14         model = "VF610 Tower Board";
  15         compatible = "fsl,vf610-twr", "fsl,vf610";
  16
  17         chosen {
  18                 bootargs = "console=ttyLP1,115200";
  19         };
  20
  21         memory {
  22                 reg = <0x80000000 0x8000000>;
  23         };
  24
  25         audio_ext: mclk_osc {
  26                 compatible = "fixed-clock";
  27                 #clock-cells = <0>;
  28                 clock-frequency = <24576000>;
  29         };
  30
  31         enet_ext: eth_osc {
  32                 compatible = "fixed-clock";
  33                 #clock-cells = <0>;
  34                 clock-frequency = <50000000>;
  35         };
  36
  37         regulators {
  38                 compatible = "simple-bus";
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 reg_3p3v: regulator@0 {
  43                         compatible = "regulator-fixed";
  44                         reg = <0>;
  45                         regulator-name = "3P3V";
  46                         regulator-min-microvolt = <3300000>;
  47                         regulator-max-microvolt = <3300000>;
  48                         regulator-always-on;
  49                 };
  50
  51                 reg_vcc_3v3_mcu: regulator@1 {
  52                         compatible = "regulator-fixed";
  53                         reg = <1>;
  54                         regulator-name = "vcc_3v3_mcu";
  55                         regulator-min-microvolt = <3300000>;
  56                         regulator-max-microvolt = <3300000>;
  57                 };
  58         };
  59
  60         sound {
  61                 compatible = "simple-audio-card";
  62                 simple-audio-card,format = "i2s";
  63                 simple-audio-card,widgets =
  64                         "Microphone", "Microphone Jack",
  65                         "Headphone", "Headphone Jack",
  66                         "Speaker", "Speaker Ext",
  67                         "Line", "Line In Jack";
  68                 simple-audio-card,routing =
  69                         "MIC_IN", "Microphone Jack",
  70                         "Microphone Jack", "Mic Bias",
  71                         "LINE_IN", "Line In Jack",
  72                         "Headphone Jack", "HP_OUT",
  73                         "Speaker Ext", "LINE_OUT";
  74
  75                 simple-audio-card,cpu {
  76                         sound-dai = <&sai2>;
  77                         frame-master;
  78                         bitclock-master;
  79                 };
  80
  81                 simple-audio-card,codec {
  82                         sound-dai = <&codec>;
  83                         frame-master;
  84                         bitclock-master;
  85                 };
  86         };
  87 };
  88
  89 &adc0 {
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_adc0_ad5>;
  92         vref-supply = <&reg_vcc_3v3_mcu>;
  93         status = "okay";
  94 };
  95
  96 &clks {
  97         clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
  98         clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
  99 };
 100
 101 &dspi0 {
 102         bus-num = <0>;
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_dspi0>;
 105         status = "okay";
 106
 107         sflash: at26df081a@0 {
 108                 #address-cells = <1>;
 109                 #size-cells = <1>;
 110                 compatible = "atmel,at26df081a";
 111                 spi-max-frequency = <16000000>;
 112                 spi-cpol;
 113                 spi-cpha;
 114                 reg = <0>;
 115         };
 116 };
 117
 118 &edma0 {
 119         status = "okay";
 120 };
 121
 122 &esdhc1 {
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&pinctrl_esdhc1>;
 125         bus-width = <4>;
 126         cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
 127         status = "okay";
 128 };
 129
 130 &fec0 {
 131         phy-mode = "rmii";
 132         phy-handle = <&ethphy0>;
 133         pinctrl-names = "default";
 134         pinctrl-0 = <&pinctrl_fec0>;
 135         status = "okay";
 136
 137         mdio {
 138                 #address-cells = <1>;
 139                 #size-cells = <0>;
 140
 141                 ethphy0: ethernet-phy@0 {
 142                         reg = <0>;
 143                 };
 144
 145                 ethphy1: ethernet-phy@1 {
 146                         reg = <1>;
 147                 };
 148         };
 149 };
 150
 151 &fec1 {
 152         phy-mode = "rmii";
 153         phy-handle = <&ethphy1>;
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_fec1>;
 156         status = "okay";
 157 };
 158
 159 &i2c0 {
 160         clock-frequency = <100000>;
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_i2c0>;
 163         status = "okay";
 164
 165         codec: sgtl5000@0a {
 166                #sound-dai-cells = <0>;
 167                compatible = "fsl,sgtl5000";
 168                reg = <0x0a>;
 169                VDDA-supply = <&reg_3p3v>;
 170                VDDIO-supply = <&reg_3p3v>;
 171                clocks = <&clks VF610_CLK_SAI2>;
 172        };
 173 };
 174
 175 &iomuxc {
 176         vf610-twr {
 177                 pinctrl_adc0_ad5: adc0ad5grp {
 178                         fsl,pins = <
 179                                 VF610_PAD_PTC30__ADC0_SE5               0xa1
 180                         >;
 181                 };
 182
 183                 pinctrl_dspi0: dspi0grp {
 184                         fsl,pins = <
 185                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
 186                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
 187                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 188                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
 189                         >;
 190                 };
 191
 192                 pinctrl_esdhc1: esdhc1grp {
 193                         fsl,pins = <
 194                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 195                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 196                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 197                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 198                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 199                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 200                                 VF610_PAD_PTA7__GPIO_134        0x219d
 201                         >;
 202                 };
 203
 204                 pinctrl_fec0: fec0grp {
 205                         fsl,pins = <
 206                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 207                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
 208                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
 209                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
 210                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
 211                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
 212                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
 213                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
 214                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
 215                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 216                         >;
 217                 };
 218
 219                 pinctrl_fec1: fec1grp {
 220                         fsl,pins = <
 221                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 222                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 223                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 224                                 VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 225                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 226                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 227                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 228                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 229                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 230                         >;
 231                 };
 232
 233                 pinctrl_i2c0: i2c0grp {
 234                         fsl,pins = <
 235                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 236                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 237                         >;
 238                 };
 239
 240                 pinctrl_pwm0: pwm0grp {
 241                         fsl,pins = <
 242                                 VF610_PAD_PTB0__FTM0_CH0                0x1582
 243                                 VF610_PAD_PTB1__FTM0_CH1                0x1582
 244                                 VF610_PAD_PTB2__FTM0_CH2                0x1582
 245                                 VF610_PAD_PTB3__FTM0_CH3                0x1582
 246                         >;
 247                 };
 248
 249                 pinctrl_sai2: sai2grp {
 250                         fsl,pins = <
 251                                 VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
 252                                 VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
 253                                 VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
 254                                 VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
 255                                 VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
 256                                 VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
 257                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
 258                         >;
 259                 };
 260
 261                 pinctrl_uart1: uart1grp {
 262                         fsl,pins = <
 263                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 264                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 265                         >;
 266                 };
 267
 268                 pinctrl_uart2: uart2grp {
 269                         fsl,pins = <
 270                                 VF610_PAD_PTB6__UART2_TX                0x21a2
 271                                 VF610_PAD_PTB7__UART2_RX                0x21a1
 272                         >;
 273                 };
 274         };
 275 };
 276
 277 &pwm0 {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_pwm0>;
 280         status = "okay";
 281 };
 282
 283 &sai2 {
 284         #sound-dai-cells = <0>;
 285         pinctrl-names = "default";
 286         pinctrl-0 = <&pinctrl_sai2>;
 287         status = "okay";
 288 };
 289
 290 &uart1 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_uart1>;
 293         status = "okay";
 294 };
 295
 296 &uart2 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_uart2>;
 299         status = "okay";
 300 };
 301
 302 &usbdev0 {
 303         disable-over-current;
 304         status = "okay";
 305 };
 306
 307 &usbh1 {
 308         disable-over-current;
 309         status = "okay";
 310 };
 311
 312 &usbmisc0 {
 313         status = "okay";
 314 };
 315
 316 &usbmisc1 {
 317         status = "okay";
 318 };
 319
 320 &usbphy0 {
 321         status = "okay";
 322 };
 323
 324 &usbphy1 {
 325         status = "okay";
 326 };