arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/gpio/tegra-gpio.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3
   4 #include "skeleton.dtsi"
   5
   6 / {
   7         compatible = "nvidia,tegra124";
   8         interrupt-parent = <&gic>;
   9
  10         gic: interrupt-controller@50041000 {
  11                 compatible = "arm,cortex-a15-gic";
  12                 #interrupt-cells = <3>;
  13                 interrupt-controller;
  14                 reg = <0x50041000 0x1000>,
  15                       <0x50042000 0x1000>,
  16                       <0x50044000 0x2000>,
  17                       <0x50046000 0x2000>;
  18                 interrupts = <GIC_PPI 9
  19                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  20         };
  21
  22         timer@60005000 {
  23                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
  24                 reg = <0x60005000 0x400>;
  25                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  26                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  27                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  28                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  29                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  31         };
  32
  33         gpio: gpio@6000d000 {
  34                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
  35                 reg = <0x6000d000 0x1000>;
  36                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  37                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  38                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  39                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  40                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  41                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  42                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  43                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  44                 #gpio-cells = <2>;
  45                 gpio-controller;
  46                 #interrupt-cells = <2>;
  47                 interrupt-controller;
  48         };
  49
  50         /*
  51          * There are two serial driver i.e. 8250 based simple serial
  52          * driver and APB DMA based serial driver for higher baudrate
  53          * and performace. To enable the 8250 based driver, the compatible
  54          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
  55          * the APB DMA based serial driver, the comptible is
  56          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
  57          */
  58         serial@70006000 {
  59                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  60                 reg = <0x70006000 0x40>;
  61                 reg-shift = <2>;
  62                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  63                 status = "disabled";
  64         };
  65
  66         serial@70006040 {
  67                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  68                 reg = <0x70006040 0x40>;
  69                 reg-shift = <2>;
  70                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  71                 status = "disabled";
  72         };
  73
  74         serial@70006200 {
  75                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  76                 reg = <0x70006200 0x40>;
  77                 reg-shift = <2>;
  78                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  79                 status = "disabled";
  80         };
  81
  82         serial@70006300 {
  83                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  84                 reg = <0x70006300 0x40>;
  85                 reg-shift = <2>;
  86                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  87                 status = "disabled";
  88         };
  89
  90         serial@70006400 {
  91                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  92                 reg = <0x70006400 0x40>;
  93                 reg-shift = <2>;
  94                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  95                 status = "disabled";
  96         };
  97
  98         rtc@7000e000 {
  99                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 100                 reg = <0x7000e000 0x100>;
 101                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 102         };
 103
 104         pmc@7000e400 {
 105                 compatible = "nvidia,tegra124-pmc";
 106                 reg = <0x7000e400 0x400>;
 107         };
 108
 109         cpus {
 110                 #address-cells = <1>;
 111                 #size-cells = <0>;
 112
 113                 cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a15";
 116                         reg = <0>;
 117                 };
 118
 119                 cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a15";
 122                         reg = <1>;
 123                 };
 124
 125                 cpu@2 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a15";
 128                         reg = <2>;
 129                 };
 130
 131                 cpu@3 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a15";
 134                         reg = <3>;
 135                 };
 136         };
 137
 138         timer {
 139                 compatible = "arm,armv7-timer";
 140                 interrupts = <GIC_PPI 13
 141                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 142                              <GIC_PPI 14
 143                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 144                              <GIC_PPI 11
 145                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 146                              <GIC_PPI 10
 147                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 148         };
 149 };