arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this file; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 /include/ "skeleton.dtsi"
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &gmac;
  57         };
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  66                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  67                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  68                                  <&ahb_gates 44>;
  69                         status = "disabled";
  70                 };
  71         };
  72
  73         cpus {
  74                 #address-cells = <1>;
  75                 #size-cells = <0>;
  76
  77                 cpu@0 {
  78                         compatible = "arm,cortex-a7";
  79                         device_type = "cpu";
  80                         reg = <0>;
  81                 };
  82
  83                 cpu@1 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <1>;
  87                 };
  88         };
  89
  90         memory {
  91                 reg = <0x40000000 0x80000000>;
  92         };
  93
  94         timer {
  95                 compatible = "arm,armv7-timer";
  96                 interrupts = <1 13 0xf08>,
  97                              <1 14 0xf08>,
  98                              <1 11 0xf08>,
  99                              <1 10 0xf08>;
 100         };
 101
 102         pmu {
 103                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 104                 interrupts = <0 120 4>,
 105                              <0 121 4>;
 106         };
 107
 108         clocks {
 109                 #address-cells = <1>;
 110                 #size-cells = <1>;
 111                 ranges;
 112
 113                 osc24M: clk@01c20050 {
 114                         #clock-cells = <0>;
 115                         compatible = "allwinner,sun4i-a10-osc-clk";
 116                         reg = <0x01c20050 0x4>;
 117                         clock-frequency = <24000000>;
 118                         clock-output-names = "osc24M";
 119                 };
 120
 121                 osc32k: clk@0 {
 122                         #clock-cells = <0>;
 123                         compatible = "fixed-clock";
 124                         clock-frequency = <32768>;
 125                         clock-output-names = "osc32k";
 126                 };
 127
 128                 pll1: clk@01c20000 {
 129                         #clock-cells = <0>;
 130                         compatible = "allwinner,sun4i-a10-pll1-clk";
 131                         reg = <0x01c20000 0x4>;
 132                         clocks = <&osc24M>;
 133                         clock-output-names = "pll1";
 134                 };
 135
 136                 pll4: clk@01c20018 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun7i-a20-pll4-clk";
 139                         reg = <0x01c20018 0x4>;
 140                         clocks = <&osc24M>;
 141                         clock-output-names = "pll4";
 142                 };
 143
 144                 pll5: clk@01c20020 {
 145                         #clock-cells = <1>;
 146                         compatible = "allwinner,sun4i-a10-pll5-clk";
 147                         reg = <0x01c20020 0x4>;
 148                         clocks = <&osc24M>;
 149                         clock-output-names = "pll5_ddr", "pll5_other";
 150                 };
 151
 152                 pll6: clk@01c20028 {
 153                         #clock-cells = <1>;
 154                         compatible = "allwinner,sun4i-a10-pll6-clk";
 155                         reg = <0x01c20028 0x4>;
 156                         clocks = <&osc24M>;
 157                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 158                 };
 159
 160                 pll8: clk@01c20040 {
 161                         #clock-cells = <0>;
 162                         compatible = "allwinner,sun7i-a20-pll4-clk";
 163                         reg = <0x01c20040 0x4>;
 164                         clocks = <&osc24M>;
 165                         clock-output-names = "pll8";
 166                 };
 167
 168                 cpu: cpu@01c20054 {
 169                         #clock-cells = <0>;
 170                         compatible = "allwinner,sun4i-a10-cpu-clk";
 171                         reg = <0x01c20054 0x4>;
 172                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 173                         clock-output-names = "cpu";
 174                 };
 175
 176                 axi: axi@01c20054 {
 177                         #clock-cells = <0>;
 178                         compatible = "allwinner,sun4i-a10-axi-clk";
 179                         reg = <0x01c20054 0x4>;
 180                         clocks = <&cpu>;
 181                         clock-output-names = "axi";
 182                 };
 183
 184                 ahb: ahb@01c20054 {
 185                         #clock-cells = <0>;
 186                         compatible = "allwinner,sun4i-a10-ahb-clk";
 187                         reg = <0x01c20054 0x4>;
 188                         clocks = <&axi>;
 189                         clock-output-names = "ahb";
 190                 };
 191
 192                 ahb_gates: clk@01c20060 {
 193                         #clock-cells = <1>;
 194                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 195                         reg = <0x01c20060 0x8>;
 196                         clocks = <&ahb>;
 197                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 198                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 199                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 200                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 201                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 202                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 203                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 204                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 205                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 206                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 207                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 208                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 209                                 "ahb_mali";
 210                 };
 211
 212                 apb0: apb0@01c20054 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-a10-apb0-clk";
 215                         reg = <0x01c20054 0x4>;
 216                         clocks = <&ahb>;
 217                         clock-output-names = "apb0";
 218                 };
 219
 220                 apb0_gates: clk@01c20068 {
 221                         #clock-cells = <1>;
 222                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 223                         reg = <0x01c20068 0x4>;
 224                         clocks = <&apb0>;
 225                         clock-output-names = "apb0_codec", "apb0_spdif",
 226                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 227                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 228                                 "apb0_iis2", "apb0_keypad";
 229                 };
 230
 231                 apb1: clk@01c20058 {
 232                         #clock-cells = <0>;
 233                         compatible = "allwinner,sun4i-a10-apb1-clk";
 234                         reg = <0x01c20058 0x4>;
 235                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 236                         clock-output-names = "apb1";
 237                 };
 238
 239                 apb1_gates: clk@01c2006c {
 240                         #clock-cells = <1>;
 241                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 242                         reg = <0x01c2006c 0x4>;
 243                         clocks = <&apb1>;
 244                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 245                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 246                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 247                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 248                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 249                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 250                 };
 251
 252                 nand_clk: clk@01c20080 {
 253                         #clock-cells = <0>;
 254                         compatible = "allwinner,sun4i-a10-mod0-clk";
 255                         reg = <0x01c20080 0x4>;
 256                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 257                         clock-output-names = "nand";
 258                 };
 259
 260                 ms_clk: clk@01c20084 {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun4i-a10-mod0-clk";
 263                         reg = <0x01c20084 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 265                         clock-output-names = "ms";
 266                 };
 267
 268                 mmc0_clk: clk@01c20088 {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-a10-mod0-clk";
 271                         reg = <0x01c20088 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "mmc0";
 274                 };
 275
 276                 mmc1_clk: clk@01c2008c {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-a10-mod0-clk";
 279                         reg = <0x01c2008c 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "mmc1";
 282                 };
 283
 284                 mmc2_clk: clk@01c20090 {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-a10-mod0-clk";
 287                         reg = <0x01c20090 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "mmc2";
 290                 };
 291
 292                 mmc3_clk: clk@01c20094 {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-a10-mod0-clk";
 295                         reg = <0x01c20094 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "mmc3";
 298                 };
 299
 300                 ts_clk: clk@01c20098 {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-a10-mod0-clk";
 303                         reg = <0x01c20098 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "ts";
 306                 };
 307
 308                 ss_clk: clk@01c2009c {
 309                         #clock-cells = <0>;
 310                         compatible = "allwinner,sun4i-a10-mod0-clk";
 311                         reg = <0x01c2009c 0x4>;
 312                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 313                         clock-output-names = "ss";
 314                 };
 315
 316                 spi0_clk: clk@01c200a0 {
 317                         #clock-cells = <0>;
 318                         compatible = "allwinner,sun4i-a10-mod0-clk";
 319                         reg = <0x01c200a0 0x4>;
 320                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 321                         clock-output-names = "spi0";
 322                 };
 323
 324                 spi1_clk: clk@01c200a4 {
 325                         #clock-cells = <0>;
 326                         compatible = "allwinner,sun4i-a10-mod0-clk";
 327                         reg = <0x01c200a4 0x4>;
 328                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 329                         clock-output-names = "spi1";
 330                 };
 331
 332                 spi2_clk: clk@01c200a8 {
 333                         #clock-cells = <0>;
 334                         compatible = "allwinner,sun4i-a10-mod0-clk";
 335                         reg = <0x01c200a8 0x4>;
 336                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 337                         clock-output-names = "spi2";
 338                 };
 339
 340                 pata_clk: clk@01c200ac {
 341                         #clock-cells = <0>;
 342                         compatible = "allwinner,sun4i-a10-mod0-clk";
 343                         reg = <0x01c200ac 0x4>;
 344                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 345                         clock-output-names = "pata";
 346                 };
 347
 348                 ir0_clk: clk@01c200b0 {
 349                         #clock-cells = <0>;
 350                         compatible = "allwinner,sun4i-a10-mod0-clk";
 351                         reg = <0x01c200b0 0x4>;
 352                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 353                         clock-output-names = "ir0";
 354                 };
 355
 356                 ir1_clk: clk@01c200b4 {
 357                         #clock-cells = <0>;
 358                         compatible = "allwinner,sun4i-a10-mod0-clk";
 359                         reg = <0x01c200b4 0x4>;
 360                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 361                         clock-output-names = "ir1";
 362                 };
 363
 364                 usb_clk: clk@01c200cc {
 365                         #clock-cells = <1>;
 366                         #reset-cells = <1>;
 367                         compatible = "allwinner,sun4i-a10-usb-clk";
 368                         reg = <0x01c200cc 0x4>;
 369                         clocks = <&pll6 1>;
 370                         clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
 371                 };
 372
 373                 spi3_clk: clk@01c200d4 {
 374                         #clock-cells = <0>;
 375                         compatible = "allwinner,sun4i-a10-mod0-clk";
 376                         reg = <0x01c200d4 0x4>;
 377                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 378                         clock-output-names = "spi3";
 379                 };
 380
 381                 mbus_clk: clk@01c2015c {
 382                         #clock-cells = <0>;
 383                         compatible = "allwinner,sun5i-a13-mbus-clk";
 384                         reg = <0x01c2015c 0x4>;
 385                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 386                         clock-output-names = "mbus";
 387                 };
 388
 389                 /*
 390                  * The following two are dummy clocks, placeholders used in the gmac_tx
 391                  * clock. The gmac driver will choose one parent depending on the PHY
 392                  * interface mode, using clk_set_rate auto-reparenting.
 393                  * The actual TX clock rate is not controlled by the gmac_tx clock.
 394                  */
 395                 mii_phy_tx_clk: clk@2 {
 396                         #clock-cells = <0>;
 397                         compatible = "fixed-clock";
 398                         clock-frequency = <25000000>;
 399                         clock-output-names = "mii_phy_tx";
 400                 };
 401
 402                 gmac_int_tx_clk: clk@3 {
 403                         #clock-cells = <0>;
 404                         compatible = "fixed-clock";
 405                         clock-frequency = <125000000>;
 406                         clock-output-names = "gmac_int_tx";
 407                 };
 408
 409                 gmac_tx_clk: clk@01c20164 {
 410                         #clock-cells = <0>;
 411                         compatible = "allwinner,sun7i-a20-gmac-clk";
 412                         reg = <0x01c20164 0x4>;
 413                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 414                         clock-output-names = "gmac_tx";
 415                 };
 416
 417                 /*
 418                  * Dummy clock used by output clocks
 419                  */
 420                 osc24M_32k: clk@1 {
 421                         #clock-cells = <0>;
 422                         compatible = "fixed-factor-clock";
 423                         clock-div = <750>;
 424                         clock-mult = <1>;
 425                         clocks = <&osc24M>;
 426                         clock-output-names = "osc24M_32k";
 427                 };
 428
 429                 clk_out_a: clk@01c201f0 {
 430                         #clock-cells = <0>;
 431                         compatible = "allwinner,sun7i-a20-out-clk";
 432                         reg = <0x01c201f0 0x4>;
 433                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 434                         clock-output-names = "clk_out_a";
 435                 };
 436
 437                 clk_out_b: clk@01c201f4 {
 438                         #clock-cells = <0>;
 439                         compatible = "allwinner,sun7i-a20-out-clk";
 440                         reg = <0x01c201f4 0x4>;
 441                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 442                         clock-output-names = "clk_out_b";
 443                 };
 444         };
 445
 446         soc@01c00000 {
 447                 compatible = "simple-bus";
 448                 #address-cells = <1>;
 449                 #size-cells = <1>;
 450                 ranges;
 451
 452                 nmi_intc: interrupt-controller@01c00030 {
 453                         compatible = "allwinner,sun7i-a20-sc-nmi";
 454                         interrupt-controller;
 455                         #interrupt-cells = <2>;
 456                         reg = <0x01c00030 0x0c>;
 457                         interrupts = <0 0 4>;
 458                 };
 459
 460                 dma: dma-controller@01c02000 {
 461                         compatible = "allwinner,sun4i-a10-dma";
 462                         reg = <0x01c02000 0x1000>;
 463                         interrupts = <0 27 4>;
 464                         clocks = <&ahb_gates 6>;
 465                         #dma-cells = <2>;
 466                 };
 467
 468                 spi0: spi@01c05000 {
 469                         compatible = "allwinner,sun4i-a10-spi";
 470                         reg = <0x01c05000 0x1000>;
 471                         interrupts = <0 10 4>;
 472                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 473                         clock-names = "ahb", "mod";
 474                         dmas = <&dma 1 27>, <&dma 1 26>;
 475                         dma-names = "rx", "tx";
 476                         status = "disabled";
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                 };
 480
 481                 spi1: spi@01c06000 {
 482                         compatible = "allwinner,sun4i-a10-spi";
 483                         reg = <0x01c06000 0x1000>;
 484                         interrupts = <0 11 4>;
 485                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 486                         clock-names = "ahb", "mod";
 487                         dmas = <&dma 1 9>, <&dma 1 8>;
 488                         dma-names = "rx", "tx";
 489                         status = "disabled";
 490                         #address-cells = <1>;
 491                         #size-cells = <0>;
 492                 };
 493
 494                 emac: ethernet@01c0b000 {
 495                         compatible = "allwinner,sun4i-a10-emac";
 496                         reg = <0x01c0b000 0x1000>;
 497                         interrupts = <0 55 4>;
 498                         clocks = <&ahb_gates 17>;
 499                         status = "disabled";
 500                 };
 501
 502                 mdio@01c0b080 {
 503                         compatible = "allwinner,sun4i-a10-mdio";
 504                         reg = <0x01c0b080 0x14>;
 505                         status = "disabled";
 506                         #address-cells = <1>;
 507                         #size-cells = <0>;
 508                 };
 509
 510                 mmc0: mmc@01c0f000 {
 511                         compatible = "allwinner,sun5i-a13-mmc";
 512                         reg = <0x01c0f000 0x1000>;
 513                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 514                         clock-names = "ahb", "mmc";
 515                         interrupts = <0 32 4>;
 516                         status = "disabled";
 517                 };
 518
 519                 mmc1: mmc@01c10000 {
 520                         compatible = "allwinner,sun5i-a13-mmc";
 521                         reg = <0x01c10000 0x1000>;
 522                         clocks = <&ahb_gates 9>, <&mmc1_clk>;
 523                         clock-names = "ahb", "mmc";
 524                         interrupts = <0 33 4>;
 525                         status = "disabled";
 526                 };
 527
 528                 mmc2: mmc@01c11000 {
 529                         compatible = "allwinner,sun5i-a13-mmc";
 530                         reg = <0x01c11000 0x1000>;
 531                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 532                         clock-names = "ahb", "mmc";
 533                         interrupts = <0 34 4>;
 534                         status = "disabled";
 535                 };
 536
 537                 mmc3: mmc@01c12000 {
 538                         compatible = "allwinner,sun5i-a13-mmc";
 539                         reg = <0x01c12000 0x1000>;
 540                         clocks = <&ahb_gates 11>, <&mmc3_clk>;
 541                         clock-names = "ahb", "mmc";
 542                         interrupts = <0 35 4>;
 543                         status = "disabled";
 544                 };
 545
 546                 usbphy: phy@01c13400 {
 547                         #phy-cells = <1>;
 548                         compatible = "allwinner,sun7i-a20-usb-phy";
 549                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 550                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 551                         clocks = <&usb_clk 8>;
 552                         clock-names = "usb_phy";
 553                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 554                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 555                         status = "disabled";
 556                 };
 557
 558                 ehci0: usb@01c14000 {
 559                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 560                         reg = <0x01c14000 0x100>;
 561                         interrupts = <0 39 4>;
 562                         clocks = <&ahb_gates 1>;
 563                         phys = <&usbphy 1>;
 564                         phy-names = "usb";
 565                         status = "disabled";
 566                 };
 567
 568                 ohci0: usb@01c14400 {
 569                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 570                         reg = <0x01c14400 0x100>;
 571                         interrupts = <0 64 4>;
 572                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 573                         phys = <&usbphy 1>;
 574                         phy-names = "usb";
 575                         status = "disabled";
 576                 };
 577
 578                 spi2: spi@01c17000 {
 579                         compatible = "allwinner,sun4i-a10-spi";
 580                         reg = <0x01c17000 0x1000>;
 581                         interrupts = <0 12 4>;
 582                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 583                         clock-names = "ahb", "mod";
 584                         dmas = <&dma 1 29>, <&dma 1 28>;
 585                         dma-names = "rx", "tx";
 586                         status = "disabled";
 587                         #address-cells = <1>;
 588                         #size-cells = <0>;
 589                 };
 590
 591                 ahci: sata@01c18000 {
 592                         compatible = "allwinner,sun4i-a10-ahci";
 593                         reg = <0x01c18000 0x1000>;
 594                         interrupts = <0 56 4>;
 595                         clocks = <&pll6 0>, <&ahb_gates 25>;
 596                         status = "disabled";
 597                 };
 598
 599                 ehci1: usb@01c1c000 {
 600                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 601                         reg = <0x01c1c000 0x100>;
 602                         interrupts = <0 40 4>;
 603                         clocks = <&ahb_gates 3>;
 604                         phys = <&usbphy 2>;
 605                         phy-names = "usb";
 606                         status = "disabled";
 607                 };
 608
 609                 ohci1: usb@01c1c400 {
 610                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 611                         reg = <0x01c1c400 0x100>;
 612                         interrupts = <0 65 4>;
 613                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 614                         phys = <&usbphy 2>;
 615                         phy-names = "usb";
 616                         status = "disabled";
 617                 };
 618
 619                 spi3: spi@01c1f000 {
 620                         compatible = "allwinner,sun4i-a10-spi";
 621                         reg = <0x01c1f000 0x1000>;
 622                         interrupts = <0 50 4>;
 623                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 624                         clock-names = "ahb", "mod";
 625                         dmas = <&dma 1 31>, <&dma 1 30>;
 626                         dma-names = "rx", "tx";
 627                         status = "disabled";
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630                 };
 631
 632                 pio: pinctrl@01c20800 {
 633                         compatible = "allwinner,sun7i-a20-pinctrl";
 634                         reg = <0x01c20800 0x400>;
 635                         interrupts = <0 28 4>;
 636                         clocks = <&apb0_gates 5>;
 637                         gpio-controller;
 638                         interrupt-controller;
 639                         #interrupt-cells = <2>;
 640                         #size-cells = <0>;
 641                         #gpio-cells = <3>;
 642
 643                         pwm0_pins_a: pwm0@0 {
 644                                 allwinner,pins = "PB2";
 645                                 allwinner,function = "pwm";
 646                                 allwinner,drive = <0>;
 647                                 allwinner,pull = <0>;
 648                         };
 649
 650                         pwm1_pins_a: pwm1@0 {
 651                                 allwinner,pins = "PI3";
 652                                 allwinner,function = "pwm";
 653                                 allwinner,drive = <0>;
 654                                 allwinner,pull = <0>;
 655                         };
 656
 657                         uart0_pins_a: uart0@0 {
 658                                 allwinner,pins = "PB22", "PB23";
 659                                 allwinner,function = "uart0";
 660                                 allwinner,drive = <0>;
 661                                 allwinner,pull = <0>;
 662                         };
 663
 664                         uart2_pins_a: uart2@0 {
 665                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 666                                 allwinner,function = "uart2";
 667                                 allwinner,drive = <0>;
 668                                 allwinner,pull = <0>;
 669                         };
 670
 671                         uart3_pins_a: uart3@0 {
 672                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 673                                 allwinner,function = "uart3";
 674                                 allwinner,drive = <0>;
 675                                 allwinner,pull = <0>;
 676                         };
 677
 678                         uart3_pins_b: uart3@1 {
 679                                 allwinner,pins = "PH0", "PH1";
 680                                 allwinner,function = "uart3";
 681                                 allwinner,drive = <0>;
 682                                 allwinner,pull = <0>;
 683                         };
 684
 685                         uart4_pins_a: uart4@0 {
 686                                 allwinner,pins = "PG10", "PG11";
 687                                 allwinner,function = "uart4";
 688                                 allwinner,drive = <0>;
 689                                 allwinner,pull = <0>;
 690                         };
 691
 692                         uart5_pins_a: uart5@0 {
 693                                 allwinner,pins = "PI10", "PI11";
 694                                 allwinner,function = "uart5";
 695                                 allwinner,drive = <0>;
 696                                 allwinner,pull = <0>;
 697                         };
 698
 699                         uart6_pins_a: uart6@0 {
 700                                 allwinner,pins = "PI12", "PI13";
 701                                 allwinner,function = "uart6";
 702                                 allwinner,drive = <0>;
 703                                 allwinner,pull = <0>;
 704                         };
 705
 706                         uart7_pins_a: uart7@0 {
 707                                 allwinner,pins = "PI20", "PI21";
 708                                 allwinner,function = "uart7";
 709                                 allwinner,drive = <0>;
 710                                 allwinner,pull = <0>;
 711                         };
 712
 713                         i2c0_pins_a: i2c0@0 {
 714                                 allwinner,pins = "PB0", "PB1";
 715                                 allwinner,function = "i2c0";
 716                                 allwinner,drive = <0>;
 717                                 allwinner,pull = <0>;
 718                         };
 719
 720                         i2c1_pins_a: i2c1@0 {
 721                                 allwinner,pins = "PB18", "PB19";
 722                                 allwinner,function = "i2c1";
 723                                 allwinner,drive = <0>;
 724                                 allwinner,pull = <0>;
 725                         };
 726
 727                         i2c2_pins_a: i2c2@0 {
 728                                 allwinner,pins = "PB20", "PB21";
 729                                 allwinner,function = "i2c2";
 730                                 allwinner,drive = <0>;
 731                                 allwinner,pull = <0>;
 732                         };
 733
 734                         i2c3_pins_a: i2c3@0 {
 735                                 allwinner,pins = "PI0", "PI1";
 736                                 allwinner,function = "i2c3";
 737                                 allwinner,drive = <0>;
 738                                 allwinner,pull = <0>;
 739                         };
 740
 741                         emac_pins_a: emac0@0 {
 742                                 allwinner,pins = "PA0", "PA1", "PA2",
 743                                                 "PA3", "PA4", "PA5", "PA6",
 744                                                 "PA7", "PA8", "PA9", "PA10",
 745                                                 "PA11", "PA12", "PA13", "PA14",
 746                                                 "PA15", "PA16";
 747                                 allwinner,function = "emac";
 748                                 allwinner,drive = <0>;
 749                                 allwinner,pull = <0>;
 750                         };
 751
 752                         clk_out_a_pins_a: clk_out_a@0 {
 753                                 allwinner,pins = "PI12";
 754                                 allwinner,function = "clk_out_a";
 755                                 allwinner,drive = <0>;
 756                                 allwinner,pull = <0>;
 757                         };
 758
 759                         clk_out_b_pins_a: clk_out_b@0 {
 760                                 allwinner,pins = "PI13";
 761                                 allwinner,function = "clk_out_b";
 762                                 allwinner,drive = <0>;
 763                                 allwinner,pull = <0>;
 764                         };
 765
 766                         gmac_pins_mii_a: gmac_mii@0 {
 767                                 allwinner,pins = "PA0", "PA1", "PA2",
 768                                                 "PA3", "PA4", "PA5", "PA6",
 769                                                 "PA7", "PA8", "PA9", "PA10",
 770                                                 "PA11", "PA12", "PA13", "PA14",
 771                                                 "PA15", "PA16";
 772                                 allwinner,function = "gmac";
 773                                 allwinner,drive = <0>;
 774                                 allwinner,pull = <0>;
 775                         };
 776
 777                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 778                                 allwinner,pins = "PA0", "PA1", "PA2",
 779                                                 "PA3", "PA4", "PA5", "PA6",
 780                                                 "PA7", "PA8", "PA10",
 781                                                 "PA11", "PA12", "PA13",
 782                                                 "PA15", "PA16";
 783                                 allwinner,function = "gmac";
 784                                 /*
 785                                  * data lines in RGMII mode use DDR mode
 786                                  * and need a higher signal drive strength
 787                                  */
 788                                 allwinner,drive = <3>;
 789                                 allwinner,pull = <0>;
 790                         };
 791
 792                         spi0_pins_a: spi0@0 {
 793                                 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
 794                                 allwinner,function = "spi0";
 795                                 allwinner,drive = <0>;
 796                                 allwinner,pull = <0>;
 797                         };
 798
 799                         spi1_pins_a: spi1@0 {
 800                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 801                                 allwinner,function = "spi1";
 802                                 allwinner,drive = <0>;
 803                                 allwinner,pull = <0>;
 804                         };
 805
 806                         spi2_pins_a: spi2@0 {
 807                                 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
 808                                 allwinner,function = "spi2";
 809                                 allwinner,drive = <0>;
 810                                 allwinner,pull = <0>;
 811                         };
 812
 813                         spi2_pins_b: spi2@1 {
 814                                 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
 815                                 allwinner,function = "spi2";
 816                                 allwinner,drive = <0>;
 817                                 allwinner,pull = <0>;
 818                         };
 819
 820                         mmc0_pins_a: mmc0@0 {
 821                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 822                                 allwinner,function = "mmc0";
 823                                 allwinner,drive = <2>;
 824                                 allwinner,pull = <0>;
 825                         };
 826
 827                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 828                                 allwinner,pins = "PH1";
 829                                 allwinner,function = "gpio_in";
 830                                 allwinner,drive = <0>;
 831                                 allwinner,pull = <1>;
 832                         };
 833
 834                         mmc2_pins_a: mmc2@0 {
 835                                 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
 836                                 allwinner,function = "mmc2";
 837                                 allwinner,drive = <2>;
 838                                 allwinner,pull = <1>;
 839                         };
 840
 841                         mmc3_pins_a: mmc3@0 {
 842                                 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
 843                                 allwinner,function = "mmc3";
 844                                 allwinner,drive = <2>;
 845                                 allwinner,pull = <0>;
 846                         };
 847
 848                         ir0_pins_a: ir0@0 {
 849                                     allwinner,pins = "PB3","PB4";
 850                                     allwinner,function = "ir0";
 851                                     allwinner,drive = <0>;
 852                                     allwinner,pull = <0>;
 853                         };
 854
 855                         ir1_pins_a: ir1@0 {
 856                                     allwinner,pins = "PB22","PB23";
 857                                     allwinner,function = "ir1";
 858                                     allwinner,drive = <0>;
 859                                     allwinner,pull = <0>;
 860                         };
 861                 };
 862
 863                 timer@01c20c00 {
 864                         compatible = "allwinner,sun4i-a10-timer";
 865                         reg = <0x01c20c00 0x90>;
 866                         interrupts = <0 22 4>,
 867                                      <0 23 4>,
 868                                      <0 24 4>,
 869                                      <0 25 4>,
 870                                      <0 67 4>,
 871                                      <0 68 4>;
 872                         clocks = <&osc24M>;
 873                 };
 874
 875                 wdt: watchdog@01c20c90 {
 876                         compatible = "allwinner,sun4i-a10-wdt";
 877                         reg = <0x01c20c90 0x10>;
 878                 };
 879
 880                 rtc: rtc@01c20d00 {
 881                         compatible = "allwinner,sun7i-a20-rtc";
 882                         reg = <0x01c20d00 0x20>;
 883                         interrupts = <0 24 4>;
 884                 };
 885
 886                 pwm: pwm@01c20e00 {
 887                         compatible = "allwinner,sun7i-a20-pwm";
 888                         reg = <0x01c20e00 0xc>;
 889                         clocks = <&osc24M>;
 890                         #pwm-cells = <3>;
 891                         status = "disabled";
 892                 };
 893
 894                 ir0: ir@01c21800 {
 895                         compatible = "allwinner,sun4i-a10-ir";
 896                         clocks = <&apb0_gates 6>, <&ir0_clk>;
 897                         clock-names = "apb", "ir";
 898                         interrupts = <0 5 4>;
 899                         reg = <0x01c21800 0x40>;
 900                         status = "disabled";
 901                 };
 902
 903                 ir1: ir@01c21c00 {
 904                         compatible = "allwinner,sun4i-a10-ir";
 905                         clocks = <&apb0_gates 7>, <&ir1_clk>;
 906                         clock-names = "apb", "ir";
 907                         interrupts = <0 6 4>;
 908                         reg = <0x01c21c00 0x40>;
 909                         status = "disabled";
 910                 };
 911
 912                 sid: eeprom@01c23800 {
 913                         compatible = "allwinner,sun7i-a20-sid";
 914                         reg = <0x01c23800 0x200>;
 915                 };
 916
 917                 rtp: rtp@01c25000 {
 918                         compatible = "allwinner,sun4i-a10-ts";
 919                         reg = <0x01c25000 0x100>;
 920                         interrupts = <0 29 4>;
 921                 };
 922
 923                 uart0: serial@01c28000 {
 924                         compatible = "snps,dw-apb-uart";
 925                         reg = <0x01c28000 0x400>;
 926                         interrupts = <0 1 4>;
 927                         reg-shift = <2>;
 928                         reg-io-width = <4>;
 929                         clocks = <&apb1_gates 16>;
 930                         status = "disabled";
 931                 };
 932
 933                 uart1: serial@01c28400 {
 934                         compatible = "snps,dw-apb-uart";
 935                         reg = <0x01c28400 0x400>;
 936                         interrupts = <0 2 4>;
 937                         reg-shift = <2>;
 938                         reg-io-width = <4>;
 939                         clocks = <&apb1_gates 17>;
 940                         status = "disabled";
 941                 };
 942
 943                 uart2: serial@01c28800 {
 944                         compatible = "snps,dw-apb-uart";
 945                         reg = <0x01c28800 0x400>;
 946                         interrupts = <0 3 4>;
 947                         reg-shift = <2>;
 948                         reg-io-width = <4>;
 949                         clocks = <&apb1_gates 18>;
 950                         status = "disabled";
 951                 };
 952
 953                 uart3: serial@01c28c00 {
 954                         compatible = "snps,dw-apb-uart";
 955                         reg = <0x01c28c00 0x400>;
 956                         interrupts = <0 4 4>;
 957                         reg-shift = <2>;
 958                         reg-io-width = <4>;
 959                         clocks = <&apb1_gates 19>;
 960                         status = "disabled";
 961                 };
 962
 963                 uart4: serial@01c29000 {
 964                         compatible = "snps,dw-apb-uart";
 965                         reg = <0x01c29000 0x400>;
 966                         interrupts = <0 17 4>;
 967                         reg-shift = <2>;
 968                         reg-io-width = <4>;
 969                         clocks = <&apb1_gates 20>;
 970                         status = "disabled";
 971                 };
 972
 973                 uart5: serial@01c29400 {
 974                         compatible = "snps,dw-apb-uart";
 975                         reg = <0x01c29400 0x400>;
 976                         interrupts = <0 18 4>;
 977                         reg-shift = <2>;
 978                         reg-io-width = <4>;
 979                         clocks = <&apb1_gates 21>;
 980                         status = "disabled";
 981                 };
 982
 983                 uart6: serial@01c29800 {
 984                         compatible = "snps,dw-apb-uart";
 985                         reg = <0x01c29800 0x400>;
 986                         interrupts = <0 19 4>;
 987                         reg-shift = <2>;
 988                         reg-io-width = <4>;
 989                         clocks = <&apb1_gates 22>;
 990                         status = "disabled";
 991                 };
 992
 993                 uart7: serial@01c29c00 {
 994                         compatible = "snps,dw-apb-uart";
 995                         reg = <0x01c29c00 0x400>;
 996                         interrupts = <0 20 4>;
 997                         reg-shift = <2>;
 998                         reg-io-width = <4>;
 999                         clocks = <&apb1_gates 23>;
1000                         status = "disabled";
1001                 };
1002
1003                 i2c0: i2c@01c2ac00 {
1004                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1005                         reg = <0x01c2ac00 0x400>;
1006                         interrupts = <0 7 4>;
1007                         clocks = <&apb1_gates 0>;
1008                         status = "disabled";
1009                         #address-cells = <1>;
1010                         #size-cells = <0>;
1011                 };
1012
1013                 i2c1: i2c@01c2b000 {
1014                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1015                         reg = <0x01c2b000 0x400>;
1016                         interrupts = <0 8 4>;
1017                         clocks = <&apb1_gates 1>;
1018                         status = "disabled";
1019                         #address-cells = <1>;
1020                         #size-cells = <0>;
1021                 };
1022
1023                 i2c2: i2c@01c2b400 {
1024                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1025                         reg = <0x01c2b400 0x400>;
1026                         interrupts = <0 9 4>;
1027                         clocks = <&apb1_gates 2>;
1028                         status = "disabled";
1029                         #address-cells = <1>;
1030                         #size-cells = <0>;
1031                 };
1032
1033                 i2c3: i2c@01c2b800 {
1034                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1035                         reg = <0x01c2b800 0x400>;
1036                         interrupts = <0 88 4>;
1037                         clocks = <&apb1_gates 3>;
1038                         status = "disabled";
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041                 };
1042
1043                 i2c4: i2c@01c2c000 {
1044                         compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
1045                         reg = <0x01c2c000 0x400>;
1046                         interrupts = <0 89 4>;
1047                         clocks = <&apb1_gates 15>;
1048                         status = "disabled";
1049                         #address-cells = <1>;
1050                         #size-cells = <0>;
1051                 };
1052
1053                 gmac: ethernet@01c50000 {
1054                         compatible = "allwinner,sun7i-a20-gmac";
1055                         reg = <0x01c50000 0x10000>;
1056                         interrupts = <0 85 4>;
1057                         interrupt-names = "macirq";
1058                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1059                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1060                         snps,pbl = <2>;
1061                         snps,fixed-burst;
1062                         snps,force_sf_dma_mode;
1063                         status = "disabled";
1064                         #address-cells = <1>;
1065                         #size-cells = <0>;
1066                 };
1067
1068                 hstimer@01c60000 {
1069                         compatible = "allwinner,sun7i-a20-hstimer";
1070                         reg = <0x01c60000 0x1000>;
1071                         interrupts = <0 81 4>,
1072                                      <0 82 4>,
1073                                      <0 83 4>,
1074                                      <0 84 4>;
1075                         clocks = <&ahb_gates 28>;
1076                 };
1077
1078                 gic: interrupt-controller@01c81000 {
1079                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1080                         reg = <0x01c81000 0x1000>,
1081                               <0x01c82000 0x1000>,
1082                               <0x01c84000 0x2000>,
1083                               <0x01c86000 0x2000>;
1084                         interrupt-controller;
1085                         #interrupt-cells = <3>;
1086                         interrupts = <1 9 0xf04>;
1087                 };
1088         };
1089 };