arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/dma/sun4i-a10.h>
  48 #include <dt-bindings/pinctrl/sun4i-a10.h>
  49
  50 / {
  51         interrupt-parent = <&intc>;
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a8";
  60                         reg = <0x0>;
  61                         clocks = <&cpu>;
  62                 };
  63         };
  64
  65         clocks {
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68                 ranges;
  69
  70                 /*
  71                  * This is a dummy clock, to be used as placeholder on
  72                  * other mux clocks when a specific parent clock is not
  73                  * yet implemented. It should be dropped when the driver
  74                  * is complete.
  75                  */
  76                 dummy: dummy {
  77                         #clock-cells = <0>;
  78                         compatible = "fixed-clock";
  79                         clock-frequency = <0>;
  80                 };
  81
  82                 osc24M: clk@01c20050 {
  83                         #clock-cells = <0>;
  84                         compatible = "allwinner,sun4i-a10-osc-clk";
  85                         reg = <0x01c20050 0x4>;
  86                         clock-frequency = <24000000>;
  87                         clock-output-names = "osc24M";
  88                 };
  89
  90                 osc32k: clk@0 {
  91                         #clock-cells = <0>;
  92                         compatible = "fixed-clock";
  93                         clock-frequency = <32768>;
  94                         clock-output-names = "osc32k";
  95                 };
  96
  97                 pll1: clk@01c20000 {
  98                         #clock-cells = <0>;
  99                         compatible = "allwinner,sun4i-a10-pll1-clk";
 100                         reg = <0x01c20000 0x4>;
 101                         clocks = <&osc24M>;
 102                         clock-output-names = "pll1";
 103                 };
 104
 105                 pll4: clk@01c20018 {
 106                         #clock-cells = <0>;
 107                         compatible = "allwinner,sun4i-a10-pll1-clk";
 108                         reg = <0x01c20018 0x4>;
 109                         clocks = <&osc24M>;
 110                         clock-output-names = "pll4";
 111                 };
 112
 113                 pll5: clk@01c20020 {
 114                         #clock-cells = <1>;
 115                         compatible = "allwinner,sun4i-a10-pll5-clk";
 116                         reg = <0x01c20020 0x4>;
 117                         clocks = <&osc24M>;
 118                         clock-output-names = "pll5_ddr", "pll5_other";
 119                 };
 120
 121                 pll6: clk@01c20028 {
 122                         #clock-cells = <1>;
 123                         compatible = "allwinner,sun4i-a10-pll6-clk";
 124                         reg = <0x01c20028 0x4>;
 125                         clocks = <&osc24M>;
 126                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 127                 };
 128
 129                 /* dummy is 200M */
 130                 cpu: cpu@01c20054 {
 131                         #clock-cells = <0>;
 132                         compatible = "allwinner,sun4i-a10-cpu-clk";
 133                         reg = <0x01c20054 0x4>;
 134                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 135                         clock-output-names = "cpu";
 136                 };
 137
 138                 axi: axi@01c20054 {
 139                         #clock-cells = <0>;
 140                         compatible = "allwinner,sun4i-a10-axi-clk";
 141                         reg = <0x01c20054 0x4>;
 142                         clocks = <&cpu>;
 143                         clock-output-names = "axi";
 144                 };
 145
 146                 ahb: ahb@01c20054 {
 147                         #clock-cells = <0>;
 148                         compatible = "allwinner,sun5i-a13-ahb-clk";
 149                         reg = <0x01c20054 0x4>;
 150                         clocks = <&axi>, <&cpu>, <&pll6 1>;
 151                         clock-output-names = "ahb";
 152                         /*
 153                          * Use PLL6 as parent, instead of CPU/AXI
 154                          * which has rate changes due to cpufreq
 155                          */
 156                         assigned-clocks = <&ahb>;
 157                         assigned-clock-parents = <&pll6 1>;
 158                 };
 159
 160                 apb0: apb0@01c20054 {
 161                         #clock-cells = <0>;
 162                         compatible = "allwinner,sun4i-a10-apb0-clk";
 163                         reg = <0x01c20054 0x4>;
 164                         clocks = <&ahb>;
 165                         clock-output-names = "apb0";
 166                 };
 167
 168                 apb1: clk@01c20058 {
 169                         #clock-cells = <0>;
 170                         compatible = "allwinner,sun4i-a10-apb1-clk";
 171                         reg = <0x01c20058 0x4>;
 172                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 173                         clock-output-names = "apb1";
 174                 };
 175
 176                 axi_gates: clk@01c2005c {
 177                         #clock-cells = <1>;
 178                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 179                         reg = <0x01c2005c 0x4>;
 180                         clocks = <&axi>;
 181                         clock-output-names = "axi_dram";
 182                 };
 183
 184                 nand_clk: clk@01c20080 {
 185                         #clock-cells = <0>;
 186                         compatible = "allwinner,sun4i-a10-mod0-clk";
 187                         reg = <0x01c20080 0x4>;
 188                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 189                         clock-output-names = "nand";
 190                 };
 191
 192                 ms_clk: clk@01c20084 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun4i-a10-mod0-clk";
 195                         reg = <0x01c20084 0x4>;
 196                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 197                         clock-output-names = "ms";
 198                 };
 199
 200                 mmc0_clk: clk@01c20088 {
 201                         #clock-cells = <1>;
 202                         compatible = "allwinner,sun4i-a10-mmc-clk";
 203                         reg = <0x01c20088 0x4>;
 204                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 205                         clock-output-names = "mmc0",
 206                                              "mmc0_output",
 207                                              "mmc0_sample";
 208                 };
 209
 210                 mmc1_clk: clk@01c2008c {
 211                         #clock-cells = <1>;
 212                         compatible = "allwinner,sun4i-a10-mmc-clk";
 213                         reg = <0x01c2008c 0x4>;
 214                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 215                         clock-output-names = "mmc1",
 216                                              "mmc1_output",
 217                                              "mmc1_sample";
 218                 };
 219
 220                 mmc2_clk: clk@01c20090 {
 221                         #clock-cells = <1>;
 222                         compatible = "allwinner,sun4i-a10-mmc-clk";
 223                         reg = <0x01c20090 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "mmc2",
 226                                              "mmc2_output",
 227                                              "mmc2_sample";
 228                 };
 229
 230                 ts_clk: clk@01c20098 {
 231                         #clock-cells = <0>;
 232                         compatible = "allwinner,sun4i-a10-mod0-clk";
 233                         reg = <0x01c20098 0x4>;
 234                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 235                         clock-output-names = "ts";
 236                 };
 237
 238                 ss_clk: clk@01c2009c {
 239                         #clock-cells = <0>;
 240                         compatible = "allwinner,sun4i-a10-mod0-clk";
 241                         reg = <0x01c2009c 0x4>;
 242                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 243                         clock-output-names = "ss";
 244                 };
 245
 246                 spi0_clk: clk@01c200a0 {
 247                         #clock-cells = <0>;
 248                         compatible = "allwinner,sun4i-a10-mod0-clk";
 249                         reg = <0x01c200a0 0x4>;
 250                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 251                         clock-output-names = "spi0";
 252                 };
 253
 254                 spi1_clk: clk@01c200a4 {
 255                         #clock-cells = <0>;
 256                         compatible = "allwinner,sun4i-a10-mod0-clk";
 257                         reg = <0x01c200a4 0x4>;
 258                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 259                         clock-output-names = "spi1";
 260                 };
 261
 262                 spi2_clk: clk@01c200a8 {
 263                         #clock-cells = <0>;
 264                         compatible = "allwinner,sun4i-a10-mod0-clk";
 265                         reg = <0x01c200a8 0x4>;
 266                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 267                         clock-output-names = "spi2";
 268                 };
 269
 270                 ir0_clk: clk@01c200b0 {
 271                         #clock-cells = <0>;
 272                         compatible = "allwinner,sun4i-a10-mod0-clk";
 273                         reg = <0x01c200b0 0x4>;
 274                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 275                         clock-output-names = "ir0";
 276                 };
 277
 278                 usb_clk: clk@01c200cc {
 279                         #clock-cells = <1>;
 280                         #reset-cells = <1>;
 281                         compatible = "allwinner,sun5i-a13-usb-clk";
 282                         reg = <0x01c200cc 0x4>;
 283                         clocks = <&pll6 1>;
 284                         clock-output-names = "usb_ohci0", "usb_phy";
 285                 };
 286
 287                 mbus_clk: clk@01c2015c {
 288                         #clock-cells = <0>;
 289                         compatible = "allwinner,sun5i-a13-mbus-clk";
 290                         reg = <0x01c2015c 0x4>;
 291                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 292                         clock-output-names = "mbus";
 293                 };
 294         };
 295
 296         soc@01c00000 {
 297                 compatible = "simple-bus";
 298                 #address-cells = <1>;
 299                 #size-cells = <1>;
 300                 ranges;
 301
 302                 sram-controller@01c00000 {
 303                         compatible = "allwinner,sun4i-a10-sram-controller";
 304                         reg = <0x01c00000 0x30>;
 305                         #address-cells = <1>;
 306                         #size-cells = <1>;
 307                         ranges;
 308
 309                         sram_a: sram@00000000 {
 310                                 compatible = "mmio-sram";
 311                                 reg = <0x00000000 0xc000>;
 312                                 #address-cells = <1>;
 313                                 #size-cells = <1>;
 314                                 ranges = <0 0x00000000 0xc000>;
 315                         };
 316
 317                         sram_d: sram@00010000 {
 318                                 compatible = "mmio-sram";
 319                                 reg = <0x00010000 0x1000>;
 320                                 #address-cells = <1>;
 321                                 #size-cells = <1>;
 322                                 ranges = <0 0x00010000 0x1000>;
 323
 324                                 otg_sram: sram-section@0000 {
 325                                         compatible = "allwinner,sun4i-a10-sram-d";
 326                                         reg = <0x0000 0x1000>;
 327                                         status = "disabled";
 328                                 };
 329                         };
 330                 };
 331
 332                 dma: dma-controller@01c02000 {
 333                         compatible = "allwinner,sun4i-a10-dma";
 334                         reg = <0x01c02000 0x1000>;
 335                         interrupts = <27>;
 336                         clocks = <&ahb_gates 6>;
 337                         #dma-cells = <2>;
 338                 };
 339
 340                 spi0: spi@01c05000 {
 341                         compatible = "allwinner,sun4i-a10-spi";
 342                         reg = <0x01c05000 0x1000>;
 343                         interrupts = <10>;
 344                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 345                         clock-names = "ahb", "mod";
 346                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 347                                <&dma SUN4I_DMA_DEDICATED 26>;
 348                         dma-names = "rx", "tx";
 349                         status = "disabled";
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                 };
 353
 354                 spi1: spi@01c06000 {
 355                         compatible = "allwinner,sun4i-a10-spi";
 356                         reg = <0x01c06000 0x1000>;
 357                         interrupts = <11>;
 358                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 359                         clock-names = "ahb", "mod";
 360                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 361                                <&dma SUN4I_DMA_DEDICATED 8>;
 362                         dma-names = "rx", "tx";
 363                         status = "disabled";
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                 };
 367
 368                 mmc0: mmc@01c0f000 {
 369                         compatible = "allwinner,sun5i-a13-mmc";
 370                         reg = <0x01c0f000 0x1000>;
 371                         clocks = <&ahb_gates 8>,
 372                                  <&mmc0_clk 0>,
 373                                  <&mmc0_clk 1>,
 374                                  <&mmc0_clk 2>;
 375                         clock-names = "ahb",
 376                                       "mmc",
 377                                       "output",
 378                                       "sample";
 379                         interrupts = <32>;
 380                         status = "disabled";
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                 };
 384
 385                 mmc1: mmc@01c10000 {
 386                         compatible = "allwinner,sun5i-a13-mmc";
 387                         reg = <0x01c10000 0x1000>;
 388                         clocks = <&ahb_gates 9>,
 389                                  <&mmc1_clk 0>,
 390                                  <&mmc1_clk 1>,
 391                                  <&mmc1_clk 2>;
 392                         clock-names = "ahb",
 393                                       "mmc",
 394                                       "output",
 395                                       "sample";
 396                         interrupts = <33>;
 397                         status = "disabled";
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                 };
 401
 402                 mmc2: mmc@01c11000 {
 403                         compatible = "allwinner,sun5i-a13-mmc";
 404                         reg = <0x01c11000 0x1000>;
 405                         clocks = <&ahb_gates 10>,
 406                                  <&mmc2_clk 0>,
 407                                  <&mmc2_clk 1>,
 408                                  <&mmc2_clk 2>;
 409                         clock-names = "ahb",
 410                                       "mmc",
 411                                       "output",
 412                                       "sample";
 413                         interrupts = <34>;
 414                         status = "disabled";
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                 };
 418
 419                 usbphy: phy@01c13400 {
 420                         #phy-cells = <1>;
 421                         compatible = "allwinner,sun5i-a13-usb-phy";
 422                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 423                         reg-names = "phy_ctrl", "pmu1";
 424                         clocks = <&usb_clk 8>;
 425                         clock-names = "usb_phy";
 426                         resets = <&usb_clk 0>, <&usb_clk 1>;
 427                         reset-names = "usb0_reset", "usb1_reset";
 428                         status = "disabled";
 429                 };
 430
 431                 ehci0: usb@01c14000 {
 432                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 433                         reg = <0x01c14000 0x100>;
 434                         interrupts = <39>;
 435                         clocks = <&ahb_gates 1>;
 436                         phys = <&usbphy 1>;
 437                         phy-names = "usb";
 438                         status = "disabled";
 439                 };
 440
 441                 ohci0: usb@01c14400 {
 442                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 443                         reg = <0x01c14400 0x100>;
 444                         interrupts = <40>;
 445                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 446                         phys = <&usbphy 1>;
 447                         phy-names = "usb";
 448                         status = "disabled";
 449                 };
 450
 451                 spi2: spi@01c17000 {
 452                         compatible = "allwinner,sun4i-a10-spi";
 453                         reg = <0x01c17000 0x1000>;
 454                         interrupts = <12>;
 455                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 456                         clock-names = "ahb", "mod";
 457                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 458                                <&dma SUN4I_DMA_DEDICATED 28>;
 459                         dma-names = "rx", "tx";
 460                         status = "disabled";
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                 };
 464
 465                 intc: interrupt-controller@01c20400 {
 466                         compatible = "allwinner,sun4i-a10-ic";
 467                         reg = <0x01c20400 0x400>;
 468                         interrupt-controller;
 469                         #interrupt-cells = <1>;
 470                 };
 471
 472                 pio: pinctrl@01c20800 {
 473                         reg = <0x01c20800 0x400>;
 474                         interrupts = <28>;
 475                         clocks = <&apb0_gates 5>;
 476                         gpio-controller;
 477                         interrupt-controller;
 478                         #interrupt-cells = <2>;
 479                         #size-cells = <0>;
 480                         #gpio-cells = <3>;
 481
 482                         i2c0_pins_a: i2c0@0 {
 483                                 allwinner,pins = "PB0", "PB1";
 484                                 allwinner,function = "i2c0";
 485                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 486                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 487                         };
 488
 489                         i2c1_pins_a: i2c1@0 {
 490                                 allwinner,pins = "PB15", "PB16";
 491                                 allwinner,function = "i2c1";
 492                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 493                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 494                         };
 495
 496                         i2c2_pins_a: i2c2@0 {
 497                                 allwinner,pins = "PB17", "PB18";
 498                                 allwinner,function = "i2c2";
 499                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 500                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 501                         };
 502
 503                         mmc0_pins_a: mmc0@0 {
 504                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 505                                                  "PF4", "PF5";
 506                                 allwinner,function = "mmc0";
 507                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 508                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 509                         };
 510
 511                         mmc2_pins_a: mmc2@0 {
 512                                 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 513                                         "PC10", "PC11", "PC12", "PC13",
 514                                         "PC14", "PC15";
 515                                 allwinner,function = "mmc2";
 516                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 517                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 518                         };
 519                 };
 520
 521                 timer@01c20c00 {
 522                         compatible = "allwinner,sun4i-a10-timer";
 523                         reg = <0x01c20c00 0x90>;
 524                         interrupts = <22>;
 525                         clocks = <&osc24M>;
 526                 };
 527
 528                 wdt: watchdog@01c20c90 {
 529                         compatible = "allwinner,sun4i-a10-wdt";
 530                         reg = <0x01c20c90 0x10>;
 531                 };
 532
 533                 lradc: lradc@01c22800 {
 534                         compatible = "allwinner,sun4i-a10-lradc-keys";
 535                         reg = <0x01c22800 0x100>;
 536                         interrupts = <31>;
 537                         status = "disabled";
 538                 };
 539
 540                 sid: eeprom@01c23800 {
 541                         compatible = "allwinner,sun4i-a10-sid";
 542                         reg = <0x01c23800 0x10>;
 543                 };
 544
 545                 rtp: rtp@01c25000 {
 546                         compatible = "allwinner,sun5i-a13-ts";
 547                         reg = <0x01c25000 0x100>;
 548                         interrupts = <29>;
 549                         #thermal-sensor-cells = <0>;
 550                 };
 551
 552                 uart1: serial@01c28400 {
 553                         compatible = "snps,dw-apb-uart";
 554                         reg = <0x01c28400 0x400>;
 555                         interrupts = <2>;
 556                         reg-shift = <2>;
 557                         reg-io-width = <4>;
 558                         clocks = <&apb1_gates 17>;
 559                         status = "disabled";
 560                 };
 561
 562                 uart3: serial@01c28c00 {
 563                         compatible = "snps,dw-apb-uart";
 564                         reg = <0x01c28c00 0x400>;
 565                         interrupts = <4>;
 566                         reg-shift = <2>;
 567                         reg-io-width = <4>;
 568                         clocks = <&apb1_gates 19>;
 569                         status = "disabled";
 570                 };
 571
 572                 i2c0: i2c@01c2ac00 {
 573                         compatible = "allwinner,sun4i-a10-i2c";
 574                         reg = <0x01c2ac00 0x400>;
 575                         interrupts = <7>;
 576                         clocks = <&apb1_gates 0>;
 577                         status = "disabled";
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                 };
 581
 582                 i2c1: i2c@01c2b000 {
 583                         compatible = "allwinner,sun4i-a10-i2c";
 584                         reg = <0x01c2b000 0x400>;
 585                         interrupts = <8>;
 586                         clocks = <&apb1_gates 1>;
 587                         status = "disabled";
 588                         #address-cells = <1>;
 589                         #size-cells = <0>;
 590                 };
 591
 592                 i2c2: i2c@01c2b400 {
 593                         compatible = "allwinner,sun4i-a10-i2c";
 594                         reg = <0x01c2b400 0x400>;
 595                         interrupts = <9>;
 596                         clocks = <&apb1_gates 2>;
 597                         status = "disabled";
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                 };
 601
 602                 timer@01c60000 {
 603                         compatible = "allwinner,sun5i-a13-hstimer";
 604                         reg = <0x01c60000 0x1000>;
 605                         interrupts = <82>, <83>;
 606                         clocks = <&ahb_gates 28>;
 607                 };
 608         };
 609 };