arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22                 cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a8";
  25                         reg = <0x0>;
  26                 };
  27         };
  28
  29         memory {
  30                 reg = <0x40000000 0x20000000>;
  31         };
  32
  33         clocks {
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges;
  37
  38                 /*
  39                  * This is a dummy clock, to be used as placeholder on
  40                  * other mux clocks when a specific parent clock is not
  41                  * yet implemented. It should be dropped when the driver
  42                  * is complete.
  43                  */
  44                 dummy: dummy {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <0>;
  48                 };
  49
  50                 osc24M: clk@01c20050 {
  51                         #clock-cells = <0>;
  52                         compatible = "allwinner,sun4i-a10-osc-clk";
  53                         reg = <0x01c20050 0x4>;
  54                         clock-frequency = <24000000>;
  55                         clock-output-names = "osc24M";
  56                 };
  57
  58                 osc32k: clk@0 {
  59                         #clock-cells = <0>;
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <32768>;
  62                         clock-output-names = "osc32k";
  63                 };
  64
  65                 pll1: clk@01c20000 {
  66                         #clock-cells = <0>;
  67                         compatible = "allwinner,sun4i-a10-pll1-clk";
  68                         reg = <0x01c20000 0x4>;
  69                         clocks = <&osc24M>;
  70                         clock-output-names = "pll1";
  71                 };
  72
  73                 pll4: clk@01c20018 {
  74                         #clock-cells = <0>;
  75                         compatible = "allwinner,sun4i-a10-pll1-clk";
  76                         reg = <0x01c20018 0x4>;
  77                         clocks = <&osc24M>;
  78                         clock-output-names = "pll4";
  79                 };
  80
  81                 pll5: clk@01c20020 {
  82                         #clock-cells = <1>;
  83                         compatible = "allwinner,sun4i-a10-pll5-clk";
  84                         reg = <0x01c20020 0x4>;
  85                         clocks = <&osc24M>;
  86                         clock-output-names = "pll5_ddr", "pll5_other";
  87                 };
  88
  89                 pll6: clk@01c20028 {
  90                         #clock-cells = <1>;
  91                         compatible = "allwinner,sun4i-a10-pll6-clk";
  92                         reg = <0x01c20028 0x4>;
  93                         clocks = <&osc24M>;
  94                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  95                 };
  96
  97                 /* dummy is 200M */
  98                 cpu: cpu@01c20054 {
  99                         #clock-cells = <0>;
 100                         compatible = "allwinner,sun4i-a10-cpu-clk";
 101                         reg = <0x01c20054 0x4>;
 102                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 103                         clock-output-names = "cpu";
 104                 };
 105
 106                 axi: axi@01c20054 {
 107                         #clock-cells = <0>;
 108                         compatible = "allwinner,sun4i-a10-axi-clk";
 109                         reg = <0x01c20054 0x4>;
 110                         clocks = <&cpu>;
 111                         clock-output-names = "axi";
 112                 };
 113
 114                 axi_gates: clk@01c2005c {
 115                         #clock-cells = <1>;
 116                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 117                         reg = <0x01c2005c 0x4>;
 118                         clocks = <&axi>;
 119                         clock-output-names = "axi_dram";
 120                 };
 121
 122                 ahb: ahb@01c20054 {
 123                         #clock-cells = <0>;
 124                         compatible = "allwinner,sun4i-a10-ahb-clk";
 125                         reg = <0x01c20054 0x4>;
 126                         clocks = <&axi>;
 127                         clock-output-names = "ahb";
 128                 };
 129
 130                 ahb_gates: clk@01c20060 {
 131                         #clock-cells = <1>;
 132                         compatible = "allwinner,sun5i-a13-ahb-gates-clk";
 133                         reg = <0x01c20060 0x8>;
 134                         clocks = <&ahb>;
 135                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 136                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 137                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 138                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
 139                                 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
 140                                 "ahb_de_fe", "ahb_iep", "ahb_mali400";
 141                 };
 142
 143                 apb0: apb0@01c20054 {
 144                         #clock-cells = <0>;
 145                         compatible = "allwinner,sun4i-a10-apb0-clk";
 146                         reg = <0x01c20054 0x4>;
 147                         clocks = <&ahb>;
 148                         clock-output-names = "apb0";
 149                 };
 150
 151                 apb0_gates: clk@01c20068 {
 152                         #clock-cells = <1>;
 153                         compatible = "allwinner,sun5i-a13-apb0-gates-clk";
 154                         reg = <0x01c20068 0x4>;
 155                         clocks = <&apb0>;
 156                         clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
 157                 };
 158
 159                 apb1: clk@01c20058 {
 160                         #clock-cells = <0>;
 161                         compatible = "allwinner,sun4i-a10-apb1-clk";
 162                         reg = <0x01c20058 0x4>;
 163                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 164                         clock-output-names = "apb1";
 165                 };
 166
 167                 apb1_gates: clk@01c2006c {
 168                         #clock-cells = <1>;
 169                         compatible = "allwinner,sun5i-a13-apb1-gates-clk";
 170                         reg = <0x01c2006c 0x4>;
 171                         clocks = <&apb1>;
 172                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 173                                 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
 174                 };
 175
 176                 nand_clk: clk@01c20080 {
 177                         #clock-cells = <0>;
 178                         compatible = "allwinner,sun4i-a10-mod0-clk";
 179                         reg = <0x01c20080 0x4>;
 180                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 181                         clock-output-names = "nand";
 182                 };
 183
 184                 ms_clk: clk@01c20084 {
 185                         #clock-cells = <0>;
 186                         compatible = "allwinner,sun4i-a10-mod0-clk";
 187                         reg = <0x01c20084 0x4>;
 188                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 189                         clock-output-names = "ms";
 190                 };
 191
 192                 mmc0_clk: clk@01c20088 {
 193                         #clock-cells = <0>;
 194                         compatible = "allwinner,sun4i-a10-mod0-clk";
 195                         reg = <0x01c20088 0x4>;
 196                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 197                         clock-output-names = "mmc0";
 198                 };
 199
 200                 mmc1_clk: clk@01c2008c {
 201                         #clock-cells = <0>;
 202                         compatible = "allwinner,sun4i-a10-mod0-clk";
 203                         reg = <0x01c2008c 0x4>;
 204                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 205                         clock-output-names = "mmc1";
 206                 };
 207
 208                 mmc2_clk: clk@01c20090 {
 209                         #clock-cells = <0>;
 210                         compatible = "allwinner,sun4i-a10-mod0-clk";
 211                         reg = <0x01c20090 0x4>;
 212                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 213                         clock-output-names = "mmc2";
 214                 };
 215
 216                 ts_clk: clk@01c20098 {
 217                         #clock-cells = <0>;
 218                         compatible = "allwinner,sun4i-a10-mod0-clk";
 219                         reg = <0x01c20098 0x4>;
 220                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 221                         clock-output-names = "ts";
 222                 };
 223
 224                 ss_clk: clk@01c2009c {
 225                         #clock-cells = <0>;
 226                         compatible = "allwinner,sun4i-a10-mod0-clk";
 227                         reg = <0x01c2009c 0x4>;
 228                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 229                         clock-output-names = "ss";
 230                 };
 231
 232                 spi0_clk: clk@01c200a0 {
 233                         #clock-cells = <0>;
 234                         compatible = "allwinner,sun4i-a10-mod0-clk";
 235                         reg = <0x01c200a0 0x4>;
 236                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 237                         clock-output-names = "spi0";
 238                 };
 239
 240                 spi1_clk: clk@01c200a4 {
 241                         #clock-cells = <0>;
 242                         compatible = "allwinner,sun4i-a10-mod0-clk";
 243                         reg = <0x01c200a4 0x4>;
 244                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 245                         clock-output-names = "spi1";
 246                 };
 247
 248                 spi2_clk: clk@01c200a8 {
 249                         #clock-cells = <0>;
 250                         compatible = "allwinner,sun4i-a10-mod0-clk";
 251                         reg = <0x01c200a8 0x4>;
 252                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 253                         clock-output-names = "spi2";
 254                 };
 255
 256                 ir0_clk: clk@01c200b0 {
 257                         #clock-cells = <0>;
 258                         compatible = "allwinner,sun4i-a10-mod0-clk";
 259                         reg = <0x01c200b0 0x4>;
 260                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 261                         clock-output-names = "ir0";
 262                 };
 263
 264                 usb_clk: clk@01c200cc {
 265                         #clock-cells = <1>;
 266                         #reset-cells = <1>;
 267                         compatible = "allwinner,sun5i-a13-usb-clk";
 268                         reg = <0x01c200cc 0x4>;
 269                         clocks = <&pll6 1>;
 270                         clock-output-names = "usb_ohci0", "usb_phy";
 271                 };
 272
 273                 mbus_clk: clk@01c2015c {
 274                         #clock-cells = <0>;
 275                         compatible = "allwinner,sun5i-a13-mbus-clk";
 276                         reg = <0x01c2015c 0x4>;
 277                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 278                         clock-output-names = "mbus";
 279                 };
 280         };
 281
 282         soc@01c00000 {
 283                 compatible = "simple-bus";
 284                 #address-cells = <1>;
 285                 #size-cells = <1>;
 286                 ranges;
 287
 288                 dma: dma-controller@01c02000 {
 289                         compatible = "allwinner,sun4i-a10-dma";
 290                         reg = <0x01c02000 0x1000>;
 291                         interrupts = <27>;
 292                         clocks = <&ahb_gates 6>;
 293                         #dma-cells = <2>;
 294                 };
 295
 296                 spi0: spi@01c05000 {
 297                         compatible = "allwinner,sun4i-a10-spi";
 298                         reg = <0x01c05000 0x1000>;
 299                         interrupts = <10>;
 300                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 301                         clock-names = "ahb", "mod";
 302                         dmas = <&dma 1 27>, <&dma 1 26>;
 303                         dma-names = "rx", "tx";
 304                         status = "disabled";
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                 };
 308
 309                 spi1: spi@01c06000 {
 310                         compatible = "allwinner,sun4i-a10-spi";
 311                         reg = <0x01c06000 0x1000>;
 312                         interrupts = <11>;
 313                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 314                         clock-names = "ahb", "mod";
 315                         dmas = <&dma 1 9>, <&dma 1 8>;
 316                         dma-names = "rx", "tx";
 317                         status = "disabled";
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                 };
 321
 322                 mmc0: mmc@01c0f000 {
 323                         compatible = "allwinner,sun5i-a13-mmc";
 324                         reg = <0x01c0f000 0x1000>;
 325                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 326                         clock-names = "ahb", "mmc";
 327                         interrupts = <32>;
 328                         status = "disabled";
 329                 };
 330
 331                 mmc2: mmc@01c11000 {
 332                         compatible = "allwinner,sun5i-a13-mmc";
 333                         reg = <0x01c11000 0x1000>;
 334                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 335                         clock-names = "ahb", "mmc";
 336                         interrupts = <34>;
 337                         status = "disabled";
 338                 };
 339
 340                 usbphy: phy@01c13400 {
 341                         #phy-cells = <1>;
 342                         compatible = "allwinner,sun5i-a13-usb-phy";
 343                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 344                         reg-names = "phy_ctrl", "pmu1";
 345                         clocks = <&usb_clk 8>;
 346                         clock-names = "usb_phy";
 347                         resets = <&usb_clk 0>, <&usb_clk 1>;
 348                         reset-names = "usb0_reset", "usb1_reset";
 349                         status = "disabled";
 350                 };
 351
 352                 ehci0: usb@01c14000 {
 353                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 354                         reg = <0x01c14000 0x100>;
 355                         interrupts = <39>;
 356                         clocks = <&ahb_gates 1>;
 357                         phys = <&usbphy 1>;
 358                         phy-names = "usb";
 359                         status = "disabled";
 360                 };
 361
 362                 ohci0: usb@01c14400 {
 363                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 364                         reg = <0x01c14400 0x100>;
 365                         interrupts = <40>;
 366                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 367                         phys = <&usbphy 1>;
 368                         phy-names = "usb";
 369                         status = "disabled";
 370                 };
 371
 372                 spi2: spi@01c17000 {
 373                         compatible = "allwinner,sun4i-a10-spi";
 374                         reg = <0x01c17000 0x1000>;
 375                         interrupts = <12>;
 376                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 377                         clock-names = "ahb", "mod";
 378                         dmas = <&dma 1 29>, <&dma 1 28>;
 379                         dma-names = "rx", "tx";
 380                         status = "disabled";
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                 };
 384
 385                 intc: interrupt-controller@01c20400 {
 386                         compatible = "allwinner,sun4i-a10-ic";
 387                         reg = <0x01c20400 0x400>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <1>;
 390                 };
 391
 392                 pio: pinctrl@01c20800 {
 393                         compatible = "allwinner,sun5i-a13-pinctrl";
 394                         reg = <0x01c20800 0x400>;
 395                         interrupts = <28>;
 396                         clocks = <&apb0_gates 5>;
 397                         gpio-controller;
 398                         interrupt-controller;
 399                         #interrupt-cells = <2>;
 400                         #size-cells = <0>;
 401                         #gpio-cells = <3>;
 402
 403                         uart1_pins_a: uart1@0 {
 404                                 allwinner,pins = "PE10", "PE11";
 405                                 allwinner,function = "uart1";
 406                                 allwinner,drive = <0>;
 407                                 allwinner,pull = <0>;
 408                         };
 409
 410                         uart1_pins_b: uart1@1 {
 411                                 allwinner,pins = "PG3", "PG4";
 412                                 allwinner,function = "uart1";
 413                                 allwinner,drive = <0>;
 414                                 allwinner,pull = <0>;
 415                         };
 416
 417                         i2c0_pins_a: i2c0@0 {
 418                                 allwinner,pins = "PB0", "PB1";
 419                                 allwinner,function = "i2c0";
 420                                 allwinner,drive = <0>;
 421                                 allwinner,pull = <0>;
 422                         };
 423
 424                         i2c1_pins_a: i2c1@0 {
 425                                 allwinner,pins = "PB15", "PB16";
 426                                 allwinner,function = "i2c1";
 427                                 allwinner,drive = <0>;
 428                                 allwinner,pull = <0>;
 429                         };
 430
 431                         i2c2_pins_a: i2c2@0 {
 432                                 allwinner,pins = "PB17", "PB18";
 433                                 allwinner,function = "i2c2";
 434                                 allwinner,drive = <0>;
 435                                 allwinner,pull = <0>;
 436                         };
 437
 438                         mmc0_pins_a: mmc0@0 {
 439                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 440                                 allwinner,function = "mmc0";
 441                                 allwinner,drive = <2>;
 442                                 allwinner,pull = <0>;
 443                         };
 444                 };
 445
 446                 timer@01c20c00 {
 447                         compatible = "allwinner,sun4i-a10-timer";
 448                         reg = <0x01c20c00 0x90>;
 449                         interrupts = <22>;
 450                         clocks = <&osc24M>;
 451                 };
 452
 453                 wdt: watchdog@01c20c90 {
 454                         compatible = "allwinner,sun4i-a10-wdt";
 455                         reg = <0x01c20c90 0x10>;
 456                 };
 457
 458                 sid: eeprom@01c23800 {
 459                         compatible = "allwinner,sun4i-a10-sid";
 460                         reg = <0x01c23800 0x10>;
 461                 };
 462
 463                 rtp: rtp@01c25000 {
 464                         compatible = "allwinner,sun4i-a10-ts";
 465                         reg = <0x01c25000 0x100>;
 466                         interrupts = <29>;
 467                 };
 468
 469                 uart1: serial@01c28400 {
 470                         compatible = "snps,dw-apb-uart";
 471                         reg = <0x01c28400 0x400>;
 472                         interrupts = <2>;
 473                         reg-shift = <2>;
 474                         reg-io-width = <4>;
 475                         clocks = <&apb1_gates 17>;
 476                         status = "disabled";
 477                 };
 478
 479                 uart3: serial@01c28c00 {
 480                         compatible = "snps,dw-apb-uart";
 481                         reg = <0x01c28c00 0x400>;
 482                         interrupts = <4>;
 483                         reg-shift = <2>;
 484                         reg-io-width = <4>;
 485                         clocks = <&apb1_gates 19>;
 486                         status = "disabled";
 487                 };
 488
 489                 i2c0: i2c@01c2ac00 {
 490                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 491                         reg = <0x01c2ac00 0x400>;
 492                         interrupts = <7>;
 493                         clocks = <&apb1_gates 0>;
 494                         status = "disabled";
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                 };
 498
 499                 i2c1: i2c@01c2b000 {
 500                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 501                         reg = <0x01c2b000 0x400>;
 502                         interrupts = <8>;
 503                         clocks = <&apb1_gates 1>;
 504                         status = "disabled";
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507                 };
 508
 509                 i2c2: i2c@01c2b400 {
 510                         compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
 511                         reg = <0x01c2b400 0x400>;
 512                         interrupts = <9>;
 513                         clocks = <&apb1_gates 2>;
 514                         status = "disabled";
 515                         #address-cells = <1>;
 516                         #size-cells = <0>;
 517                 };
 518
 519                 timer@01c60000 {
 520                         compatible = "allwinner,sun5i-a13-hstimer";
 521                         reg = <0x01c60000 0x1000>;
 522                         interrupts = <82>, <83>;
 523                         clocks = <&ahb_gates 28>;
 524                 };
 525         };
 526 };