arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         aliases {
  20                 ethernet0 = &emac;
  21         };
  22
  23         chosen {
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26                 ranges;
  27
  28                 framebuffer@0 {
  29                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  30                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  31                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  32                                  <&ahb_gates 44>;
  33                         status = "disabled";
  34                 };
  35         };
  36
  37         cpus {
  38                 cpu@0 {
  39                         compatible = "arm,cortex-a8";
  40                 };
  41         };
  42
  43         memory {
  44                 reg = <0x40000000 0x20000000>;
  45         };
  46
  47         clocks {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 ranges;
  51
  52                 /*
  53                  * This is a dummy clock, to be used as placeholder on
  54                  * other mux clocks when a specific parent clock is not
  55                  * yet implemented. It should be dropped when the driver
  56                  * is complete.
  57                  */
  58                 dummy: dummy {
  59                         #clock-cells = <0>;
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <0>;
  62                 };
  63
  64                 osc24M: clk@01c20050 {
  65                         #clock-cells = <0>;
  66                         compatible = "allwinner,sun4i-a10-osc-clk";
  67                         reg = <0x01c20050 0x4>;
  68                         clock-frequency = <24000000>;
  69                         clock-output-names = "osc24M";
  70                 };
  71
  72                 osc32k: clk@0 {
  73                         #clock-cells = <0>;
  74                         compatible = "fixed-clock";
  75                         clock-frequency = <32768>;
  76                         clock-output-names = "osc32k";
  77                 };
  78
  79                 pll1: clk@01c20000 {
  80                         #clock-cells = <0>;
  81                         compatible = "allwinner,sun4i-a10-pll1-clk";
  82                         reg = <0x01c20000 0x4>;
  83                         clocks = <&osc24M>;
  84                         clock-output-names = "pll1";
  85                 };
  86
  87                 pll4: clk@01c20018 {
  88                         #clock-cells = <0>;
  89                         compatible = "allwinner,sun4i-a10-pll1-clk";
  90                         reg = <0x01c20018 0x4>;
  91                         clocks = <&osc24M>;
  92                         clock-output-names = "pll4";
  93                 };
  94
  95                 pll5: clk@01c20020 {
  96                         #clock-cells = <1>;
  97                         compatible = "allwinner,sun4i-a10-pll5-clk";
  98                         reg = <0x01c20020 0x4>;
  99                         clocks = <&osc24M>;
 100                         clock-output-names = "pll5_ddr", "pll5_other";
 101                 };
 102
 103                 pll6: clk@01c20028 {
 104                         #clock-cells = <1>;
 105                         compatible = "allwinner,sun4i-a10-pll6-clk";
 106                         reg = <0x01c20028 0x4>;
 107                         clocks = <&osc24M>;
 108                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 109                 };
 110
 111                 /* dummy is 200M */
 112                 cpu: cpu@01c20054 {
 113                         #clock-cells = <0>;
 114                         compatible = "allwinner,sun4i-a10-cpu-clk";
 115                         reg = <0x01c20054 0x4>;
 116                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 117                         clock-output-names = "cpu";
 118                 };
 119
 120                 axi: axi@01c20054 {
 121                         #clock-cells = <0>;
 122                         compatible = "allwinner,sun4i-a10-axi-clk";
 123                         reg = <0x01c20054 0x4>;
 124                         clocks = <&cpu>;
 125                         clock-output-names = "axi";
 126                 };
 127
 128                 axi_gates: clk@01c2005c {
 129                         #clock-cells = <1>;
 130                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 131                         reg = <0x01c2005c 0x4>;
 132                         clocks = <&axi>;
 133                         clock-output-names = "axi_dram";
 134                 };
 135
 136                 ahb: ahb@01c20054 {
 137                         #clock-cells = <0>;
 138                         compatible = "allwinner,sun4i-a10-ahb-clk";
 139                         reg = <0x01c20054 0x4>;
 140                         clocks = <&axi>;
 141                         clock-output-names = "ahb";
 142                 };
 143
 144                 ahb_gates: clk@01c20060 {
 145                         #clock-cells = <1>;
 146                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 147                         reg = <0x01c20060 0x8>;
 148                         clocks = <&ahb>;
 149                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 150                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 151                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 152                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 153                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 154                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 155                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 156                 };
 157
 158                 apb0: apb0@01c20054 {
 159                         #clock-cells = <0>;
 160                         compatible = "allwinner,sun4i-a10-apb0-clk";
 161                         reg = <0x01c20054 0x4>;
 162                         clocks = <&ahb>;
 163                         clock-output-names = "apb0";
 164                 };
 165
 166                 apb0_gates: clk@01c20068 {
 167                         #clock-cells = <1>;
 168                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 169                         reg = <0x01c20068 0x4>;
 170                         clocks = <&apb0>;
 171                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 172                                 "apb0_ir", "apb0_keypad";
 173                 };
 174
 175                 apb1: clk@01c20058 {
 176                         #clock-cells = <0>;
 177                         compatible = "allwinner,sun4i-a10-apb1-clk";
 178                         reg = <0x01c20058 0x4>;
 179                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 180                         clock-output-names = "apb1";
 181                 };
 182
 183                 apb1_gates: clk@01c2006c {
 184                         #clock-cells = <1>;
 185                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 186                         reg = <0x01c2006c 0x4>;
 187                         clocks = <&apb1>;
 188                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 189                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 190                                 "apb1_uart2", "apb1_uart3";
 191                 };
 192
 193                 nand_clk: clk@01c20080 {
 194                         #clock-cells = <0>;
 195                         compatible = "allwinner,sun4i-a10-mod0-clk";
 196                         reg = <0x01c20080 0x4>;
 197                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 198                         clock-output-names = "nand";
 199                 };
 200
 201                 ms_clk: clk@01c20084 {
 202                         #clock-cells = <0>;
 203                         compatible = "allwinner,sun4i-a10-mod0-clk";
 204                         reg = <0x01c20084 0x4>;
 205                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 206                         clock-output-names = "ms";
 207                 };
 208
 209                 mmc0_clk: clk@01c20088 {
 210                         #clock-cells = <0>;
 211                         compatible = "allwinner,sun4i-a10-mod0-clk";
 212                         reg = <0x01c20088 0x4>;
 213                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 214                         clock-output-names = "mmc0";
 215                 };
 216
 217                 mmc1_clk: clk@01c2008c {
 218                         #clock-cells = <0>;
 219                         compatible = "allwinner,sun4i-a10-mod0-clk";
 220                         reg = <0x01c2008c 0x4>;
 221                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 222                         clock-output-names = "mmc1";
 223                 };
 224
 225                 mmc2_clk: clk@01c20090 {
 226                         #clock-cells = <0>;
 227                         compatible = "allwinner,sun4i-a10-mod0-clk";
 228                         reg = <0x01c20090 0x4>;
 229                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 230                         clock-output-names = "mmc2";
 231                 };
 232
 233                 ts_clk: clk@01c20098 {
 234                         #clock-cells = <0>;
 235                         compatible = "allwinner,sun4i-a10-mod0-clk";
 236                         reg = <0x01c20098 0x4>;
 237                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 238                         clock-output-names = "ts";
 239                 };
 240
 241                 ss_clk: clk@01c2009c {
 242                         #clock-cells = <0>;
 243                         compatible = "allwinner,sun4i-a10-mod0-clk";
 244                         reg = <0x01c2009c 0x4>;
 245                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 246                         clock-output-names = "ss";
 247                 };
 248
 249                 spi0_clk: clk@01c200a0 {
 250                         #clock-cells = <0>;
 251                         compatible = "allwinner,sun4i-a10-mod0-clk";
 252                         reg = <0x01c200a0 0x4>;
 253                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 254                         clock-output-names = "spi0";
 255                 };
 256
 257                 spi1_clk: clk@01c200a4 {
 258                         #clock-cells = <0>;
 259                         compatible = "allwinner,sun4i-a10-mod0-clk";
 260                         reg = <0x01c200a4 0x4>;
 261                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 262                         clock-output-names = "spi1";
 263                 };
 264
 265                 spi2_clk: clk@01c200a8 {
 266                         #clock-cells = <0>;
 267                         compatible = "allwinner,sun4i-a10-mod0-clk";
 268                         reg = <0x01c200a8 0x4>;
 269                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 270                         clock-output-names = "spi2";
 271                 };
 272
 273                 ir0_clk: clk@01c200b0 {
 274                         #clock-cells = <0>;
 275                         compatible = "allwinner,sun4i-a10-mod0-clk";
 276                         reg = <0x01c200b0 0x4>;
 277                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 278                         clock-output-names = "ir0";
 279                 };
 280
 281                 usb_clk: clk@01c200cc {
 282                         #clock-cells = <1>;
 283                         #reset-cells = <1>;
 284                         compatible = "allwinner,sun5i-a13-usb-clk";
 285                         reg = <0x01c200cc 0x4>;
 286                         clocks = <&pll6 1>;
 287                         clock-output-names = "usb_ohci0", "usb_phy";
 288                 };
 289
 290                 mbus_clk: clk@01c2015c {
 291                         #clock-cells = <0>;
 292                         compatible = "allwinner,sun5i-a13-mbus-clk";
 293                         reg = <0x01c2015c 0x4>;
 294                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 295                         clock-output-names = "mbus";
 296                 };
 297         };
 298
 299         soc@01c00000 {
 300                 compatible = "simple-bus";
 301                 #address-cells = <1>;
 302                 #size-cells = <1>;
 303                 ranges;
 304
 305                 dma: dma-controller@01c02000 {
 306                         compatible = "allwinner,sun4i-a10-dma";
 307                         reg = <0x01c02000 0x1000>;
 308                         interrupts = <27>;
 309                         clocks = <&ahb_gates 6>;
 310                         #dma-cells = <2>;
 311                 };
 312
 313                 spi0: spi@01c05000 {
 314                         compatible = "allwinner,sun4i-a10-spi";
 315                         reg = <0x01c05000 0x1000>;
 316                         interrupts = <10>;
 317                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 318                         clock-names = "ahb", "mod";
 319                         dmas = <&dma 1 27>, <&dma 1 26>;
 320                         dma-names = "rx", "tx";
 321                         status = "disabled";
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                 };
 325
 326                 spi1: spi@01c06000 {
 327                         compatible = "allwinner,sun4i-a10-spi";
 328                         reg = <0x01c06000 0x1000>;
 329                         interrupts = <11>;
 330                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 331                         clock-names = "ahb", "mod";
 332                         dmas = <&dma 1 9>, <&dma 1 8>;
 333                         dma-names = "rx", "tx";
 334                         status = "disabled";
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                 };
 338
 339                 emac: ethernet@01c0b000 {
 340                         compatible = "allwinner,sun4i-a10-emac";
 341                         reg = <0x01c0b000 0x1000>;
 342                         interrupts = <55>;
 343                         clocks = <&ahb_gates 17>;
 344                         status = "disabled";
 345                 };
 346
 347                 mdio@01c0b080 {
 348                         compatible = "allwinner,sun4i-a10-mdio";
 349                         reg = <0x01c0b080 0x14>;
 350                         status = "disabled";
 351                         #address-cells = <1>;
 352                         #size-cells = <0>;
 353                 };
 354
 355                 mmc0: mmc@01c0f000 {
 356                         compatible = "allwinner,sun5i-a13-mmc";
 357                         reg = <0x01c0f000 0x1000>;
 358                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 359                         clock-names = "ahb", "mmc";
 360                         interrupts = <32>;
 361                         status = "disabled";
 362                 };
 363
 364                 mmc1: mmc@01c10000 {
 365                         compatible = "allwinner,sun5i-a13-mmc";
 366                         reg = <0x01c10000 0x1000>;
 367                         clocks = <&ahb_gates 9>, <&mmc1_clk>;
 368                         clock-names = "ahb", "mmc";
 369                         interrupts = <33>;
 370                         status = "disabled";
 371                 };
 372
 373                 mmc2: mmc@01c11000 {
 374                         compatible = "allwinner,sun5i-a13-mmc";
 375                         reg = <0x01c11000 0x1000>;
 376                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 377                         clock-names = "ahb", "mmc";
 378                         interrupts = <34>;
 379                         status = "disabled";
 380                 };
 381
 382                 usbphy: phy@01c13400 {
 383                         #phy-cells = <1>;
 384                         compatible = "allwinner,sun5i-a13-usb-phy";
 385                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 386                         reg-names = "phy_ctrl", "pmu1";
 387                         clocks = <&usb_clk 8>;
 388                         clock-names = "usb_phy";
 389                         resets = <&usb_clk 0>, <&usb_clk 1>;
 390                         reset-names = "usb0_reset", "usb1_reset";
 391                         status = "disabled";
 392                 };
 393
 394                 ehci0: usb@01c14000 {
 395                         compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
 396                         reg = <0x01c14000 0x100>;
 397                         interrupts = <39>;
 398                         clocks = <&ahb_gates 1>;
 399                         phys = <&usbphy 1>;
 400                         phy-names = "usb";
 401                         status = "disabled";
 402                 };
 403
 404                 ohci0: usb@01c14400 {
 405                         compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
 406                         reg = <0x01c14400 0x100>;
 407                         interrupts = <40>;
 408                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 409                         phys = <&usbphy 1>;
 410                         phy-names = "usb";
 411                         status = "disabled";
 412                 };
 413
 414                 spi2: spi@01c17000 {
 415                         compatible = "allwinner,sun4i-a10-spi";
 416                         reg = <0x01c17000 0x1000>;
 417                         interrupts = <12>;
 418                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 419                         clock-names = "ahb", "mod";
 420                         dmas = <&dma 1 29>, <&dma 1 28>;
 421                         dma-names = "rx", "tx";
 422                         status = "disabled";
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                 };
 426
 427                 intc: interrupt-controller@01c20400 {
 428                         compatible = "allwinner,sun4i-a10-ic";
 429                         reg = <0x01c20400 0x400>;
 430                         interrupt-controller;
 431                         #interrupt-cells = <1>;
 432                 };
 433
 434                 pio: pinctrl@01c20800 {
 435                         compatible = "allwinner,sun5i-a10s-pinctrl";
 436                         reg = <0x01c20800 0x400>;
 437                         interrupts = <28>;
 438                         clocks = <&apb0_gates 5>;
 439                         gpio-controller;
 440                         interrupt-controller;
 441                         #interrupt-cells = <2>;
 442                         #size-cells = <0>;
 443                         #gpio-cells = <3>;
 444
 445                         uart0_pins_a: uart0@0 {
 446                                 allwinner,pins = "PB19", "PB20";
 447                                 allwinner,function = "uart0";
 448                                 allwinner,drive = <0>;
 449                                 allwinner,pull = <0>;
 450                         };
 451
 452                         uart2_pins_a: uart2@0 {
 453                                 allwinner,pins = "PC18", "PC19";
 454                                 allwinner,function = "uart2";
 455                                 allwinner,drive = <0>;
 456                                 allwinner,pull = <0>;
 457                         };
 458
 459                         uart3_pins_a: uart3@0 {
 460                                 allwinner,pins = "PG9", "PG10";
 461                                 allwinner,function = "uart3";
 462                                 allwinner,drive = <0>;
 463                                 allwinner,pull = <0>;
 464                         };
 465
 466                         emac_pins_a: emac0@0 {
 467                                 allwinner,pins = "PA0", "PA1", "PA2",
 468                                                 "PA3", "PA4", "PA5", "PA6",
 469                                                 "PA7", "PA8", "PA9", "PA10",
 470                                                 "PA11", "PA12", "PA13", "PA14",
 471                                                 "PA15", "PA16";
 472                                 allwinner,function = "emac";
 473                                 allwinner,drive = <0>;
 474                                 allwinner,pull = <0>;
 475                         };
 476
 477                         i2c0_pins_a: i2c0@0 {
 478                                 allwinner,pins = "PB0", "PB1";
 479                                 allwinner,function = "i2c0";
 480                                 allwinner,drive = <0>;
 481                                 allwinner,pull = <0>;
 482                         };
 483
 484                         i2c1_pins_a: i2c1@0 {
 485                                 allwinner,pins = "PB15", "PB16";
 486                                 allwinner,function = "i2c1";
 487                                 allwinner,drive = <0>;
 488                                 allwinner,pull = <0>;
 489                         };
 490
 491                         i2c2_pins_a: i2c2@0 {
 492                                 allwinner,pins = "PB17", "PB18";
 493                                 allwinner,function = "i2c2";
 494                                 allwinner,drive = <0>;
 495                                 allwinner,pull = <0>;
 496                         };
 497
 498                         mmc0_pins_a: mmc0@0 {
 499                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 500                                 allwinner,function = "mmc0";
 501                                 allwinner,drive = <2>;
 502                                 allwinner,pull = <0>;
 503                         };
 504
 505                         mmc1_pins_a: mmc1@0 {
 506                                 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
 507                                 allwinner,function = "mmc1";
 508                                 allwinner,drive = <2>;
 509                                 allwinner,pull = <0>;
 510                         };
 511                 };
 512
 513                 timer@01c20c00 {
 514                         compatible = "allwinner,sun4i-a10-timer";
 515                         reg = <0x01c20c00 0x90>;
 516                         interrupts = <22>;
 517                         clocks = <&osc24M>;
 518                 };
 519
 520                 wdt: watchdog@01c20c90 {
 521                         compatible = "allwinner,sun4i-a10-wdt";
 522                         reg = <0x01c20c90 0x10>;
 523                 };
 524
 525                 sid: eeprom@01c23800 {
 526                         compatible = "allwinner,sun4i-a10-sid";
 527                         reg = <0x01c23800 0x10>;
 528                 };
 529
 530                 rtp: rtp@01c25000 {
 531                         compatible = "allwinner,sun4i-a10-ts";
 532                         reg = <0x01c25000 0x100>;
 533                         interrupts = <29>;
 534                 };
 535
 536                 uart0: serial@01c28000 {
 537                         compatible = "snps,dw-apb-uart";
 538                         reg = <0x01c28000 0x400>;
 539                         interrupts = <1>;
 540                         reg-shift = <2>;
 541                         reg-io-width = <4>;
 542                         clocks = <&apb1_gates 16>;
 543                         status = "disabled";
 544                 };
 545
 546                 uart1: serial@01c28400 {
 547                         compatible = "snps,dw-apb-uart";
 548                         reg = <0x01c28400 0x400>;
 549                         interrupts = <2>;
 550                         reg-shift = <2>;
 551                         reg-io-width = <4>;
 552                         clocks = <&apb1_gates 17>;
 553                         status = "disabled";
 554                 };
 555
 556                 uart2: serial@01c28800 {
 557                         compatible = "snps,dw-apb-uart";
 558                         reg = <0x01c28800 0x400>;
 559                         interrupts = <3>;
 560                         reg-shift = <2>;
 561                         reg-io-width = <4>;
 562                         clocks = <&apb1_gates 18>;
 563                         status = "disabled";
 564                 };
 565
 566                 uart3: serial@01c28c00 {
 567                         compatible = "snps,dw-apb-uart";
 568                         reg = <0x01c28c00 0x400>;
 569                         interrupts = <4>;
 570                         reg-shift = <2>;
 571                         reg-io-width = <4>;
 572                         clocks = <&apb1_gates 19>;
 573                         status = "disabled";
 574                 };
 575
 576                 i2c0: i2c@01c2ac00 {
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 580                         reg = <0x01c2ac00 0x400>;
 581                         interrupts = <7>;
 582                         clocks = <&apb1_gates 0>;
 583                         status = "disabled";
 584                 };
 585
 586                 i2c1: i2c@01c2b000 {
 587                         #address-cells = <1>;
 588                         #size-cells = <0>;
 589                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 590                         reg = <0x01c2b000 0x400>;
 591                         interrupts = <8>;
 592                         clocks = <&apb1_gates 1>;
 593                         status = "disabled";
 594                 };
 595
 596                 i2c2: i2c@01c2b400 {
 597                         #address-cells = <1>;
 598                         #size-cells = <0>;
 599                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 600                         reg = <0x01c2b400 0x400>;
 601                         interrupts = <9>;
 602                         clocks = <&apb1_gates 2>;
 603                         status = "disabled";
 604                 };
 605
 606                 timer@01c60000 {
 607                         compatible = "allwinner,sun5i-a13-hstimer";
 608                         reg = <0x01c60000 0x1000>;
 609                         interrupts = <82>, <83>;
 610                         clocks = <&ahb_gates 28>;
 611                 };
 612         };
 613 };