arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         aliases {
  19                 ethernet0 = &emac;
  20         };
  21
  22         chosen {
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 ranges;
  26
  27                 framebuffer@0 {
  28                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  29                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  30                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  31                                  <&ahb_gates 44>;
  32                         status = "disabled";
  33                 };
  34
  35                 framebuffer@1 {
  36                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  37                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  38                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  39                                  <&ahb_gates 44>, <&ahb_gates 46>;
  40                         status = "disabled";
  41                 };
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a8";
  50                         reg = <0x0>;
  51                 };
  52         };
  53
  54         memory {
  55                 reg = <0x40000000 0x80000000>;
  56         };
  57
  58         clocks {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 /*
  64                  * This is a dummy clock, to be used as placeholder on
  65                  * other mux clocks when a specific parent clock is not
  66                  * yet implemented. It should be dropped when the driver
  67                  * is complete.
  68                  */
  69                 dummy: dummy {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-clock";
  72                         clock-frequency = <0>;
  73                 };
  74
  75                 osc24M: clk@01c20050 {
  76                         #clock-cells = <0>;
  77                         compatible = "allwinner,sun4i-a10-osc-clk";
  78                         reg = <0x01c20050 0x4>;
  79                         clock-frequency = <24000000>;
  80                         clock-output-names = "osc24M";
  81                 };
  82
  83                 osc32k: clk@0 {
  84                         #clock-cells = <0>;
  85                         compatible = "fixed-clock";
  86                         clock-frequency = <32768>;
  87                         clock-output-names = "osc32k";
  88                 };
  89
  90                 pll1: clk@01c20000 {
  91                         #clock-cells = <0>;
  92                         compatible = "allwinner,sun4i-a10-pll1-clk";
  93                         reg = <0x01c20000 0x4>;
  94                         clocks = <&osc24M>;
  95                         clock-output-names = "pll1";
  96                 };
  97
  98                 pll4: clk@01c20018 {
  99                         #clock-cells = <0>;
 100                         compatible = "allwinner,sun4i-a10-pll1-clk";
 101                         reg = <0x01c20018 0x4>;
 102                         clocks = <&osc24M>;
 103                         clock-output-names = "pll4";
 104                 };
 105
 106                 pll5: clk@01c20020 {
 107                         #clock-cells = <1>;
 108                         compatible = "allwinner,sun4i-a10-pll5-clk";
 109                         reg = <0x01c20020 0x4>;
 110                         clocks = <&osc24M>;
 111                         clock-output-names = "pll5_ddr", "pll5_other";
 112                 };
 113
 114                 pll6: clk@01c20028 {
 115                         #clock-cells = <1>;
 116                         compatible = "allwinner,sun4i-a10-pll6-clk";
 117                         reg = <0x01c20028 0x4>;
 118                         clocks = <&osc24M>;
 119                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 120                 };
 121
 122                 /* dummy is 200M */
 123                 cpu: cpu@01c20054 {
 124                         #clock-cells = <0>;
 125                         compatible = "allwinner,sun4i-a10-cpu-clk";
 126                         reg = <0x01c20054 0x4>;
 127                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 128                         clock-output-names = "cpu";
 129                 };
 130
 131                 axi: axi@01c20054 {
 132                         #clock-cells = <0>;
 133                         compatible = "allwinner,sun4i-a10-axi-clk";
 134                         reg = <0x01c20054 0x4>;
 135                         clocks = <&cpu>;
 136                         clock-output-names = "axi";
 137                 };
 138
 139                 axi_gates: clk@01c2005c {
 140                         #clock-cells = <1>;
 141                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 142                         reg = <0x01c2005c 0x4>;
 143                         clocks = <&axi>;
 144                         clock-output-names = "axi_dram";
 145                 };
 146
 147                 ahb: ahb@01c20054 {
 148                         #clock-cells = <0>;
 149                         compatible = "allwinner,sun4i-a10-ahb-clk";
 150                         reg = <0x01c20054 0x4>;
 151                         clocks = <&axi>;
 152                         clock-output-names = "ahb";
 153                 };
 154
 155                 ahb_gates: clk@01c20060 {
 156                         #clock-cells = <1>;
 157                         compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 158                         reg = <0x01c20060 0x8>;
 159                         clocks = <&ahb>;
 160                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 161                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 162                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 163                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 164                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 165                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 166                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 167                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 168                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 169                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 170                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 171                 };
 172
 173                 apb0: apb0@01c20054 {
 174                         #clock-cells = <0>;
 175                         compatible = "allwinner,sun4i-a10-apb0-clk";
 176                         reg = <0x01c20054 0x4>;
 177                         clocks = <&ahb>;
 178                         clock-output-names = "apb0";
 179                 };
 180
 181                 apb0_gates: clk@01c20068 {
 182                         #clock-cells = <1>;
 183                         compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 184                         reg = <0x01c20068 0x4>;
 185                         clocks = <&apb0>;
 186                         clock-output-names = "apb0_codec", "apb0_spdif",
 187                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 188                                 "apb0_ir1", "apb0_keypad";
 189                 };
 190
 191                 apb1: clk@01c20058 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun4i-a10-apb1-clk";
 194                         reg = <0x01c20058 0x4>;
 195                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 196                         clock-output-names = "apb1";
 197                 };
 198
 199                 apb1_gates: clk@01c2006c {
 200                         #clock-cells = <1>;
 201                         compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 202                         reg = <0x01c2006c 0x4>;
 203                         clocks = <&apb1>;
 204                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 205                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 206                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 207                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 208                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 209                                 "apb1_uart7";
 210                 };
 211
 212                 nand_clk: clk@01c20080 {
 213                         #clock-cells = <0>;
 214                         compatible = "allwinner,sun4i-a10-mod0-clk";
 215                         reg = <0x01c20080 0x4>;
 216                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 217                         clock-output-names = "nand";
 218                 };
 219
 220                 ms_clk: clk@01c20084 {
 221                         #clock-cells = <0>;
 222                         compatible = "allwinner,sun4i-a10-mod0-clk";
 223                         reg = <0x01c20084 0x4>;
 224                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 225                         clock-output-names = "ms";
 226                 };
 227
 228                 mmc0_clk: clk@01c20088 {
 229                         #clock-cells = <0>;
 230                         compatible = "allwinner,sun4i-a10-mod0-clk";
 231                         reg = <0x01c20088 0x4>;
 232                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 233                         clock-output-names = "mmc0";
 234                 };
 235
 236                 mmc1_clk: clk@01c2008c {
 237                         #clock-cells = <0>;
 238                         compatible = "allwinner,sun4i-a10-mod0-clk";
 239                         reg = <0x01c2008c 0x4>;
 240                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 241                         clock-output-names = "mmc1";
 242                 };
 243
 244                 mmc2_clk: clk@01c20090 {
 245                         #clock-cells = <0>;
 246                         compatible = "allwinner,sun4i-a10-mod0-clk";
 247                         reg = <0x01c20090 0x4>;
 248                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 249                         clock-output-names = "mmc2";
 250                 };
 251
 252                 mmc3_clk: clk@01c20094 {
 253                         #clock-cells = <0>;
 254                         compatible = "allwinner,sun4i-a10-mod0-clk";
 255                         reg = <0x01c20094 0x4>;
 256                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 257                         clock-output-names = "mmc3";
 258                 };
 259
 260                 ts_clk: clk@01c20098 {
 261                         #clock-cells = <0>;
 262                         compatible = "allwinner,sun4i-a10-mod0-clk";
 263                         reg = <0x01c20098 0x4>;
 264                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 265                         clock-output-names = "ts";
 266                 };
 267
 268                 ss_clk: clk@01c2009c {
 269                         #clock-cells = <0>;
 270                         compatible = "allwinner,sun4i-a10-mod0-clk";
 271                         reg = <0x01c2009c 0x4>;
 272                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 273                         clock-output-names = "ss";
 274                 };
 275
 276                 spi0_clk: clk@01c200a0 {
 277                         #clock-cells = <0>;
 278                         compatible = "allwinner,sun4i-a10-mod0-clk";
 279                         reg = <0x01c200a0 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "spi0";
 282                 };
 283
 284                 spi1_clk: clk@01c200a4 {
 285                         #clock-cells = <0>;
 286                         compatible = "allwinner,sun4i-a10-mod0-clk";
 287                         reg = <0x01c200a4 0x4>;
 288                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 289                         clock-output-names = "spi1";
 290                 };
 291
 292                 spi2_clk: clk@01c200a8 {
 293                         #clock-cells = <0>;
 294                         compatible = "allwinner,sun4i-a10-mod0-clk";
 295                         reg = <0x01c200a8 0x4>;
 296                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 297                         clock-output-names = "spi2";
 298                 };
 299
 300                 pata_clk: clk@01c200ac {
 301                         #clock-cells = <0>;
 302                         compatible = "allwinner,sun4i-a10-mod0-clk";
 303                         reg = <0x01c200ac 0x4>;
 304                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 305                         clock-output-names = "pata";
 306                 };
 307
 308                 ir0_clk: clk@01c200b0 {
 309                         #clock-cells = <0>;
 310                         compatible = "allwinner,sun4i-a10-mod0-clk";
 311                         reg = <0x01c200b0 0x4>;
 312                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 313                         clock-output-names = "ir0";
 314                 };
 315
 316                 ir1_clk: clk@01c200b4 {
 317                         #clock-cells = <0>;
 318                         compatible = "allwinner,sun4i-a10-mod0-clk";
 319                         reg = <0x01c200b4 0x4>;
 320                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 321                         clock-output-names = "ir1";
 322                 };
 323
 324                 usb_clk: clk@01c200cc {
 325                         #clock-cells = <1>;
 326                         #reset-cells = <1>;
 327                         compatible = "allwinner,sun4i-a10-usb-clk";
 328                         reg = <0x01c200cc 0x4>;
 329                         clocks = <&pll6 1>;
 330                         clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
 331                 };
 332
 333                 spi3_clk: clk@01c200d4 {
 334                         #clock-cells = <0>;
 335                         compatible = "allwinner,sun4i-a10-mod0-clk";
 336                         reg = <0x01c200d4 0x4>;
 337                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 338                         clock-output-names = "spi3";
 339                 };
 340         };
 341
 342         soc@01c00000 {
 343                 compatible = "simple-bus";
 344                 #address-cells = <1>;
 345                 #size-cells = <1>;
 346                 ranges;
 347
 348                 dma: dma-controller@01c02000 {
 349                         compatible = "allwinner,sun4i-a10-dma";
 350                         reg = <0x01c02000 0x1000>;
 351                         interrupts = <27>;
 352                         clocks = <&ahb_gates 6>;
 353                         #dma-cells = <2>;
 354                 };
 355
 356                 spi0: spi@01c05000 {
 357                         compatible = "allwinner,sun4i-a10-spi";
 358                         reg = <0x01c05000 0x1000>;
 359                         interrupts = <10>;
 360                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 361                         clock-names = "ahb", "mod";
 362                         dmas = <&dma 1 27>, <&dma 1 26>;
 363                         dma-names = "rx", "tx";
 364                         status = "disabled";
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                 };
 368
 369                 spi1: spi@01c06000 {
 370                         compatible = "allwinner,sun4i-a10-spi";
 371                         reg = <0x01c06000 0x1000>;
 372                         interrupts = <11>;
 373                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 374                         clock-names = "ahb", "mod";
 375                         dmas = <&dma 1 9>, <&dma 1 8>;
 376                         dma-names = "rx", "tx";
 377                         status = "disabled";
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                 };
 381
 382                 emac: ethernet@01c0b000 {
 383                         compatible = "allwinner,sun4i-a10-emac";
 384                         reg = <0x01c0b000 0x1000>;
 385                         interrupts = <55>;
 386                         clocks = <&ahb_gates 17>;
 387                         status = "disabled";
 388                 };
 389
 390                 mdio@01c0b080 {
 391                         compatible = "allwinner,sun4i-a10-mdio";
 392                         reg = <0x01c0b080 0x14>;
 393                         status = "disabled";
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                 };
 397
 398                 mmc0: mmc@01c0f000 {
 399                         compatible = "allwinner,sun4i-a10-mmc";
 400                         reg = <0x01c0f000 0x1000>;
 401                         clocks = <&ahb_gates 8>, <&mmc0_clk>;
 402                         clock-names = "ahb", "mmc";
 403                         interrupts = <32>;
 404                         status = "disabled";
 405                 };
 406
 407                 mmc1: mmc@01c10000 {
 408                         compatible = "allwinner,sun4i-a10-mmc";
 409                         reg = <0x01c10000 0x1000>;
 410                         clocks = <&ahb_gates 9>, <&mmc1_clk>;
 411                         clock-names = "ahb", "mmc";
 412                         interrupts = <33>;
 413                         status = "disabled";
 414                 };
 415
 416                 mmc2: mmc@01c11000 {
 417                         compatible = "allwinner,sun4i-a10-mmc";
 418                         reg = <0x01c11000 0x1000>;
 419                         clocks = <&ahb_gates 10>, <&mmc2_clk>;
 420                         clock-names = "ahb", "mmc";
 421                         interrupts = <34>;
 422                         status = "disabled";
 423                 };
 424
 425                 mmc3: mmc@01c12000 {
 426                         compatible = "allwinner,sun4i-a10-mmc";
 427                         reg = <0x01c12000 0x1000>;
 428                         clocks = <&ahb_gates 11>, <&mmc3_clk>;
 429                         clock-names = "ahb", "mmc";
 430                         interrupts = <35>;
 431                         status = "disabled";
 432                 };
 433
 434                 usbphy: phy@01c13400 {
 435                         #phy-cells = <1>;
 436                         compatible = "allwinner,sun4i-a10-usb-phy";
 437                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 438                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 439                         clocks = <&usb_clk 8>;
 440                         clock-names = "usb_phy";
 441                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 442                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 443                         status = "disabled";
 444                 };
 445
 446                 ehci0: usb@01c14000 {
 447                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 448                         reg = <0x01c14000 0x100>;
 449                         interrupts = <39>;
 450                         clocks = <&ahb_gates 1>;
 451                         phys = <&usbphy 1>;
 452                         phy-names = "usb";
 453                         status = "disabled";
 454                 };
 455
 456                 ohci0: usb@01c14400 {
 457                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 458                         reg = <0x01c14400 0x100>;
 459                         interrupts = <64>;
 460                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 461                         phys = <&usbphy 1>;
 462                         phy-names = "usb";
 463                         status = "disabled";
 464                 };
 465
 466                 spi2: spi@01c17000 {
 467                         compatible = "allwinner,sun4i-a10-spi";
 468                         reg = <0x01c17000 0x1000>;
 469                         interrupts = <12>;
 470                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 471                         clock-names = "ahb", "mod";
 472                         dmas = <&dma 1 29>, <&dma 1 28>;
 473                         dma-names = "rx", "tx";
 474                         status = "disabled";
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                 };
 478
 479                 ahci: sata@01c18000 {
 480                         compatible = "allwinner,sun4i-a10-ahci";
 481                         reg = <0x01c18000 0x1000>;
 482                         interrupts = <56>;
 483                         clocks = <&pll6 0>, <&ahb_gates 25>;
 484                         status = "disabled";
 485                 };
 486
 487                 ehci1: usb@01c1c000 {
 488                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 489                         reg = <0x01c1c000 0x100>;
 490                         interrupts = <40>;
 491                         clocks = <&ahb_gates 3>;
 492                         phys = <&usbphy 2>;
 493                         phy-names = "usb";
 494                         status = "disabled";
 495                 };
 496
 497                 ohci1: usb@01c1c400 {
 498                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 499                         reg = <0x01c1c400 0x100>;
 500                         interrupts = <65>;
 501                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 502                         phys = <&usbphy 2>;
 503                         phy-names = "usb";
 504                         status = "disabled";
 505                 };
 506
 507                 spi3: spi@01c1f000 {
 508                         compatible = "allwinner,sun4i-a10-spi";
 509                         reg = <0x01c1f000 0x1000>;
 510                         interrupts = <50>;
 511                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 512                         clock-names = "ahb", "mod";
 513                         dmas = <&dma 1 31>, <&dma 1 30>;
 514                         dma-names = "rx", "tx";
 515                         status = "disabled";
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518                 };
 519
 520                 intc: interrupt-controller@01c20400 {
 521                         compatible = "allwinner,sun4i-a10-ic";
 522                         reg = <0x01c20400 0x400>;
 523                         interrupt-controller;
 524                         #interrupt-cells = <1>;
 525                 };
 526
 527                 pio: pinctrl@01c20800 {
 528                         compatible = "allwinner,sun4i-a10-pinctrl";
 529                         reg = <0x01c20800 0x400>;
 530                         interrupts = <28>;
 531                         clocks = <&apb0_gates 5>;
 532                         gpio-controller;
 533                         interrupt-controller;
 534                         #interrupt-cells = <2>;
 535                         #size-cells = <0>;
 536                         #gpio-cells = <3>;
 537
 538                         pwm0_pins_a: pwm0@0 {
 539                                 allwinner,pins = "PB2";
 540                                 allwinner,function = "pwm";
 541                                 allwinner,drive = <0>;
 542                                 allwinner,pull = <0>;
 543                         };
 544
 545                         pwm1_pins_a: pwm1@0 {
 546                                 allwinner,pins = "PI3";
 547                                 allwinner,function = "pwm";
 548                                 allwinner,drive = <0>;
 549                                 allwinner,pull = <0>;
 550                         };
 551
 552                         uart0_pins_a: uart0@0 {
 553                                 allwinner,pins = "PB22", "PB23";
 554                                 allwinner,function = "uart0";
 555                                 allwinner,drive = <0>;
 556                                 allwinner,pull = <0>;
 557                         };
 558
 559                         uart0_pins_b: uart0@1 {
 560                                 allwinner,pins = "PF2", "PF4";
 561                                 allwinner,function = "uart0";
 562                                 allwinner,drive = <0>;
 563                                 allwinner,pull = <0>;
 564                         };
 565
 566                         uart1_pins_a: uart1@0 {
 567                                 allwinner,pins = "PA10", "PA11";
 568                                 allwinner,function = "uart1";
 569                                 allwinner,drive = <0>;
 570                                 allwinner,pull = <0>;
 571                         };
 572
 573                         i2c0_pins_a: i2c0@0 {
 574                                 allwinner,pins = "PB0", "PB1";
 575                                 allwinner,function = "i2c0";
 576                                 allwinner,drive = <0>;
 577                                 allwinner,pull = <0>;
 578                         };
 579
 580                         i2c1_pins_a: i2c1@0 {
 581                                 allwinner,pins = "PB18", "PB19";
 582                                 allwinner,function = "i2c1";
 583                                 allwinner,drive = <0>;
 584                                 allwinner,pull = <0>;
 585                         };
 586
 587                         i2c2_pins_a: i2c2@0 {
 588                                 allwinner,pins = "PB20", "PB21";
 589                                 allwinner,function = "i2c2";
 590                                 allwinner,drive = <0>;
 591                                 allwinner,pull = <0>;
 592                         };
 593
 594                         emac_pins_a: emac0@0 {
 595                                 allwinner,pins = "PA0", "PA1", "PA2",
 596                                                 "PA3", "PA4", "PA5", "PA6",
 597                                                 "PA7", "PA8", "PA9", "PA10",
 598                                                 "PA11", "PA12", "PA13", "PA14",
 599                                                 "PA15", "PA16";
 600                                 allwinner,function = "emac";
 601                                 allwinner,drive = <0>;
 602                                 allwinner,pull = <0>;
 603                         };
 604
 605                         mmc0_pins_a: mmc0@0 {
 606                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 607                                 allwinner,function = "mmc0";
 608                                 allwinner,drive = <2>;
 609                                 allwinner,pull = <0>;
 610                         };
 611
 612                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 613                                 allwinner,pins = "PH1";
 614                                 allwinner,function = "gpio_in";
 615                                 allwinner,drive = <0>;
 616                                 allwinner,pull = <1>;
 617                         };
 618
 619                         ir0_pins_a: ir0@0 {
 620                                 allwinner,pins = "PB3","PB4";
 621                                 allwinner,function = "ir0";
 622                                 allwinner,drive = <0>;
 623                                 allwinner,pull = <0>;
 624                         };
 625
 626                         ir1_pins_a: ir1@0 {
 627                                 allwinner,pins = "PB22","PB23";
 628                                 allwinner,function = "ir1";
 629                                 allwinner,drive = <0>;
 630                                 allwinner,pull = <0>;
 631                         };
 632                 };
 633
 634                 timer@01c20c00 {
 635                         compatible = "allwinner,sun4i-a10-timer";
 636                         reg = <0x01c20c00 0x90>;
 637                         interrupts = <22>;
 638                         clocks = <&osc24M>;
 639                 };
 640
 641                 wdt: watchdog@01c20c90 {
 642                         compatible = "allwinner,sun4i-a10-wdt";
 643                         reg = <0x01c20c90 0x10>;
 644                 };
 645
 646                 rtc: rtc@01c20d00 {
 647                         compatible = "allwinner,sun4i-a10-rtc";
 648                         reg = <0x01c20d00 0x20>;
 649                         interrupts = <24>;
 650                 };
 651
 652                 pwm: pwm@01c20e00 {
 653                         compatible = "allwinner,sun4i-a10-pwm";
 654                         reg = <0x01c20e00 0xc>;
 655                         clocks = <&osc24M>;
 656                         #pwm-cells = <3>;
 657                         status = "disabled";
 658                 };
 659
 660                 ir0: ir@01c21800 {
 661                         compatible = "allwinner,sun4i-a10-ir";
 662                         clocks = <&apb0_gates 6>, <&ir0_clk>;
 663                         clock-names = "apb", "ir";
 664                         interrupts = <5>;
 665                         reg = <0x01c21800 0x40>;
 666                         status = "disabled";
 667                 };
 668
 669                 ir1: ir@01c21c00 {
 670                         compatible = "allwinner,sun4i-a10-ir";
 671                         clocks = <&apb0_gates 7>, <&ir1_clk>;
 672                         clock-names = "apb", "ir";
 673                         interrupts = <6>;
 674                         reg = <0x01c21c00 0x40>;
 675                         status = "disabled";
 676                 };
 677
 678                 sid: eeprom@01c23800 {
 679                         compatible = "allwinner,sun4i-a10-sid";
 680                         reg = <0x01c23800 0x10>;
 681                 };
 682
 683                 rtp: rtp@01c25000 {
 684                         compatible = "allwinner,sun4i-a10-ts";
 685                         reg = <0x01c25000 0x100>;
 686                         interrupts = <29>;
 687                 };
 688
 689                 uart0: serial@01c28000 {
 690                         compatible = "snps,dw-apb-uart";
 691                         reg = <0x01c28000 0x400>;
 692                         interrupts = <1>;
 693                         reg-shift = <2>;
 694                         reg-io-width = <4>;
 695                         clocks = <&apb1_gates 16>;
 696                         status = "disabled";
 697                 };
 698
 699                 uart1: serial@01c28400 {
 700                         compatible = "snps,dw-apb-uart";
 701                         reg = <0x01c28400 0x400>;
 702                         interrupts = <2>;
 703                         reg-shift = <2>;
 704                         reg-io-width = <4>;
 705                         clocks = <&apb1_gates 17>;
 706                         status = "disabled";
 707                 };
 708
 709                 uart2: serial@01c28800 {
 710                         compatible = "snps,dw-apb-uart";
 711                         reg = <0x01c28800 0x400>;
 712                         interrupts = <3>;
 713                         reg-shift = <2>;
 714                         reg-io-width = <4>;
 715                         clocks = <&apb1_gates 18>;
 716                         status = "disabled";
 717                 };
 718
 719                 uart3: serial@01c28c00 {
 720                         compatible = "snps,dw-apb-uart";
 721                         reg = <0x01c28c00 0x400>;
 722                         interrupts = <4>;
 723                         reg-shift = <2>;
 724                         reg-io-width = <4>;
 725                         clocks = <&apb1_gates 19>;
 726                         status = "disabled";
 727                 };
 728
 729                 uart4: serial@01c29000 {
 730                         compatible = "snps,dw-apb-uart";
 731                         reg = <0x01c29000 0x400>;
 732                         interrupts = <17>;
 733                         reg-shift = <2>;
 734                         reg-io-width = <4>;
 735                         clocks = <&apb1_gates 20>;
 736                         status = "disabled";
 737                 };
 738
 739                 uart5: serial@01c29400 {
 740                         compatible = "snps,dw-apb-uart";
 741                         reg = <0x01c29400 0x400>;
 742                         interrupts = <18>;
 743                         reg-shift = <2>;
 744                         reg-io-width = <4>;
 745                         clocks = <&apb1_gates 21>;
 746                         status = "disabled";
 747                 };
 748
 749                 uart6: serial@01c29800 {
 750                         compatible = "snps,dw-apb-uart";
 751                         reg = <0x01c29800 0x400>;
 752                         interrupts = <19>;
 753                         reg-shift = <2>;
 754                         reg-io-width = <4>;
 755                         clocks = <&apb1_gates 22>;
 756                         status = "disabled";
 757                 };
 758
 759                 uart7: serial@01c29c00 {
 760                         compatible = "snps,dw-apb-uart";
 761                         reg = <0x01c29c00 0x400>;
 762                         interrupts = <20>;
 763                         reg-shift = <2>;
 764                         reg-io-width = <4>;
 765                         clocks = <&apb1_gates 23>;
 766                         status = "disabled";
 767                 };
 768
 769                 i2c0: i2c@01c2ac00 {
 770                         compatible = "allwinner,sun4i-a10-i2c";
 771                         reg = <0x01c2ac00 0x400>;
 772                         interrupts = <7>;
 773                         clocks = <&apb1_gates 0>;
 774                         status = "disabled";
 775                         #address-cells = <1>;
 776                         #size-cells = <0>;
 777                 };
 778
 779                 i2c1: i2c@01c2b000 {
 780                         compatible = "allwinner,sun4i-a10-i2c";
 781                         reg = <0x01c2b000 0x400>;
 782                         interrupts = <8>;
 783                         clocks = <&apb1_gates 1>;
 784                         status = "disabled";
 785                         #address-cells = <1>;
 786                         #size-cells = <0>;
 787                 };
 788
 789                 i2c2: i2c@01c2b400 {
 790                         compatible = "allwinner,sun4i-a10-i2c";
 791                         reg = <0x01c2b400 0x400>;
 792                         interrupts = <9>;
 793                         clocks = <&apb1_gates 2>;
 794                         status = "disabled";
 795                         #address-cells = <1>;
 796                         #size-cells = <0>;
 797                 };
 798         };
 799 };